2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # JTAG protocol decoder
23 import sigrokdecode as srd
26 Protocol output format:
29 [<packet-type>, <data>]
31 <packet-type> is one of:
32 - 'NEW STATE': <data> is the new state of the JTAG state machine.
33 Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
34 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
35 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
36 'EXIT2-IR', 'UPDATE-IR'.
37 - 'IR TDI': Bitstring that was clocked into the IR register.
38 - 'IR TDO': Bitstring that was clocked out of the IR register.
39 - 'DR TDI': Bitstring that was clocked into the DR register.
40 - 'DR TDO': Bitstring that was clocked out of the DR register.
43 All bitstrings are a sequence of '1' and '0' characters. The right-most
44 character in the bitstring is the LSB. Example: '01110001' (1 is LSB).
49 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
51 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
52 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
54 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
55 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
58 def get_annotation_classes():
61 l.append([s.lower(), s])
64 class Decoder(srd.Decoder):
68 longname = 'Joint Test Action Group (IEEE 1149.1)'
69 desc = 'Protocol for testing, debugging, and flashing ICs.'
74 {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
75 {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
76 {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
77 {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
80 {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
81 {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
82 {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
85 annotations = get_annotation_classes()
87 def __init__(self, **kwargs):
88 # self.state = 'TEST-LOGIC-RESET'
89 self.state = 'RUN-TEST/IDLE'
91 self.oldpins = (-1, -1, -1, -1)
96 self.ss_item = self.es_item = None
97 self.saved_item = None
101 self.out_proto = self.register(srd.OUTPUT_PYTHON)
102 self.out_ann = self.register(srd.OUTPUT_ANN)
104 def putx(self, data):
105 self.put(self.ss_item, self.es_item, self.out_ann, data)
107 def putp(self, data):
108 self.put(self.ss_item, self.es_item, self.out_proto, data)
110 def advance_state_machine(self, tms):
111 self.oldstate = self.state
114 if self.state == 'TEST-LOGIC-RESET':
115 self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
116 elif self.state == 'RUN-TEST/IDLE':
117 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
120 elif self.state == 'SELECT-DR-SCAN':
121 self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
122 elif self.state == 'CAPTURE-DR':
123 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
124 elif self.state == 'SHIFT-DR':
125 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
126 elif self.state == 'EXIT1-DR':
127 self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
128 elif self.state == 'PAUSE-DR':
129 self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
130 elif self.state == 'EXIT2-DR':
131 self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
132 elif self.state == 'UPDATE-DR':
133 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
136 elif self.state == 'SELECT-IR-SCAN':
137 self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
138 elif self.state == 'CAPTURE-IR':
139 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
140 elif self.state == 'SHIFT-IR':
141 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
142 elif self.state == 'EXIT1-IR':
143 self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
144 elif self.state == 'PAUSE-IR':
145 self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
146 elif self.state == 'EXIT2-IR':
147 self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
148 elif self.state == 'UPDATE-IR':
149 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
152 raise Exception('Invalid state: %s' % self.state)
154 def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
155 # Rising TCK edges always advance the state machine.
156 self.advance_state_machine(tms)
158 if self.first == True:
159 # Save the start sample and item for later (no output yet).
160 self.ss_item = self.samplenum
162 self.saved_item = self.state
164 # Output the saved item (from the last CLK edge to the current).
165 self.es_item = self.samplenum
166 # Output the state we just switched to.
167 self.putx([jtag_states.index(self.state), [self.state]])
168 self.putp(['NEW STATE', self.state])
169 self.ss_item = self.samplenum
170 self.saved_item = self.state
172 # If we went from SHIFT-IR to SHIFT-IR, or SHIFT-DR to SHIFT-DR,
173 # collect the current TDI/TDO values (upon rising TCK edge).
174 if self.state.startswith('SHIFT-') and self.oldstate == self.state:
175 self.bits_tdi.insert(0, tdi)
176 self.bits_tdo.insert(0, tdo)
177 # TODO: ANN/PROTO output.
178 # self.putx([0, ['TDI add: ' + str(tdi)]])
179 # self.putp([0, ['TDO add: ' + str(tdo)]])
181 # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
182 if self.oldstate.startswith('SHIFT-') and \
183 self.state.startswith('EXIT1-'):
185 t = self.state[-2:] + ' TDI'
186 b = ''.join(map(str, self.bits_tdi))
187 h = ' (0x%x' % int('0b' + b, 2) + ')'
188 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits'
189 # self.putx([0, [s]])
193 t = self.state[-2:] + ' TDO'
194 b = ''.join(map(str, self.bits_tdo))
195 h = ' (0x%x' % int('0b' + b, 2) + ')'
196 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits'
197 # self.putx([0, [s]])
201 def decode(self, ss, es, data):
202 for (self.samplenum, pins) in data:
204 # If none of the pins changed, there's nothing to do.
205 if self.oldpins == pins:
208 # Store current pin values for the next round.
211 # Get individual pin values into local variables.
212 # Unused probes will have a value of > 1.
213 (tdi, tdo, tck, tms, trst, srst, rtck) = pins
215 # We only care about TCK edges (either rising or falling).
216 if (self.oldtck == tck):
219 # Store start/end sample for later usage.
220 self.ss, self.es = ss, es
222 # self.putx([0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \
223 # % (tdi, tdo, tck, tms)]])
225 if (self.oldtck == 0 and tck == 1):
226 self.handle_rising_tck_edge(tdi, tdo, tck, tms)