2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # JTAG protocol decoder
23 import sigrokdecode as srd
25 class Decoder(srd.Decoder):
29 longname = 'Joint Test Action Group'
30 desc = 'Protocol for testing, debugging, and flashing ICs.'
35 {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
36 {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
37 {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
38 {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
41 # {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
42 # {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
46 ['ASCII', 'TODO: description'],
49 def __init__(self, **kwargs):
50 # self.state = 'TEST-LOGIC-RESET'
51 self.state = 'RUN-TEST/IDLE'
53 self.oldpins = (-1, -1, -1, -1)
58 def start(self, metadata):
59 self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag')
60 self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag')
65 def advance_state_machine(self, tms):
66 self.oldstate = self.state
69 if self.state == 'TEST-LOGIC-RESET':
70 self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
71 elif self.state == 'RUN-TEST/IDLE':
72 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
75 elif self.state == 'SELECT-DR-SCAN':
76 self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
77 elif self.state == 'CAPTURE-DR':
78 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
79 elif self.state == 'SHIFT-DR':
80 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
81 elif self.state == 'EXIT1-DR':
82 self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
83 elif self.state == 'PAUSE-DR':
84 self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
85 elif self.state == 'EXIT2-DR':
86 self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
87 elif self.state == 'UPDATE-DR':
88 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
91 elif self.state == 'SELECT-IR-SCAN':
92 self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
93 elif self.state == 'CAPTURE-IR':
94 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
95 elif self.state == 'SHIFT-IR':
96 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
97 elif self.state == 'EXIT1-IR':
98 self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
99 elif self.state == 'PAUSE-IR':
100 self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
101 elif self.state == 'EXIT2-IR':
102 self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
103 elif self.state == 'UPDATE-IR':
104 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
107 raise Exception('Invalid state: %s' % self.state)
109 def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
110 # Rising TCK edges always advance the state machine.
111 self.advance_state_machine(tms)
113 # Output the state we just switched to.
114 self.put(self.ss, self.es, self.out_ann,
115 [0, ['New state: %s' % self.state]])
116 self.put(self.ss, self.es, self.out_proto,
117 ['NEW STATE', self.state])
119 # If we went from SHIFT-IR to SHIFT-IR, or SHIFT-DR to SHIFT-DR,
120 # collect the current TDI/TDO values (upon rising TCK edge).
121 if self.state.startswith('SHIFT-') and self.oldstate == self.state:
122 self.bits_tdi.insert(0, tdi)
123 self.bits_tdo.insert(0, tdo)
124 # TODO: ANN/PROTO output.
125 # self.put(self.ss, self.es, self.out_ann,
126 # [0, ['TDI add: ' + str(tdi)]])
127 # self.put(self.ss, self.es, self.out_ann,
128 # [0, ['TDO add: ' + str(tdo)]])
130 # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
131 if self.oldstate.startswith('SHIFT-') and \
132 self.state.startswith('EXIT1-'):
134 t = self.state[-2:] + ' TDI'
135 b = ''.join(map(str, self.bits_tdi))
136 s = t + ': ' + b + ', ' + str(len(self.bits_tdi)) + ' bits'
137 self.put(self.ss, self.es, self.out_ann, [0, [s]])
138 self.put(self.ss, self.es, self.out_proto, [t, b])
141 t = self.state[-2:] + ' TDO'
142 b = ''.join(map(str, self.bits_tdo))
143 s = t + ': ' + b + ', ' + str(len(self.bits_tdo)) + ' bits'
144 self.put(self.ss, self.es, self.out_ann, [0, [s]])
145 self.put(self.ss, self.es, self.out_proto, [t, b])
148 def decode(self, ss, es, data):
149 for (samplenum, pins) in data:
151 # If none of the pins changed, there's nothing to do.
152 if self.oldpins == pins:
155 # Store current pin values for the next round.
158 # Get individual pin values into local variables.
159 # TODO: Handle optional pins (TRST, SRST).
160 (tdi, tdo, tck, tms) = pins
162 # We only care about TCK edges (either rising or falling).
163 if (self.oldtck == tck):
166 # Store start/end sample for later usage.
167 self.ss, self.es = ss, es
169 # self.put(self.ss, self.es, self.out_ann,
170 # [0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \
171 # % (tdi, tdo, tck, tms)]])
173 if (self.oldtck == 0 and tck == 1):
174 self.handle_rising_tck_edge(tdi, tdo, tck, tms)