2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # JTAG protocol decoder
23 import sigrokdecode as srd
25 class Decoder(srd.Decoder):
29 longname = 'Joint Test Action Group'
35 {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
36 {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
37 {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
38 {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
39 {'id': 'trst', 'name': 'TRST', 'desc': 'Test reset'},
41 optional_probes = [] # TODO? SRST?
44 ['ASCII', 'TODO: description'],
47 def __init__(self, **kwargs):
48 self.state = 'TEST-LOGIC-RESET'
49 self.oldpins = (-1, -1, -1, -1, -1)
54 def start(self, metadata):
55 self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag')
56 self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag')
61 def advance_state_machine(self, tms):
63 if self.state == 'TEST-LOGIC-RESET':
64 self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
65 elif self.state == 'RUN-TEST/IDLE':
66 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
69 elif self.state == 'SELECT-DR-SCAN':
70 self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
71 elif self.state == 'CAPTURE-DR':
72 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
73 elif self.state == 'SHIFT-DR':
74 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
75 elif self.state == 'EXIT1-DR':
76 self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
77 elif self.state == 'PAUSE-DR':
78 self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
79 elif self.state == 'EXIT2-DR':
80 self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
81 elif self.state == 'UPDATE-DR':
82 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
85 elif self.state == 'SELECT-IR-SCAN':
86 self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
87 elif self.state == 'CAPTURE-IR':
88 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
89 elif self.state == 'SHIFT-IR':
90 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
91 elif self.state == 'EXIT1-IR':
92 self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
93 elif self.state == 'PAUSE-IR':
94 self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
95 elif self.state == 'EXIT2-IR':
96 self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
97 elif self.state == 'UPDATE-IR':
98 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
101 raise Exception('Invalid state: %s' % self.state)
103 def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst):
104 # In SHIFT-DR/SHIFT-IR (on rising TCK edges) we collect TDI values.
105 if self.state in ('SHIFT-DR', 'SHIFT-IR'):
106 self.bits_tdi.append(tdi)
108 # Output all TDI bits.
109 elif self.state in ('EXIT1-DR', 'EXIT1-IR'):
110 s = self.state[-2:] + ' TDI: ' + ''.join(map(str, self.bits_tdi))
111 s += ', ' + str(len(self.bits_tdi)) + ' bits'
112 self.put(self.ss, self.es, self.out_ann, [0, [s]])
115 # Rising TCK edges always advance the state machine.
116 self.advance_state_machine(tms)
118 # Output the state we just switched to.
119 self.put(self.ss, self.es, self.out_ann,
120 [0, ['New state: %s' % self.state]])
122 def handle_falling_tck_edge(self, tdi, tdo, tck, tms, trst):
123 # In SHIFT-DR/SHIFT-IR (on falling TCK edges) we collect TDO values.
124 if self.state in ('SHIFT-DR', 'SHIFT-IR'):
125 self.bits_tdo.append(tdo)
127 # Output all TDO bits.
128 if self.state in ('EXIT1-DR', 'EXIT1-IR'):
129 s = self.state[-2:] + ' TDO: ' + ''.join(map(str, self.bits_tdo))
130 s += ', ' + str(len(self.bits_tdo)) + ' bits'
131 self.put(self.ss, self.es, self.out_ann, [0, [s]])
134 def decode(self, ss, es, data):
135 for (samplenum, pins) in data:
137 # If none of the pins changed, there's nothing to do.
138 if self.oldpins == pins:
141 # Store current pin values for the next round.
144 # Get individual pin values into local variables.
145 # TODO: Handle optional pins.
146 (tdi, tdo, tck, tms, trst) = pins
148 # We only care about TCK edges (either rising or falling).
149 if (self.oldtck == tck):
152 # Store start/end sample for later usage.
153 self.ss, self.es = ss, es
155 if (self.oldtck == 0 and tck == 1):
156 self.handle_rising_tck_edge(tdi, tdo, tck, tms, trst)
157 elif (self.oldtck == 1 and tck == 0):
158 self.handle_falling_tck_edge(tdi, tdo, tck, tms, trst)