2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2014 Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
23 # Helper dictionary for edge detection.
25 'rising': lambda x, y: bool(not x and y),
26 'falling': lambda x, y: bool(x and not y),
27 'both': lambda x, y: bool(x ^ y),
30 class SamplerateError(Exception):
33 class Decoder(srd.Decoder):
37 longname = 'Timing jitter calculation'
38 desc = 'Retrieves the timing jitter between two digital signals.'
43 {'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'},
44 {'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'},
47 {'id': 'clk_polarity', 'desc': 'Clock edge polarity',
48 'default': 'rising', 'values': ('rising', 'falling', 'both')},
49 {'id': 'sig_polarity', 'desc': 'Resulting signal edge polarity',
50 'default': 'rising', 'values': ('rising', 'falling', 'both')},
53 ('jitter', 'Jitter value'),
54 ('clk_missed', 'Clock missed'),
55 ('sig_missed', 'Signal missed'),
58 ('jitter', 'Jitter values', (0,)),
59 ('clk_missed', 'Clock missed', (1,)),
60 ('sig_missed', 'Signal missed', (2,)),
63 ('ascii-float', 'Jitter values as newline-separated ASCII floats'),
68 self.samplerate = None
69 self.oldclk, self.oldsig = 0, 0
76 self.clk_edge = edge_detector[self.options['clk_polarity']]
77 self.sig_edge = edge_detector[self.options['sig_polarity']]
78 self.out_ann = self.register(srd.OUTPUT_ANN)
79 self.out_binary = self.register(srd.OUTPUT_BINARY)
80 self.out_clk_missed = self.register(srd.OUTPUT_META,
81 meta=(int, 'Clock missed', 'Clock transition missed'))
82 self.out_sig_missed = self.register(srd.OUTPUT_META,
83 meta=(int, 'Signal missed', 'Resulting signal transition missed'))
85 def metadata(self, key, value):
86 if key == srd.SRD_CONF_SAMPLERATE:
87 self.samplerate = value
89 # Helper function for jitter time annotations.
90 def putx(self, delta):
92 if delta == 0 or delta >= 1:
93 delta_s = '%.1fs' % (delta)
95 delta_s = '%.1ffs' % (delta * 1e15)
97 delta_s = '%.1fps' % (delta * 1e12)
99 delta_s = '%.1fns' % (delta * 1e9)
101 delta_s = '%.1fμs' % (delta * 1e6)
103 delta_s = '%.1fms' % (delta * 1e3)
105 self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]])
107 # Helper function for ASCII float jitter values (one value per line).
108 def putb(self, delta):
111 # Format the delta to an ASCII float value terminated by a newline.
112 x = str(delta) + '\n'
113 self.put(self.clk_start, self.sig_start, self.out_binary,
114 [0, x.encode('UTF-8')])
116 # Helper function for missed clock and signal annotations.
117 def putm(self, data):
118 self.put(self.samplenum, self.samplenum, self.out_ann, data)
120 def handle_clk(self, clk, sig):
121 if self.clk_start == self.samplenum:
122 # Clock transition already treated.
123 # We have done everything we can with this sample.
126 if self.clk_edge(self.oldclk, clk):
128 # We note the sample and move to the next state.
129 self.clk_start = self.samplenum
133 if self.sig_start is not None \
134 and self.sig_start != self.samplenum \
135 and self.sig_edge(self.oldsig, sig):
136 # If any transition in the resulting signal
137 # occurs while we are waiting for a clock,
138 # we increase the missed signal counter.
140 self.put(self.samplenum, self.samplenum, self.out_sig_missed, self.sig_missed)
141 self.putm([2, ['Missed signal', 'MS']])
142 # No clock edge found, we have done everything we
143 # can with this sample.
146 def handle_sig(self, clk, sig):
147 if self.sig_start == self.samplenum:
148 # Signal transition already treated.
149 # We have done everything we can with this sample.
152 if self.sig_edge(self.oldsig, sig):
154 # We note the sample, calculate the jitter
155 # and move to the next state.
156 self.sig_start = self.samplenum
158 # Calculate and report the timing jitter.
159 delta = (self.sig_start - self.clk_start) / self.samplerate
164 if self.clk_start != self.samplenum \
165 and self.clk_edge(self.oldclk, clk):
166 # If any transition in the clock signal
167 # occurs while we are waiting for a resulting
168 # signal, we increase the missed clock counter.
170 self.put(self.samplenum, self.samplenum, self.out_clk_missed, self.clk_missed)
171 self.putm([1, ['Missed clock', 'MC']])
172 # No resulting signal edge found, we have done
173 # everything we can with this sample.
177 if not self.samplerate:
178 raise SamplerateError('Cannot decode without samplerate.')
180 # Wait for a transition on CLK and/or SIG.
181 clk, sig = self.wait([{0: 'e'}, {1: 'e'}])
184 # For each sample we can move 2 steps forward in the state machine.
186 # Clock state has the lead.
187 if self.state == 'CLK':
188 if self.handle_clk(clk, sig):
190 if self.state == 'SIG':
191 if self.handle_sig(clk, sig):
194 # Save current CLK/SIG values for the next round.
195 self.oldclk, self.oldsig = clk, sig