2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
6 ## Permission is hereby granted, free of charge, to any person obtaining a copy
7 ## of this software and associated documentation files (the "Software"), to deal
8 ## in the Software without restriction, including without limitation the rights
9 ## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 ## copies of the Software, and to permit persons to whom the Software is
11 ## furnished to do so, subject to the following conditions:
13 ## The above copyright notice and this permission notice shall be included in all
14 ## copies or substantial portions of the Software.
16 ## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 ## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 ## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 ## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 ## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 ## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 import sigrokdecode as srd
27 OPCODE_MASK = 0b11100000
28 REG_ADDR_MASK = 0b00011111
31 0b00000000: '_process_rcr',
32 0b00100000: '_process_rbm',
33 0b01000000: '_process_wcr',
34 0b01100000: '_process_wbm',
35 0b10000000: '_process_bfs',
36 0b10100000: '_process_bfc',
37 0b11100000: '_process_src',
40 (ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC, ANN_DATA,
41 ANN_REG_ADDR, ANN_WARNING) = range(10)
44 BIT_ECON1_BSEL0 = 0b00000001
45 BIT_ECON1_BSEL1 = 0b00000010
47 class Decoder(srd.Decoder):
51 longname = 'Microchip ENC28J60'
52 desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.'
56 tags = ['Embedded/industrial', 'Networking']
58 ('rcr', 'Read Control Register'),
59 ('rbm', 'Read Buffer Memory'),
60 ('wcr', 'Write Control Register'),
61 ('wbm', 'Write Buffer Memory'),
62 ('bfs', 'Bit Field Set'),
63 ('bfc', 'Bit Field Clear'),
64 ('src', 'System Reset Command'),
66 ('reg-addr', 'Register Address'),
67 ('warning', 'Warning'),
70 ('commands', 'Commands',
71 (ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC)),
72 ('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
73 ('warnings', 'Warnings', (ANN_WARNING,)),
90 self.ann = self.register(srd.OUTPUT_ANN)
92 def _process_command(self):
93 if len(self.mosi) == 0:
98 opcode = header & OPCODE_MASK
100 if opcode not in OPCODE_HANDLERS:
101 self._put_command_warning("Unknown opcode.")
105 getattr(self, OPCODE_HANDLERS[opcode])()
109 def _get_register_name(self, reg_addr):
110 if (self.bsel0 is None) or (self.bsel1 is None):
111 # We don't know the bank we're in yet.
114 bank = (self.bsel1 << 1) + self.bsel0
115 return REGS[bank][reg_addr]
117 def _put_register_header(self):
118 reg_addr = self.mosi[0] & REG_ADDR_MASK
119 reg_name = self._get_register_name(reg_addr)
121 ss, es = self.cmd_ss, self.ranges[1][0]
124 # We don't know the bank we're in yet.
125 self.put(ss, es, self.ann, [
128 'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr),
129 '?:{0:02X}'.format(reg_addr),
131 self.put(ss, es, self.ann, [
134 'Warning: Register bank not known yet.',
138 self.put(ss, es, self.ann, [
141 'Reg {0}'.format(reg_name),
142 '{0}'.format(reg_name),
145 if (reg_name == '-') or (reg_name == 'Reserved'):
146 self.put(ss, es, self.ann, [
149 'Warning: Invalid register accessed.',
153 def _put_data_byte(self, data, byte_index, binary=False):
154 ss = self.ranges[byte_index][0]
155 if byte_index == len(self.mosi) - 1:
158 es = self.ranges[byte_index + 1][0]
161 self.put(ss, es, self.ann, [
164 'Data 0b{0:08b}'.format(data),
165 '{0:08b}'.format(data),
168 self.put(ss, es, self.ann, [
171 'Data 0x{0:02X}'.format(data),
172 '{0:02X}'.format(data),
175 def _put_command_warning(self, reason):
176 self.put(self.cmd_ss, self.cmd_es, self.ann, [
179 'Warning: {0}'.format(reason),
183 def _process_rcr(self):
184 self.put(self.cmd_ss, self.cmd_es,
185 self.ann, [ANN_RCR, ['Read Control Register', 'RCR']])
187 if (len(self.mosi) != 2) and (len(self.mosi) != 3):
188 self._put_command_warning('Invalid command length.')
191 self._put_register_header()
193 reg_name = self._get_register_name(self.mosi[0] & REG_ADDR_MASK)
195 # We can't tell if we're accessing MAC/MII registers or not
196 # Let's trust the user in this case.
199 if (reg_name[0] == 'M') and (len(self.mosi) != 3):
200 self._put_command_warning('Attempting to read a MAC/MII '
201 + 'register without using the dummy byte.')
204 if (reg_name[0] != 'M') and (len(self.mosi) != 2):
205 self._put_command_warning('Attempting to read a non-MAC/MII '
206 + 'register using the dummy byte.')
209 if len(self.mosi) == 2:
210 self._put_data_byte(self.miso[1], 1)
212 ss, es = self.ranges[1][0], self.ranges[2][0]
213 self.put(ss, es, self.ann, [
219 self._put_data_byte(self.miso[2], 2)
221 def _process_rbm(self):
222 if self.mosi[0] != 0b00111010:
223 self._put_command_warning('Invalid header byte.')
226 self.put(self.cmd_ss, self.cmd_es, self.ann, [
229 'Read Buffer Memory: Length {0}'.format(
234 for i in range(1, len(self.miso)):
235 self._put_data_byte(self.miso[i], i)
237 def _process_wcr(self):
238 self.put(self.cmd_ss, self.cmd_es,
239 self.ann, [ANN_WCR, ['Write Control Register', 'WCR']])
241 if len(self.mosi) != 2:
242 self._put_command_warning('Invalid command length.')
245 self._put_register_header()
246 self._put_data_byte(self.mosi[1], 1)
248 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
249 self.bsel0 = (self.mosi[1] & BIT_ECON1_BSEL0) >> 0
250 self.bsel1 = (self.mosi[1] & BIT_ECON1_BSEL1) >> 1
252 def _process_wbm(self):
253 if self.mosi[0] != 0b01111010:
254 self._put_command_warning('Invalid header byte.')
257 self.put(self.cmd_ss, self.cmd_es, self.ann, [
260 'Write Buffer Memory: Length {0}'.format(
265 for i in range(1, len(self.mosi)):
266 self._put_data_byte(self.mosi[i], i)
268 def _process_bfc(self):
269 self.put(self.cmd_ss, self.cmd_es,
270 self.ann, [ANN_BFC, ['Bit Field Clear', 'BFC']])
272 if len(self.mosi) != 2:
273 self._put_command_warning('Invalid command length.')
276 self._put_register_header()
277 self._put_data_byte(self.mosi[1], 1, True)
279 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
280 if self.mosi[1] & BIT_ECON1_BSEL0:
282 if self.mosi[1] & BIT_ECON1_BSEL1:
285 def _process_bfs(self):
286 self.put(self.cmd_ss, self.cmd_es,
287 self.ann, [ANN_BFS, ['Bit Field Set', 'BFS']])
289 if len(self.mosi) != 2:
290 self._put_command_warning('Invalid command length.')
293 self._put_register_header()
294 self._put_data_byte(self.mosi[1], 1, True)
296 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
297 if self.mosi[1] & BIT_ECON1_BSEL0:
299 if self.mosi[1] & BIT_ECON1_BSEL1:
302 def _process_src(self):
303 self.put(self.cmd_ss, self.cmd_es,
304 self.ann, [ANN_SRC, ['System Reset Command', 'SRC']])
306 if len(self.mosi) != 1:
307 self._put_command_warning('Invalid command length.')
313 def decode(self, ss, es, data):
314 ptype, data1, data2 = data
316 if ptype == 'CS-CHANGE':
328 self._process_command()
329 elif ptype == 'DATA':
330 mosi, miso = data1, data2
332 self.mosi.append(mosi)
333 self.miso.append(miso)
334 self.ranges.append((ss, es))