2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
6 ## Permission is hereby granted, free of charge, to any person obtaining a copy
7 ## of this software and associated documentation files (the "Software"), to deal
8 ## in the Software without restriction, including without limitation the rights
9 ## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 ## copies of the Software, and to permit persons to whom the Software is
11 ## furnished to do so, subject to the following conditions:
13 ## The above copyright notice and this permission notice shall be included in all
14 ## copies or substantial portions of the Software.
16 ## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 ## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 ## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 ## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 ## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 ## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 import sigrokdecode as srd
26 OPCODE_MASK = 0b11100000
27 REG_ADDR_MASK = 0b00011111
30 0b00000000: '_process_rcr',
31 0b00100000: '_process_rbm',
32 0b01000000: '_process_wcr',
33 0b01100000: '_process_wbm',
34 0b10000000: '_process_bfs',
35 0b10100000: '_process_bfc',
36 0b11100000: '_process_src',
53 BIT_ECON1_BSEL0 = 0b00000001
54 BIT_ECON1_BSEL1 = 0b00000010
195 class Decoder(srd.Decoder):
199 longname = 'Microchip ENC28J60'
200 desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.'
203 outputs = ['enc28j60']
205 ('rcr', 'Read Control Register'),
206 ('rbm', 'Read Buffer Memory'),
207 ('wcr', 'Write Control Register'),
208 ('wbm', 'Write Buffer Memory'),
209 ('bfs', 'Bit Field Set'),
210 ('bfc', 'Bit Field Clear'),
211 ('src', 'System Reset Command'),
213 ('reg-addr', 'Register Address'),
214 ('warning', 'Warning'),
217 ('commands', 'Commands',
218 (ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC)),
219 ('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
220 ('warnings', 'Warnings', (ANN_WARNING,)),
230 self.command_start = None
231 self.command_end = None
237 self.ann = self.register(srd.OUTPUT_ANN)
239 def _process_command(self):
240 if len(self.mosi) == 0:
244 header = self.mosi[0]
245 opcode = header & OPCODE_MASK
247 if opcode not in OPCODE_HANDLERS:
248 self._put_command_warning("Unknown opcode.")
252 getattr(self, OPCODE_HANDLERS[opcode])()
256 def _get_register_name(self, reg_addr):
257 if (self.bsel0 is None) or (self.bsel1 is None):
258 # We don't know the bank we're in yet.
261 bank = (self.bsel1 << 1) + self.bsel0
262 return REGS[bank][reg_addr]
264 def _put_register_header(self):
265 reg_addr = self.mosi[0] & REG_ADDR_MASK
266 reg_name = self._get_register_name(reg_addr)
269 # We don't know the bank we're in yet.
270 self.put(self.command_start, self.ranges[1][0], self.ann, [
273 'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr),
274 '?:{0:02X}'.format(reg_addr),
276 self.put(self.command_start, self.ranges[1][0], self.ann, [
279 'Warning: Register bank not known yet.',
283 self.put(self.command_start, self.ranges[1][0], self.ann, [
286 'Reg {0}'.format(reg_name),
287 '{0}'.format(reg_name),
290 if (reg_name == '-') or (reg_name == 'Reserved'):
291 self.put(self.command_start, self.ranges[1][0], self.ann, [
294 'Warning: Invalid register accessed.',
298 def _put_data_byte(self, data, byte_index, binary=False):
299 if byte_index == len(self.mosi) - 1:
300 end_sample = self.command_end
302 end_sample = self.ranges[byte_index + 1][0]
305 self.put(self.ranges[byte_index][0], end_sample, self.ann, [
308 'Data 0b{0:08b}'.format(data),
309 '{0:08b}'.format(data),
312 self.put(self.ranges[byte_index][0], end_sample, self.ann, [
315 'Data 0x{0:02X}'.format(data),
316 '{0:02X}'.format(data),
319 def _put_command_warning(self, reason):
320 self.put(self.command_start, self.command_end, self.ann, [
323 'Warning: {0}'.format(reason),
327 def _process_rcr(self):
328 self.put(self.command_start, self.command_end,
329 self.ann, [ANN_RCR, ['Read Control Register', 'RCR']])
331 if (len(self.mosi) != 2) and (len(self.mosi) != 3):
332 self._put_command_warning('Invalid command length.')
335 self._put_register_header()
337 reg_name = self._get_register_name(self.mosi[0] & REG_ADDR_MASK)
339 # We can't tell if we're accessing MAC/MII registers or not
340 # Let's trust the user in this case.
343 if (reg_name[0] == 'M') and (len(self.mosi) != 3):
344 self._put_command_warning('Attempting to read a MAC/MII '
345 + 'register without using the dummy byte.')
348 if (reg_name[0] != 'M') and (len(self.mosi) != 2):
349 self._put_command_warning('Attempting to read a non-MAC/MII '
350 + 'register using the dummy byte.')
353 if len(self.mosi) == 2:
354 self._put_data_byte(self.miso[1], 1)
356 self.put(self.ranges[1][0], self.ranges[2][0], self.ann, [
362 self._put_data_byte(self.miso[2], 2)
364 def _process_rbm(self):
365 if self.mosi[0] != 0b00111010:
366 self._put_command_warning('Invalid header byte.')
369 self.put(self.command_start, self.command_end, self.ann, [
372 'Read Buffer Memory: Length {0}'.format(
377 for i in range(1, len(self.miso)):
378 self._put_data_byte(self.miso[i], i)
380 def _process_wcr(self):
381 self.put(self.command_start, self.command_end,
382 self.ann, [ANN_WCR, ['Write Control Register', 'WCR']])
384 if len(self.mosi) != 2:
385 self._put_command_warning('Invalid command length.')
388 self._put_register_header()
389 self._put_data_byte(self.mosi[1], 1)
391 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
392 self.bsel0 = (self.mosi[1] & BIT_ECON1_BSEL0) >> 0
393 self.bsel1 = (self.mosi[1] & BIT_ECON1_BSEL1) >> 1
395 def _process_wbm(self):
396 if self.mosi[0] != 0b01111010:
397 self._put_command_warning('Invalid header byte.')
400 self.put(self.command_start, self.command_end, self.ann, [
403 'Write Buffer Memory: Length {0}'.format(
408 for i in range(1, len(self.mosi)):
409 self._put_data_byte(self.mosi[i], i)
411 def _process_bfc(self):
412 self.put(self.command_start, self.command_end,
413 self.ann, [ANN_BFC, ['Bit Field Clear', 'BFC']])
415 if len(self.mosi) != 2:
416 self._put_command_warning('Invalid command length.')
419 self._put_register_header()
420 self._put_data_byte(self.mosi[1], 1, True)
422 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
423 if self.mosi[1] & BIT_ECON1_BSEL0:
425 if self.mosi[1] & BIT_ECON1_BSEL1:
428 def _process_bfs(self):
429 self.put(self.command_start, self.command_end,
430 self.ann, [ANN_BFS, ['Bit Field Set', 'BFS']])
432 if len(self.mosi) != 2:
433 self._put_command_warning('Invalid command length.')
436 self._put_register_header()
437 self._put_data_byte(self.mosi[1], 1, True)
439 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
440 if self.mosi[1] & BIT_ECON1_BSEL0:
442 if self.mosi[1] & BIT_ECON1_BSEL1:
445 def _process_src(self):
446 self.put(self.command_start, self.command_end,
447 self.ann, [ANN_SRC, ['System Reset Command', 'SRC']])
449 if len(self.mosi) != 1:
450 self._put_command_warning('Invalid command length.')
456 def decode(self, ss, es, data):
457 ptype, data1, data2 = data
459 if ptype == 'CS-CHANGE':
464 self.command_start = ss
470 self.command_end = es
471 self._process_command()
472 elif ptype == 'DATA':
473 mosi, miso = data1, data2
475 self.mosi.append(mosi)
476 self.miso.append(miso)
477 self.ranges.append((ss, es))