2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
6 ## Permission is hereby granted, free of charge, to any person obtaining a copy
7 ## of this software and associated documentation files (the "Software"), to deal
8 ## in the Software without restriction, including without limitation the rights
9 ## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 ## copies of the Software, and to permit persons to whom the Software is
11 ## furnished to do so, subject to the following conditions:
13 ## The above copyright notice and this permission notice shall be included in all
14 ## copies or substantial portions of the Software.
16 ## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 ## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 ## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 ## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 ## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 ## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 import sigrokdecode as srd
27 OPCODE_MASK = 0b11100000
28 REG_ADDR_MASK = 0b00011111
31 0b00000000: '_process_rcr',
32 0b00100000: '_process_rbm',
33 0b01000000: '_process_wcr',
34 0b01100000: '_process_wbm',
35 0b10000000: '_process_bfs',
36 0b10100000: '_process_bfc',
37 0b11100000: '_process_src',
40 (ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC, ANN_DATA,
41 ANN_REG_ADDR, ANN_WARNING) = range(10)
44 BIT_ECON1_BSEL0 = 0b00000001
45 BIT_ECON1_BSEL1 = 0b00000010
47 class Decoder(srd.Decoder):
51 longname = 'Microchip ENC28J60'
52 desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.'
56 tags = ['Embedded/industrial', 'Networking']
58 ('rcr', 'Read Control Register'),
59 ('rbm', 'Read Buffer Memory'),
60 ('wcr', 'Write Control Register'),
61 ('wbm', 'Write Buffer Memory'),
62 ('bfs', 'Bit Field Set'),
63 ('bfc', 'Bit Field Clear'),
64 ('src', 'System Reset Command'),
66 ('reg-addr', 'Register Address'),
67 ('warning', 'Warning'),
70 ('commands', 'Commands',
71 (ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC)),
72 ('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
73 ('warnings', 'Warnings', (ANN_WARNING,)),
83 self.command_start = None
84 self.command_end = None
90 self.ann = self.register(srd.OUTPUT_ANN)
92 def _process_command(self):
93 if len(self.mosi) == 0:
98 opcode = header & OPCODE_MASK
100 if opcode not in OPCODE_HANDLERS:
101 self._put_command_warning("Unknown opcode.")
105 getattr(self, OPCODE_HANDLERS[opcode])()
109 def _get_register_name(self, reg_addr):
110 if (self.bsel0 is None) or (self.bsel1 is None):
111 # We don't know the bank we're in yet.
114 bank = (self.bsel1 << 1) + self.bsel0
115 return REGS[bank][reg_addr]
117 def _put_register_header(self):
118 reg_addr = self.mosi[0] & REG_ADDR_MASK
119 reg_name = self._get_register_name(reg_addr)
122 # We don't know the bank we're in yet.
123 self.put(self.command_start, self.ranges[1][0], self.ann, [
126 'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr),
127 '?:{0:02X}'.format(reg_addr),
129 self.put(self.command_start, self.ranges[1][0], self.ann, [
132 'Warning: Register bank not known yet.',
136 self.put(self.command_start, self.ranges[1][0], self.ann, [
139 'Reg {0}'.format(reg_name),
140 '{0}'.format(reg_name),
143 if (reg_name == '-') or (reg_name == 'Reserved'):
144 self.put(self.command_start, self.ranges[1][0], self.ann, [
147 'Warning: Invalid register accessed.',
151 def _put_data_byte(self, data, byte_index, binary=False):
152 if byte_index == len(self.mosi) - 1:
153 end_sample = self.command_end
155 end_sample = self.ranges[byte_index + 1][0]
158 self.put(self.ranges[byte_index][0], end_sample, self.ann, [
161 'Data 0b{0:08b}'.format(data),
162 '{0:08b}'.format(data),
165 self.put(self.ranges[byte_index][0], end_sample, self.ann, [
168 'Data 0x{0:02X}'.format(data),
169 '{0:02X}'.format(data),
172 def _put_command_warning(self, reason):
173 self.put(self.command_start, self.command_end, self.ann, [
176 'Warning: {0}'.format(reason),
180 def _process_rcr(self):
181 self.put(self.command_start, self.command_end,
182 self.ann, [ANN_RCR, ['Read Control Register', 'RCR']])
184 if (len(self.mosi) != 2) and (len(self.mosi) != 3):
185 self._put_command_warning('Invalid command length.')
188 self._put_register_header()
190 reg_name = self._get_register_name(self.mosi[0] & REG_ADDR_MASK)
192 # We can't tell if we're accessing MAC/MII registers or not
193 # Let's trust the user in this case.
196 if (reg_name[0] == 'M') and (len(self.mosi) != 3):
197 self._put_command_warning('Attempting to read a MAC/MII '
198 + 'register without using the dummy byte.')
201 if (reg_name[0] != 'M') and (len(self.mosi) != 2):
202 self._put_command_warning('Attempting to read a non-MAC/MII '
203 + 'register using the dummy byte.')
206 if len(self.mosi) == 2:
207 self._put_data_byte(self.miso[1], 1)
209 self.put(self.ranges[1][0], self.ranges[2][0], self.ann, [
215 self._put_data_byte(self.miso[2], 2)
217 def _process_rbm(self):
218 if self.mosi[0] != 0b00111010:
219 self._put_command_warning('Invalid header byte.')
222 self.put(self.command_start, self.command_end, self.ann, [
225 'Read Buffer Memory: Length {0}'.format(
230 for i in range(1, len(self.miso)):
231 self._put_data_byte(self.miso[i], i)
233 def _process_wcr(self):
234 self.put(self.command_start, self.command_end,
235 self.ann, [ANN_WCR, ['Write Control Register', 'WCR']])
237 if len(self.mosi) != 2:
238 self._put_command_warning('Invalid command length.')
241 self._put_register_header()
242 self._put_data_byte(self.mosi[1], 1)
244 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
245 self.bsel0 = (self.mosi[1] & BIT_ECON1_BSEL0) >> 0
246 self.bsel1 = (self.mosi[1] & BIT_ECON1_BSEL1) >> 1
248 def _process_wbm(self):
249 if self.mosi[0] != 0b01111010:
250 self._put_command_warning('Invalid header byte.')
253 self.put(self.command_start, self.command_end, self.ann, [
256 'Write Buffer Memory: Length {0}'.format(
261 for i in range(1, len(self.mosi)):
262 self._put_data_byte(self.mosi[i], i)
264 def _process_bfc(self):
265 self.put(self.command_start, self.command_end,
266 self.ann, [ANN_BFC, ['Bit Field Clear', 'BFC']])
268 if len(self.mosi) != 2:
269 self._put_command_warning('Invalid command length.')
272 self._put_register_header()
273 self._put_data_byte(self.mosi[1], 1, True)
275 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
276 if self.mosi[1] & BIT_ECON1_BSEL0:
278 if self.mosi[1] & BIT_ECON1_BSEL1:
281 def _process_bfs(self):
282 self.put(self.command_start, self.command_end,
283 self.ann, [ANN_BFS, ['Bit Field Set', 'BFS']])
285 if len(self.mosi) != 2:
286 self._put_command_warning('Invalid command length.')
289 self._put_register_header()
290 self._put_data_byte(self.mosi[1], 1, True)
292 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
293 if self.mosi[1] & BIT_ECON1_BSEL0:
295 if self.mosi[1] & BIT_ECON1_BSEL1:
298 def _process_src(self):
299 self.put(self.command_start, self.command_end,
300 self.ann, [ANN_SRC, ['System Reset Command', 'SRC']])
302 if len(self.mosi) != 1:
303 self._put_command_warning('Invalid command length.')
309 def decode(self, ss, es, data):
310 ptype, data1, data2 = data
312 if ptype == 'CS-CHANGE':
317 self.command_start = ss
323 self.command_end = es
324 self._process_command()
325 elif ptype == 'DATA':
326 mosi, miso = data1, data2
328 self.mosi.append(mosi)
329 self.miso.append(miso)
330 self.ranges.append((ss, es))