2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
5 ## Copyright (C) 2019 Stephan Thiele <stephan.thiele@mailbox.org>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
21 import sigrokdecode as srd
23 class SamplerateError(Exception):
26 class Decoder(srd.Decoder):
30 longname = 'Controller Area Network'
31 desc = 'Field bus protocol for distributed realtime control.'
37 {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
40 {'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000},
41 {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0},
44 ('data', 'CAN payload data'),
45 ('sof', 'Start of frame'),
46 ('eof', 'End of frame'),
48 ('ext-id', 'Extended identifier'),
49 ('full-id', 'Full identifier'),
50 ('ide', 'Identifier extension bit'),
51 ('reserved-bit', 'Reserved bit 0 and 1'),
52 ('rtr', 'Remote transmission request'),
53 ('srr', 'Substitute remote request'),
54 ('dlc', 'Data length count'),
55 ('crc-sequence', 'CRC sequence'),
56 ('crc-delimiter', 'CRC delimiter'),
57 ('ack-slot', 'ACK slot'),
58 ('ack-delimiter', 'ACK delimiter'),
59 ('stuff-bit', 'Stuff bit'),
60 ('warnings', 'Human-readable warnings'),
64 ('bits', 'Bits', (15, 17)),
65 ('fields', 'Fields', tuple(range(15))),
66 ('warnings', 'Warnings', (16,)),
73 self.samplerate = None
74 self.reset_variables()
77 self.out_ann = self.register(srd.OUTPUT_ANN)
79 def metadata(self, key, value):
80 if key == srd.SRD_CONF_SAMPLERATE:
81 self.samplerate = value
82 self.bit_width = float(self.samplerate) / float(self.options['bitrate'])
83 self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
85 # Generic helper for CAN bit annotations.
86 def putg(self, ss, es, data):
87 left, right = int(self.sample_point), int(self.bit_width - self.sample_point)
88 self.put(ss - left, es + right, self.out_ann, data)
90 # Single-CAN-bit annotation using the current samplenum.
92 self.putg(self.samplenum, self.samplenum, data)
94 # Single-CAN-bit annotation using the samplenum of CAN bit 12.
95 def put12(self, data):
96 self.putg(self.ss_bit12, self.ss_bit12, data)
98 # Multi-CAN-bit annotation from self.ss_block to current samplenum.
100 self.putg(self.ss_block, self.samplenum, data)
102 def reset_variables(self):
104 self.sof = self.frame_type = self.dlc = None
105 self.rawbits = [] # All bits, including stuff bits
106 self.bits = [] # Only actual CAN frame bits (no stuff bits)
107 self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF)
108 self.last_databit = 999 # Positive value that bitnum+x will never match
111 self.ss_databytebits = []
113 # Poor man's clock synchronization. Use signal edges which change to
114 # dominant state in rather simple ways. This naive approach is neither
115 # aware of the SYNC phase's width nor the specific location of the edge,
116 # but improves the decoder's reliability when the input signal's bitrate
117 # does not exactly match the nominal rate.
118 def dom_edge_seen(self, force = False):
119 self.dom_edge_snum = self.samplenum
120 self.dom_edge_bcount = self.curbit
122 def bit_sampled(self):
126 # Determine the position of the next desired bit's sample point.
127 def get_sample_point(self, bitnum):
128 samplenum = self.dom_edge_snum
129 samplenum += int(self.bit_width * (bitnum - self.dom_edge_bcount))
130 samplenum += int(self.sample_point)
133 def is_stuff_bit(self):
134 # CAN uses NRZ encoding and bit stuffing.
135 # After 5 identical bits, a stuff bit of opposite value is added.
136 # But not in the CRC delimiter, ACK, and end of frame fields.
137 if len(self.bits) > self.last_databit + 17:
139 last_6_bits = self.rawbits[-6:]
140 if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]):
143 # Stuff bit. Keep it in self.rawbits, but drop it from self.bits.
144 self.bits.pop() # Drop last bit.
147 def is_valid_crc(self, crc_bits):
150 def decode_error_frame(self, bits):
153 def decode_overload_frame(self, bits):
156 # Both standard and extended frames end with CRC, CRC delimiter, ACK,
157 # ACK delimiter, and EOF fields. Handle them in a common function.
158 # Returns True if the frame ended (EOF), False otherwise.
159 def decode_frame_end(self, can_rx, bitnum):
161 # Remember start of CRC sequence (see below).
162 if bitnum == (self.last_databit + 1):
163 self.ss_block = self.samplenum
165 # CRC sequence (15 bits)
166 elif bitnum == (self.last_databit + 15):
167 x = self.last_databit + 1
168 crc_bits = self.bits[x:x + 15 + 1]
169 self.crc = int(''.join(str(d) for d in crc_bits), 2)
170 self.putb([11, ['CRC sequence: 0x%04x' % self.crc,
171 'CRC: 0x%04x' % self.crc, 'CRC']])
172 if not self.is_valid_crc(crc_bits):
173 self.putb([16, ['CRC is invalid']])
175 # CRC delimiter bit (recessive)
176 elif bitnum == (self.last_databit + 16):
177 self.putx([12, ['CRC delimiter: %d' % can_rx,
178 'CRC d: %d' % can_rx, 'CRC d']])
180 self.putx([16, ['CRC delimiter must be a recessive bit']])
182 # ACK slot bit (dominant: ACK, recessive: NACK)
183 elif bitnum == (self.last_databit + 17):
184 ack = 'ACK' if can_rx == 0 else 'NACK'
185 self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']])
187 # ACK delimiter bit (recessive)
188 elif bitnum == (self.last_databit + 18):
189 self.putx([14, ['ACK delimiter: %d' % can_rx,
190 'ACK d: %d' % can_rx, 'ACK d']])
192 self.putx([16, ['ACK delimiter must be a recessive bit']])
194 # Remember start of EOF (see below).
195 elif bitnum == (self.last_databit + 19):
196 self.ss_block = self.samplenum
198 # End of frame (EOF), 7 recessive bits
199 elif bitnum == (self.last_databit + 25):
200 self.putb([2, ['End of frame', 'EOF', 'E']])
201 if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]:
202 self.putb([16, ['End of frame (EOF) must be 7 recessive bits']])
203 self.reset_variables()
208 # Returns True if the frame ended (EOF), False otherwise.
209 def decode_standard_frame(self, can_rx, bitnum):
211 # Bit 14: FDF (Flexible Data Format)
212 # Has to be sent dominant when FD frame, has to be sent recessive when classic CAN frame.
214 self.fd = True if can_rx else False
216 self.putx([7, ['Flexible Data Format: %d' % can_rx,
220 # SRR Substitute Remote Request
222 self.put12([8, ['Substitute Remote Request', 'SRR']])
225 # Bit 12: Remote transmission request (RTR) bit
226 # Data frame: dominant, remote frame: recessive
227 # Remote frames do not contain a data field.
228 rtr = 'remote' if self.bits[12] == 1 else 'data'
229 self.put12([8, ['Remote transmission request: %s frame' % rtr,
230 'RTR: %s frame' % rtr, 'RTR']])
233 # TODO: add Res, BRS and ESI bits when FD format:
236 self.putx([7, ['Reserved: %d' % can_rx, 'R0: %d' % can_rx, 'R0']])
240 self.putx([7, ['Bit rate switch: %d' % can_rx, 'BRS: %d' % can_rx, 'BRS']])
244 self.putx([7, ['Error state indicator: %d' % can_rx, 'ESI: %d' % can_rx, 'ESI']])
246 # Remember start of DLC (see below).
247 elif bitnum == self.dlc_start:
248 self.ss_block = self.samplenum
250 # Bits 15-18: Data length code (DLC), in number of bytes (0-8).
251 elif bitnum == self.dlc_start + 3:
252 self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2)
253 self.putb([10, ['Data length code: %d' % self.dlc,
254 'DLC: %d' % self.dlc, 'DLC']])
255 self.last_databit = self.dlc_start + 3 + (self.dlc * 8)
257 self.putb([16, ['Data length code (DLC) > 8 is not allowed']])
259 # Remember all databyte bits, except the very last one.
260 elif bitnum in range(self.dlc_start + 4, self.last_databit):
261 self.ss_databytebits.append(self.samplenum)
263 # Bits 19-X: Data field (0-8 bytes, depending on DLC)
264 # The bits within a data byte are transferred MSB-first.
265 elif bitnum == self.last_databit:
266 self.ss_databytebits.append(self.samplenum) # Last databyte bit.
267 for i in range(self.dlc):
268 x = self.dlc_start + 4 + (8 * i)
269 b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
270 ss = self.ss_databytebits[i * 8]
271 es = self.ss_databytebits[((i + 1) * 8) - 1]
272 self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
273 'DB %d: 0x%02x' % (i, b), 'DB']])
274 self.ss_databytebits = []
276 elif bitnum > self.last_databit:
277 return self.decode_frame_end(can_rx, bitnum)
281 # Returns True if the frame ended (EOF), False otherwise.
282 def decode_extended_frame(self, can_rx, bitnum):
284 # Remember start of EID (see below).
286 self.ss_block = self.samplenum
288 # Bits 14-31: Extended identifier (EID[17..0])
290 self.eid = int(''.join(str(d) for d in self.bits[14:]), 2)
291 s = '%d (0x%x)' % (self.eid, self.eid)
292 self.putb([4, ['Extended Identifier: %s' % s,
293 'Extended ID: %s' % s, 'Extended ID', 'EID']])
295 self.fullid = self.id << 18 | self.eid
296 s = '%d (0x%x)' % (self.fullid, self.fullid)
297 self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s,
300 # Bit 12: Substitute remote request (SRR) bit
301 self.put12([9, ['Substitute remote request: %d' % self.bits[12],
302 'SRR: %d' % self.bits[12], 'SRR']])
304 # Bit 32: Remote transmission request (RTR) bit
305 # Data frame: dominant, remote frame: recessive
306 # Remote frames do not contain a data field.
308 rtr = 'remote' if can_rx == 1 else 'data'
309 self.putx([8, ['Remote transmission request: %s frame' % rtr,
310 'RTR: %s frame' % rtr, 'RTR']])
312 # Bit 33: RB1 (reserved bit)
314 self.putx([7, ['Reserved bit 1: %d' % can_rx,
315 'RB1: %d' % can_rx, 'RB1']])
317 # Bit 34: RB0 (reserved bit)
319 self.putx([7, ['Reserved bit 0: %d' % can_rx,
320 'RB0: %d' % can_rx, 'RB0']])
322 # Remember start of DLC (see below).
324 self.ss_block = self.samplenum
326 # Bits 35-38: Data length code (DLC), in number of bytes (0-8).
328 self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2)
329 self.putb([10, ['Data length code: %d' % self.dlc,
330 'DLC: %d' % self.dlc, 'DLC']])
331 self.last_databit = 38 + (self.dlc * 8)
333 # Remember all databyte bits, except the very last one.
334 elif bitnum in range(39, self.last_databit):
335 self.ss_databytebits.append(self.samplenum)
337 # Bits 39-X: Data field (0-8 bytes, depending on DLC)
338 # The bits within a data byte are transferred MSB-first.
339 elif bitnum == self.last_databit:
340 self.ss_databytebits.append(self.samplenum) # Last databyte bit.
341 for i in range(self.dlc):
343 b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
344 ss = self.ss_databytebits[i * 8]
345 es = self.ss_databytebits[((i + 1) * 8) - 1]
346 self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
347 'DB %d: 0x%02x' % (i, b), 'DB']])
348 self.ss_databytebits = []
350 elif bitnum > self.last_databit:
351 return self.decode_frame_end(can_rx, bitnum)
355 def handle_bit(self, can_rx):
356 self.rawbits.append(can_rx)
357 self.bits.append(can_rx)
359 # Get the index of the current CAN frame bit (without stuff bits).
360 bitnum = len(self.bits) - 1
362 # If this is a stuff bit, remove it from self.bits and ignore it.
363 if self.is_stuff_bit():
364 self.putx([15, [str(can_rx)]])
365 self.curbit += 1 # Increase self.curbit (bitnum is not affected).
368 self.putx([17, [str(can_rx)]])
370 # Bit 0: Start of frame (SOF) bit
372 self.putx([1, ['Start of frame', 'SOF', 'S']])
374 self.putx([16, ['Start of frame (SOF) must be a dominant bit']])
376 # Remember start of ID (see below).
378 self.ss_block = self.samplenum
380 # Bits 1-11: Identifier (ID[10..0])
381 # The bits ID[10..4] must NOT be all recessive.
383 self.id = int(''.join(str(d) for d in self.bits[1:]), 2)
384 s = '%d (0x%x)' % (self.id, self.id),
385 self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']])
386 if (self.id & 0x7f0) == 0x7f0:
387 self.putb([16, ['Identifier bits 10..4 must not be all recessive']])
389 # RTR or SRR bit, depending on frame type (gets handled later).
391 # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only.
392 self.ss_bit12 = self.samplenum
394 # Bit 13: Identifier extension (IDE) bit
395 # Standard frame: dominant, extended frame: recessive
397 ide = self.frame_type = 'standard' if can_rx == 0 else 'extended'
398 self.putx([6, ['Identifier extension bit: %s frame' % ide,
399 'IDE: %s frame' % ide, 'IDE']])
401 # Bits 14-X: Frame-type dependent, passed to the resp. handlers.
403 if self.frame_type == 'standard':
404 done = self.decode_standard_frame(can_rx, bitnum)
406 done = self.decode_extended_frame(can_rx, bitnum)
408 # The handlers return True if a frame ended (EOF).
412 # After a frame there are 3 intermission bits (recessive).
413 # After these bits, the bus is considered free.
418 if not self.samplerate:
419 raise SamplerateError('Cannot decode without samplerate.')
423 if self.state == 'IDLE':
424 # Wait for a dominant state (logic 0) on the bus.
425 (can_rx,) = self.wait({0: 'l'})
426 self.sof = self.samplenum
427 self.dom_edge_seen(force = True)
428 self.state = 'GET BITS'
429 elif self.state == 'GET BITS':
430 # Wait until we're in the correct bit/sampling position.
431 pos = self.get_sample_point(self.curbit)
432 (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}])
436 self.handle_bit(can_rx)