From: Diego Asanza <redacted>
Date: Sun, 8 May 2016 08:07:05 +0000 (+0200)
Subject: dslogic: Add support for external clock edge selection.
X-Git-Tag: libsigrok-0.5.0~407
X-Git-Url: https://sigrok.org/gitweb/?p=libsigrok.git;a=commitdiff_plain;h=d9a58763d66b761900fdc930d9cd580137ea3a5c

dslogic: Add support for external clock edge selection.

This commit expands support for acquisition using an external clock,
now allowing the user to select the clock edge.

Signed-off-by: Diego Asanza <redacted>
---

diff --git a/src/hardware/fx2lafw/api.c b/src/hardware/fx2lafw/api.c
index 6e8eff4e..17ae297c 100644
--- a/src/hardware/fx2lafw/api.c
+++ b/src/hardware/fx2lafw/api.c
@@ -143,6 +143,7 @@ static const uint32_t dslogic_devopts[] = {
 	SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
 	SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
 	SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
+	SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST
 };
 
 static const int32_t soft_trigger_matches[] = {
@@ -153,6 +154,13 @@ static const int32_t soft_trigger_matches[] = {
 	SR_TRIGGER_EDGE,
 };
 
+/* Names assigned to available edge slope choices.
+ */
+static const char *const signal_edge_names[] = {
+	[DS_EDGE_RISING] = "rising",
+	[DS_EDGE_FALLING] = "falling",
+};
+
 static const struct {
 	int range;
 	gdouble low;
@@ -574,6 +582,12 @@ static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *s
 	case SR_CONF_CONTINUOUS:
 		*data = g_variant_new_boolean(devc->dslogic_continuous_mode);
 		break;
+	case SR_CONF_CLOCK_EDGE:
+		i = devc->dslogic_clock_edge;
+		if (i >= ARRAY_SIZE(signal_edge_names))
+			return SR_ERR_BUG;
+		*data = g_variant_new_string(signal_edge_names[0]);//idx]);
+		break;
 	default:
 		return SR_ERR_NA;
 	}
@@ -581,6 +595,28 @@ static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *s
 	return SR_OK;
 }
 
+
+/* Helper for mapping a string-typed configuration value to an index
+ * within a table of possible values.
+ */
+static int lookup_index(GVariant *value, const char *const *table, int len)
+{
+	const char *entry;
+	int i;
+
+	entry = g_variant_get_string(value, NULL);
+	if (!entry)
+		return -1;
+
+	/* Linear search is fine for very small tables. */
+	for (i = 0; i < len; i++) {
+		if (strcmp(entry, table[i]) == 0)
+			return i;
+	}
+
+	return -1;
+}
+
 static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
 		const struct sr_channel_group *cg)
 {
@@ -645,6 +681,13 @@ static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sd
 	case SR_CONF_CONTINUOUS:
 		devc->dslogic_continuous_mode = g_variant_get_boolean(data);
 		break;
+	case SR_CONF_CLOCK_EDGE:
+		i = lookup_index(data, signal_edge_names,
+		 		   ARRAY_SIZE(signal_edge_names));
+		if (i < 0)
+			return SR_ERR_ARG;
+		devc->dslogic_clock_edge = i;
+		break;		
 	default:
 		ret = SR_ERR_NA;
 	}
@@ -709,6 +752,10 @@ static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *
 				soft_trigger_matches, ARRAY_SIZE(soft_trigger_matches),
 				sizeof(int32_t));
 		break;
+	case SR_CONF_CLOCK_EDGE:
+		*data = g_variant_new_strv(signal_edge_names,
+			ARRAY_SIZE(signal_edge_names));
+		break;
 	default:
 		return SR_ERR_NA;
 	}
diff --git a/src/hardware/fx2lafw/dslogic.c b/src/hardware/fx2lafw/dslogic.c
index 992a07a5..619544f9 100644
--- a/src/hardware/fx2lafw/dslogic.c
+++ b/src/hardware/fx2lafw/dslogic.c
@@ -337,8 +337,10 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 	 * 6	1 = samplerate 400MHz
 	 * 5	1 = samplerate 200MHz or analog mode
 	 * 4	0 = logic, 1 = dso or analog
-	 * 2-3	unused
-	 * 1	0 = internal clock, 1 = external clock
+	 * 3	unused
+	 * 1-2	00 = internal clock, 
+	 * 		01 = external clock rising, 
+	 * 		11 = external clock falling
 	 * 0	1 = trigger enabled
 	 */
 	v16 = 0x0000;
@@ -350,8 +352,12 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 		v16 = 1 << 13;
 	if (devc->dslogic_continuous_mode)
 		v16 |= 1 << 12;
-	if (devc->dslogic_external_clock)
+	if (devc->dslogic_external_clock){
 		v16 |= 1 << 1;
+		if (devc->dslogic_clock_edge == DS_EDGE_FALLING){
+			v16 |= 1 << 2;
+		}
+	}
 
 	WL16(&cfg.mode, v16);
 	v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
diff --git a/src/hardware/fx2lafw/dslogic.h b/src/hardware/fx2lafw/dslogic.h
index 15068ec9..b6c6e7d5 100644
--- a/src/hardware/fx2lafw/dslogic.h
+++ b/src/hardware/fx2lafw/dslogic.h
@@ -47,6 +47,11 @@ enum  {
 	    DS_VOLTAGE_RANGE_5_V,	/* 5V logic */
 };
 
+enum{
+	DS_EDGE_RISING,
+	DS_EDGE_FALLING
+};
+
 struct dslogic_version {
 	uint8_t major;
 	uint8_t minor;
diff --git a/src/hardware/fx2lafw/protocol.c b/src/hardware/fx2lafw/protocol.c
index 51134629..0fc3be26 100644
--- a/src/hardware/fx2lafw/protocol.c
+++ b/src/hardware/fx2lafw/protocol.c
@@ -307,6 +307,7 @@ SR_PRIV struct dev_context *fx2lafw_dev_new(void)
 	devc->capture_ratio = 0;
 	devc->sample_wide = FALSE;
 	devc->dslogic_continuous_mode = FALSE;
+	devc->dslogic_clock_edge = DS_EDGE_RISING;
 	devc->stl = NULL;
 
 	return devc;
diff --git a/src/hardware/fx2lafw/protocol.h b/src/hardware/fx2lafw/protocol.h
index b9ceebb7..a0d69c40 100644
--- a/src/hardware/fx2lafw/protocol.h
+++ b/src/hardware/fx2lafw/protocol.h
@@ -137,6 +137,7 @@ struct dev_context {
 	uint32_t trigger_pos;
 	gboolean dslogic_external_clock;
 	gboolean dslogic_continuous_mode;
+	int dslogic_clock_edge;
 	int dslogic_voltage_threshold;
 };