rigol-dg: Fix reading current output signal duty cycle value.
authorTimo Kokkonen <tjko@iki.fi>
Sat, 3 Oct 2020 23:35:10 +0000 (16:35 -0700)
committerGerhard Sittig <gerhard.sittig@gmx.net>
Sun, 4 Oct 2020 11:00:59 +0000 (13:00 +0200)
Reading output signal duty cycle value didn't always work, since it relied
on old (cached) information about the currently active waveform. Changed to
always query channel status so this won't happen anymore.

src/hardware/rigol-dg/api.c

index efe7db62ebe8aba650b629754412a25d138e84d8..43121aed57c02cf79685065075fb50fe5674ae9d 100644 (file)
@@ -490,6 +490,8 @@ static int config_get(uint32_t key, GVariant **data,
                                *data = g_variant_new_double(ch_status->phase);
                        break;
                case SR_CONF_DUTY_CYCLE:
+                       if ((ret = rigol_dg_get_channel_state(sdi, cg)) != SR_OK)
+                               break;
                        if (ch_status->wf == WF_SQUARE) {
                                cmd = PSG_CMD_GET_DCYCL_SQUARE;
                        } else if (ch_status->wf == WF_PULSE) {