return SR_OK;
}
-static void send_chunk(struct sr_dev_inst *sdi, transfer_packet_t *packets, unsigned int num_tfers)
+static void send_chunk(struct sr_dev_inst *sdi, const uint8_t *packets, unsigned int num_tfers)
{
struct dev_context *devc;
struct sr_datafeed_logic logic;
struct sr_datafeed_packet sr_packet;
- transfer_packet_t *packet;
- acq_packet_t *p;
- unsigned int max_samples, n_samples, total_samples, free_n_samples, ptotal;
+ unsigned int max_samples, n_samples, total_samples, free_n_samples;
unsigned int i, j, k;
int do_signal_trigger;
uint16_t *wp;
+ const uint8_t *rp;
+ uint16_t state;
+ uint8_t repetitions;
devc = sdi->priv;
devc->reading_behind_trigger = 1;
}
+ rp = packets;
for (i = 0; i < num_tfers; i++) {
- transfer_packet_host(packets[i]);
- packet = packets + i;
- ptotal = 0;
- for (k = 0; k < ARRAY_SIZE(packet->packet); k++) {
+ for (k = 0; k < NUM_PACKETS_IN_CHUNK; k++) {
free_n_samples = max_samples - n_samples;
if (free_n_samples < 256 || do_signal_trigger) {
logic.length = n_samples * 2;
do_signal_trigger = 0;
}
}
- p = packet->packet + k;
- for (j = 0; j < p->repetitions; j++)
- *(wp++) = p->state;
- n_samples += p->repetitions;
- total_samples += p->repetitions;
- ptotal += p->repetitions;
- devc->total_samples += p->repetitions;
+
+ state = read_u16le_inc(&rp);
+ repetitions = read_u8_inc(&rp);
+ for (j = 0; j < repetitions; j++)
+ *(wp++) = state;
+
+ n_samples += repetitions;
+ total_samples += repetitions;
+ devc->total_samples += repetitions;
if (!devc->reading_behind_trigger) {
devc->n_reps_until_trigger --;
if (devc->n_reps_until_trigger == 0) {
}
}
}
+ (void)read_u8_inc(&rp); /* Skip sequence number. */
}
if (n_samples) {
logic.length = n_samples * 2;
sr_err("bulk transfer timeout!");
devc->transfer_finished = 1;
}
- send_chunk(sdi, (transfer_packet_t*)transfer->buffer, transfer->actual_length / sizeof(transfer_packet_t));
+ send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH);
devc->n_bytes_to_read -= transfer->actual_length;
if (devc->n_bytes_to_read) {
struct drv_context *drvc;
struct sr_usb_dev_inst *usb;
struct sr_resource bitstream;
- uint32_t cmd;
+ uint8_t buffer[sizeof(uint32_t)];
+ uint8_t *wrptr;
uint8_t cmd_resp;
uint8_t block[4096];
int len, act_len;
}
devc->bitstream_size = (uint32_t)bitstream.size;
- WL32(&cmd, devc->bitstream_size);
- if ((ret = ctrl_out(sdi, 80, 0x00, 0, &cmd, sizeof(cmd))) != SR_OK) {
+ wrptr = buffer;
+ write_u32le_inc(&wrptr, devc->bitstream_size);
+ if ((ret = ctrl_out(sdi, 80, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
sr_err("failed to give upload init command");
sr_resource_close(drvc->sr_ctx, &bitstream);
return ret;
{
struct dev_context *devc;
float o1, o2, v1, v2, f;
- uint32_t cfg;
+ uint32_t cfgval;
+ uint8_t buffer[sizeof(uint32_t)];
+ uint8_t *wrptr;
int ret;
devc = sdi->priv;
o1 = 15859969; v1 = 0.45;
o2 = 15860333; v2 = 1.65;
f = (o2 - o1) / (v2 - v1);
- WL32(&cfg, (uint32_t)(o1 + (voltage - v1) * f));
+ cfgval = (uint32_t)(o1 + (voltage - v1) * f);
+ sr_dbg("set threshold voltage %.2fV, raw value 0x%lx",
+ voltage, (unsigned long)cfgval);
- sr_dbg("set threshold voltage %.2fV", voltage);
- ret = ctrl_out(sdi, 32, CTRL_THRESHOLD, 0, &cfg, sizeof(cfg));
+ wrptr = buffer;
+ write_u32le_inc(&wrptr, cfgval);
+ ret = ctrl_out(sdi, 32, CTRL_THRESHOLD, 0, buffer, wrptr - buffer);
if (ret != SR_OK) {
- sr_err("error setting new threshold voltage of %.2fV (%d)", voltage, RL16(&cfg));
+ sr_err("Error setting %.2fV threshold voltage (%d)",
+ voltage, ret);
return ret;
}
devc->threshold_voltage = voltage;
pwm_setting_dev_t cfg;
pwm_setting_t *setting;
int ret;
+ uint8_t buf[2 * sizeof(uint32_t)];
+ uint8_t *wrptr;
devc = sdi->priv;
cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.));
sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty);
- pwm_setting_dev_le(cfg);
- ret = ctrl_out(sdi, 32, CTRL_PWM[which - 1], 0, &cfg, sizeof(cfg));
+ wrptr = buf;
+ write_u32le_inc(&wrptr, cfg.period);
+ write_u32le_inc(&wrptr, cfg.duty);
+ ret = ctrl_out(sdi, 32, CTRL_PWM[which - 1], 0, buf, wrptr - buf);
if (ret != SR_OK) {
sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty);
return ret;
setting = &devc->pwm_setting[which - 1];
setting->freq = freq;
setting->duty = duty;
- setting->dev = cfg;
return SR_OK;
}
struct sr_trigger_match *match;
uint16_t ch_mask;
int ret;
+ uint8_t buf[4 * sizeof(uint32_t)];
+ uint8_t *wrptr;
devc = sdi->priv;
trigger = sr_session_trigger_get(sdi->session);
devc->had_triggers_configured = cfg.enabled != 0;
- trigger_cfg_le(cfg);
- ret = ctrl_out(sdi, 32, CTRL_TRIGGER, 16, &cfg, sizeof(cfg));
+ wrptr = buf;
+ write_u32le_inc(&wrptr, cfg.channels);
+ write_u32le_inc(&wrptr, cfg.enabled);
+ write_u32le_inc(&wrptr, cfg.level);
+ write_u32le_inc(&wrptr, cfg.high_or_falling);
+ ret = ctrl_out(sdi, 32, CTRL_TRIGGER, 16, buf, wrptr - buf);
if (ret != SR_OK) {
sr_err("error setting trigger config!");
return ret;
static int set_sample_config(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
- sample_config_t cfg;
double clock_divisor;
uint64_t psa;
uint64_t total;
int ret;
+ uint16_t divisor;
+ uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)];
+ uint8_t *wrptr;
devc = sdi->priv;
total = 128 * 1024 * 1024;
clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate;
if (clock_divisor > 0xffff)
clock_divisor = 0xffff;
- cfg.clock_divisor = (uint16_t)(clock_divisor + 0.5);
- devc->cur_samplerate = MAX_SAMPLE_RATE / cfg.clock_divisor;
+ divisor = (uint16_t)(clock_divisor + 0.5);
+ devc->cur_samplerate = MAX_SAMPLE_RATE / divisor;
if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
sr_err("too high sample depth: %" PRIu64, devc->limit_samples);
return SR_ERR;
}
- cfg.sample_depth = devc->limit_samples;
devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100;
- psa = devc->pre_trigger_size * 256;
- cfg.psa = (uint32_t)(psa & 0xffffffff);
- cfg.u1 = (uint16_t)((psa >> 32) & 0xffff);
- cfg.u2 = (uint32_t)((total * devc->capture_ratio) / 100);
-
sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%",
- devc->cur_samplerate/1e3, (unsigned int)cfg.sample_depth, (unsigned int)devc->capture_ratio);
+ devc->cur_samplerate/1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio);
- sample_config_le(cfg);
- ret = ctrl_out(sdi, 32, CTRL_SAMPLING, 0, &cfg, sizeof(cfg));
+ psa = devc->pre_trigger_size * 256;
+ wrptr = buf;
+ write_u32le_inc(&wrptr, devc->limit_samples);
+ write_u48le_inc(&wrptr, psa);
+ write_u32le_inc(&wrptr, (total * devc->capture_ratio) / 100);
+ write_u16le_inc(&wrptr, clock_divisor);
+
+ ret = ctrl_out(sdi, 32, CTRL_SAMPLING, 0, buf, wrptr - buf);
if (ret != SR_OK) {
sr_err("error setting sample config!");
return ret;
{
struct dev_context *devc;
int ret;
+ uint8_t buf[3 * sizeof(uint32_t)];
+ const uint8_t *rdptr;
devc = sdi->priv;
- if ((ret = ctrl_in(sdi, 32, CTRL_BULK, 0, &devc->info, sizeof(devc->info))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, 32, CTRL_BULK, 0, buf, sizeof(buf))) != SR_OK) {
sr_err("failed to read capture info!");
return ret;
}
- capture_info_host(devc->info);
+
+ rdptr = buf;
+ devc->info.n_rep_packets = read_u32le_inc(&rdptr);
+ devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
+ devc->info.write_pos = read_u32le_inc(&rdptr);
sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d",
devc->info.n_rep_packets, devc->info.n_rep_packets,
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
int ret;
- uint32_t bulk_cfg[2];
+ uint8_t wrbuf[2 * sizeof(uint32_t)];
+ uint8_t *wrptr;
uint32_t to_read;
uint8_t *buffer;
if ((ret = get_capture_info(sdi)) != SR_OK)
return ret;
- devc->n_transfer_packets_to_read = devc->info.n_rep_packets / 5;
- devc->n_bytes_to_read = devc->n_transfer_packets_to_read * sizeof(transfer_packet_t);
+ devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
+ devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH;
devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
sr_err("failed to reset bulk state");
return ret;
}
- WL32(&bulk_cfg[0], devc->read_pos);
- WL32(&bulk_cfg[1], devc->n_bytes_to_read);
sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read);
- if ((ret = ctrl_out(sdi, 32, CTRL_BULK, 0, &bulk_cfg, sizeof(bulk_cfg))) != SR_OK) {
+ wrptr = wrbuf;
+ write_u32le_inc(&wrptr, devc->read_pos);
+ write_u32le_inc(&wrptr, devc->n_bytes_to_read);
+ if ((ret = ctrl_out(sdi, 32, CTRL_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) {
sr_err("failed to send bulk config");
return ret;
}
#define LOG_PREFIX "kingst-la2016"
-/* device is little endian */
-
#define LA2016_VID 0x77a1
#define LA2016_PID 0x01a2
#define USB_INTERFACE 0
typedef struct pwm_setting_dev {
uint32_t period;
uint32_t duty;
-} __attribute__((__packed__)) pwm_setting_dev_t;
+} pwm_setting_dev_t;
typedef struct trigger_cfg {
uint32_t channels;
uint32_t enabled;
uint32_t level;
uint32_t high_or_falling;
-} __attribute__((__packed__)) trigger_cfg_t;
-
-typedef struct sample_config {
- uint32_t sample_depth;
- uint32_t psa;
- uint16_t u1;
- uint32_t u2;
- uint16_t clock_divisor;
-} __attribute__((__packed__)) sample_config_t;
+} trigger_cfg_t;
typedef struct capture_info {
uint32_t n_rep_packets;
uint32_t n_rep_packets_before_trigger;
uint32_t write_pos;
-} __attribute__((__packed__)) capture_info_t;
-
-typedef struct acq_packet {
- uint16_t state;
- uint8_t repetitions;
-} __attribute__((__packed__)) acq_packet_t;
+} capture_info_t;
-typedef struct transfer_packet {
- acq_packet_t packet[5];
- uint8_t seq;
-} __attribute__((__packed__)) transfer_packet_t;
+#define NUM_PACKETS_IN_CHUNK 5
+#define TRANSFER_PACKET_LENGTH 16
typedef struct pwm_setting {
uint8_t enabled;
float freq;
float duty;
- pwm_setting_dev_t dev;
} pwm_setting_t;
struct dev_context {
SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi);
SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi);
-#ifndef WORDS_BIGENDIAN
-/* this host is big-endian, need to swap from/to device inplace */
-#define inplace_WL32(obj) do { uint32_t tmp = obj; WL32(&(obj), tmp); } while (0)
-#define inplace_RL32(obj) obj = RL32(&(obj))
-#define inplace_WL16(obj) do { uint16_t tmp = obj; WL16(&(obj), tmp); } while (0)
-#define inplace_RL16(obj) obj = RL16(&(obj))
-
-#define pwm_setting_dev_le(obj) do { \
- inplace_WL32((obj).period); \
- inplace_WL32((obj).duty); \
- } while (0)
-#define trigger_cfg_le(obj) do { \
- inplace_WL32((obj).channels); \
- inplace_WL32((obj).enabled); \
- inplace_WL32((obj).level); \
- inplace_WL32((obj).high_or_falling); \
- } while (0)
-#define sample_config_le(obj) do { \
- inplace_WL32((obj).sample_depth); \
- inplace_WL32((obj).psa); \
- inplace_WL16((obj).u1); \
- inplace_WL32((obj).u2); \
- inplace_WL16((obj).clock_divisor); \
- } while (0)
-
-#define capture_info_host(obj) do { \
- inplace_RL32((obj).n_rep_packets); \
- inplace_RL32((obj).n_rep_packets_before_trigger); \
- inplace_RL32((obj).write_pos); \
- } while (0)
-#define acq_packet_host(obj) \
- inplace_RL16((obj).state)
-#define transfer_packet_host(obj) do { \
- acq_packet_host((obj).packet[0]); \
- acq_packet_host((obj).packet[1]); \
- acq_packet_host((obj).packet[2]); \
- acq_packet_host((obj).packet[3]); \
- acq_packet_host((obj).packet[4]); \
- } while (0)
-
-#else
-/* this host is little-endian, same as device */
-#define pwm_setting_dev_le(obj) (void)obj
-#define trigger_cfg_le(obj) (void)obj
-#define sample_config_le(obj) (void)obj
-
-#define capture_info_host(obj) (void)obj
-#define acq_packet_host(obj) (void)obj
-#define transfer_packet_host(obj) (void)obj
-#endif
-
#endif
projects / libsigrok.git / commitdiff