input: decorate sr_input_find() parameter as const master
authorGerhard Sittig <gerhard.sittig@gmx.net>
Sat, 23 Apr 2022 19:01:12 +0000 (21:01 +0200)
committerGerhard Sittig <gerhard.sittig@gmx.net>
Sat, 23 Apr 2022 19:54:34 +0000 (21:54 +0200)
The caller's input module name is only read for comparison. Decorate it
with the 'const' attribute to simplify calling application code.

45 files changed:
README
README.devices
configure.ac
contrib/60-libsigrok.rules
include/libsigrok/proto.h
src/device.c
src/hardware/arachnid-labs-re-load-pro/api.c
src/hardware/atten-pps3xxx/api.c
src/hardware/baylibre-acme/protocol.c
src/hardware/dcttech-usbrelay/api.c
src/hardware/demo/api.c
src/hardware/dreamsourcelab-dslogic/api.c
src/hardware/fx2lafw/api.c
src/hardware/gwinstek-gds-800/api.c
src/hardware/gwinstek-gpd/api.c
src/hardware/hameg-hmo/protocol.c
src/hardware/hantek-4032l/api.c
src/hardware/hantek-6xxx/api.c
src/hardware/hantek-dso/api.c
src/hardware/hp-3457a/api.c
src/hardware/hp-3478a/protocol.c
src/hardware/hp-59306a/api.c
src/hardware/hung-chang-dso-2100/api.c
src/hardware/itech-it8500/api.c
src/hardware/kingst-la2016/api.c
src/hardware/kingst-la2016/protocol.c
src/hardware/kingst-la2016/protocol.h
src/hardware/lecroy-xstream/protocol.c
src/hardware/maynuo-m97/api.c
src/hardware/microchip-pickit2/api.c
src/hardware/motech-lps-30x/api.c
src/hardware/rdtech-dps/protocol.c
src/hardware/rigol-dg/api.c
src/hardware/rigol-ds/api.c
src/hardware/scpi-pps/api.c
src/hardware/siglent-sds/api.c
src/hardware/yokogawa-dlm/protocol.c
src/input/input.c
src/input/logicport.c
src/input/vcd.c
src/libsigrok-internal.h
src/std.c
tests/analog.c
tests/conv.c
tests/strutil.c

diff --git a/README b/README
index 768c8ca2b6612d1850d69f8f25e95c830850aef7..ecdc2fd92875f35f14dd23c629c8a46503a289e7 100644 (file)
--- a/README
+++ b/README
@@ -49,6 +49,7 @@ Requirements for the C library:
  - libgpib (optional, used by some drivers)
  - libieee1284 (optional, used by some drivers)
  - libgio >= 2.32.0 (optional, used by some drivers)
+ - nettle (optional, used by some drivers)
  - check >= 0.9.4 (optional, only needed to run unit tests)
  - doxygen (optional, only needed for the C API docs)
  - graphviz (optional, only needed for the C API docs)
index 226ec06ba59691b2c37a3548987d963d79ae3080..d2f4db8ca1bd973432e04456bc93e54e48fc5a27 100644 (file)
@@ -288,6 +288,19 @@ rules shipped by the system will be broken.
 Please consult the udev docs for details.
 
 
+Assigning drivers to devices (Windows, Zadig)
+---------------------------------------------
+
+On Windows systems it may be necessary to assign drivers to devices
+before libusb based applications can access them. It may be necessary
+to re-run this driver assignment after firmware upload in case the
+device changes its USB identification as a consequence of loading the
+firmware image.
+
+The https://sigrok.org/wiki/Windows wiki page discusses this subject,
+and other platform specific aspects.
+
+
 Non-default drivers for commodity chips
 ---------------------------------------
 
@@ -390,6 +403,18 @@ See also: http://erste.de/UT61/index.html
   done
 
 
+UNI-T UT-D04 cable issue on Windows
+-----------------------------------
+
+There have been reports that CH9325 based cables are not detected on
+Windows out of the box when they are assigned to libwdi drivers. Though
+they may be usable in that case when the USB address is manually specified.
+This can happen when some "USB to serial" driver is assigned which does not
+provide a genuine COM port that enumerates naturally. Manually assigning a
+"USB input device" driver can improve HIDAPI compatibility and make the
+cable show up in sigrok's serial port enumeration.
+
+
 Enabling multimeter / data logger measurement output
 ----------------------------------------------------
 
index 424b00022729e4ba70671bfdc17518c3b8646ed0..5c4808183b3625a8e453ecfec110453f13aa7429 100644 (file)
@@ -630,9 +630,6 @@ AC_CHECK_FUNCS([ftdi_tciflush ftdi_tcoflush ftdi_tcioflush])
 LIBS=$sr_save_libs
 CFLAGS=$sr_save_cflags
 
-AM_COND_IF([NEED_USB], [AS_CASE([$sr_have_libusb_os_handle:$host_os], [no:mingw*],
-       [AC_MSG_ERROR([Windows builds require the event-abstraction branch of libusb])])])
-
 sr_glib_version=`$PKG_CONFIG --modversion glib-2.0 2>&AS_MESSAGE_LOG_FD`
 sr_libzip_version=`$PKG_CONFIG --modversion libzip 2>&AS_MESSAGE_LOG_FD`
 sr_zlib_version=`$PKG_CONFIG --modversion zlib 2>&AS_MESSAGE_LOG_FD`
index f6ae259f4f9666b4f2acf01485bc0716cabb1eea..569bac7cd0c2f737e142303b8a6042624e4c15be 100644 (file)
@@ -49,7 +49,9 @@ ATTRS{idVendor}=="0957", ATTRS{idProduct}=="1735", ENV{ID_SIGROK}="1"
 
 # ASIX SIGMA
 # ASIX SIGMA2
+# ASIX OMEGA
 ATTRS{idVendor}=="a600", ATTRS{idProduct}=="a000", ENV{ID_SIGROK}="1"
+ATTRS{idVendor}=="a600", ATTRS{idProduct}=="a004", ENV{ID_SIGROK}="1"
 
 # Braintechnology USB-LPS
 ATTRS{idVendor}=="16d0", ATTRS{idProduct}=="0498", ENV{ID_SIGROK}="1"
index 41d9cfcc672931f62bac06a648d24a171bcceb76..357512ca0a8103a59204668f86445881964e219f 100644 (file)
@@ -166,7 +166,7 @@ SR_API const char *sr_input_name_get(const struct sr_input_module *imod);
 SR_API const char *sr_input_description_get(const struct sr_input_module *imod);
 SR_API const char *const *sr_input_extensions_get(
                const struct sr_input_module *imod);
-SR_API const struct sr_input_module *sr_input_find(char *id);
+SR_API const struct sr_input_module *sr_input_find(const char *id);
 SR_API const struct sr_option **sr_input_options_get(const struct sr_input_module *imod);
 SR_API void sr_input_options_free(const struct sr_option **options);
 SR_API struct sr_input *sr_input_new(const struct sr_input_module *imod,
index 5a144d97ebccf3b160117b64f17c3be604e9367f..7973d1e53629e0ccba5d4bf76b1e5f1fa8e37034 100644 (file)
@@ -255,6 +255,62 @@ SR_PRIV gboolean sr_channel_lists_differ(GSList *l1, GSList *l2)
        return FALSE;
 }
 
+/**
+ * Allocate and initialize a new channel group, and add it to sdi.
+ *
+ * @param[in] sdi The device instance the channel group is connected to.
+ *                Optional, can be NULL.
+ * @param[in] name @copydoc sr_channel_group::name
+ * @param[in] priv @copydoc sr_channel_group::priv
+ *
+ * @return A pointer to a new struct sr_channel_group, NULL upon error.
+ *
+ * @private
+ */
+SR_PRIV struct sr_channel_group *sr_channel_group_new(struct sr_dev_inst *sdi,
+       const char *name, void *priv)
+{
+       struct sr_channel_group *cg;
+
+       cg = g_malloc0(sizeof(*cg));
+       if (name && *name)
+               cg->name = g_strdup(name);
+       cg->priv = priv;
+
+       if (sdi)
+               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
+
+       return cg;
+}
+
+/**
+ * Release a previously allocated struct sr_channel_group.
+ *
+ * @param[in] cg Pointer to struct sr_channel_group.
+ *
+ * @private
+ */
+SR_PRIV void sr_channel_group_free(struct sr_channel_group *cg)
+{
+       if (!cg)
+               return;
+
+       g_free(cg->name);
+       g_slist_free(cg->channels);
+       g_free(cg->priv);
+       g_free(cg);
+}
+
+/**
+ * Wrapper around sr_channel_group_free(), suitable for glib iterators.
+ *
+ * @private
+ */
+SR_PRIV void sr_channel_group_free_cb(void *cg)
+{
+       return sr_channel_group_free(cg);
+}
+
 /**
  * Determine whether the specified device instance has the specified
  * capability.
@@ -448,7 +504,6 @@ SR_API int sr_dev_inst_channel_add(struct sr_dev_inst *sdi, int index, int type,
 SR_PRIV void sr_dev_inst_free(struct sr_dev_inst *sdi)
 {
        struct sr_channel *ch;
-       struct sr_channel_group *cg;
        GSList *l;
 
        if (!sdi)
@@ -459,15 +514,7 @@ SR_PRIV void sr_dev_inst_free(struct sr_dev_inst *sdi)
                sr_channel_free(ch);
        }
        g_slist_free(sdi->channels);
-
-       for (l = sdi->channel_groups; l; l = l->next) {
-               cg = l->data;
-               g_free(cg->name);
-               g_slist_free(cg->channels);
-               g_free(cg->priv);
-               g_free(cg);
-       }
-       g_slist_free(sdi->channel_groups);
+       g_slist_free_full(sdi->channel_groups, sr_channel_group_free_cb);
 
        if (sdi->session)
                sr_session_dev_remove(sdi->session, sdi);
@@ -519,6 +566,15 @@ SR_PRIV void sr_usb_dev_inst_free(struct sr_usb_dev_inst *usb)
        g_free(usb);
 }
 
+/**
+ * Wrapper for g_slist_free_full() convenience.
+ *
+ * @private
+ */
+SR_PRIV void sr_usb_dev_inst_free_cb(gpointer p)
+{
+       sr_usb_dev_inst_free(p);
+}
 #endif
 
 #ifdef HAVE_SERIAL_COMM
index fb6f82727dedd9eafe515a5b27310bed96c6075d..c14c20d400d05db58c3c55b32680f91893666b8e 100644 (file)
@@ -146,9 +146,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
        sdi->inst_type = SR_INST_SERIAL;
        sdi->conn = serial;
 
-       cg = g_malloc0(sizeof(struct sr_channel_group));
-       cg->name = g_strdup("1");
-       sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
+       cg = sr_channel_group_new(sdi, "1", NULL);
 
        ch = sr_channel_new(sdi, 0, SR_CHANNEL_ANALOG, TRUE, "V");
        cg->channels = g_slist_append(cg->channels, ch);
index dc6e5201977d30769956521c1450ffebfd8eb8b4..28b22015d3fd13f449c0379cf7f84d92b5e8363b 100644 (file)
@@ -157,11 +157,8 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options, int modelid)
        for (i = 0; i < MAX_CHANNELS; i++) {
                snprintf(channel, 10, "CH%d", i + 1);
                ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel);
-               cg = g_malloc(sizeof(struct sr_channel_group));
-               cg->name = g_strdup(channel);
+               cg = sr_channel_group_new(sdi, channel, NULL);
                cg->channels = g_slist_append(NULL, ch);
-               cg->priv = NULL;
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
        }
 
        devc = g_malloc0(sizeof(struct dev_context));
index 89391d5482286e541873910e457be935b6e7818b..8d23b9e2f9875d36093115c52b1911c3e1ac1e2a 100644 (file)
@@ -332,9 +332,8 @@ SR_PRIV gboolean bl_acme_register_probe(struct sr_dev_inst *sdi, int type,
        if (hwmon < 0)
                return FALSE;
 
-       cg = g_malloc0(sizeof(struct sr_channel_group));
        cgp = g_malloc0(sizeof(struct channel_group_priv));
-       cg->priv = cgp;
+       cg = sr_channel_group_new(sdi, NULL, cgp);
 
        /*
         * See if we can read the EEPROM contents. If not, assume it's
@@ -380,8 +379,6 @@ SR_PRIV gboolean bl_acme_register_probe(struct sr_dev_inst *sdi, int type,
                sr_err("Invalid probe type: %d.", type);
        }
 
-       sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
-
        return TRUE;
 }
 
index 137277d0176b014758883bba82d988cd1c58a985..deeb234a95eb2e72e640e6a3d0bcc8e2b9e328a6 100644 (file)
@@ -63,6 +63,7 @@ static struct sr_dev_inst *probe_device_common(const char *path,
        struct channel_group_context *cgc;
        size_t idx, nr;
        struct sr_channel_group *cg;
+       char cg_name[24];
 
        /*
         * Get relay count from product string. Weak condition,
@@ -153,12 +154,11 @@ static struct sr_dev_inst *probe_device_common(const char *path,
        devc->relay_mask = (1U << relay_count) - 1;
        for (idx = 0; idx < devc->relay_count; idx++) {
                nr = idx + 1;
-               cg = g_malloc0(sizeof(*cg));
-               cg->name = g_strdup_printf("R%zu", nr);
+               snprintf(cg_name, sizeof(cg_name), "R%zu", nr);
                cgc = g_malloc0(sizeof(*cgc));
-               cg->priv = cgc;
                cgc->number = nr;
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
+               cg = sr_channel_group_new(sdi, cg_name, cgc);
+               (void)cg;
        }
 
        return sdi;
index ba317fbe4a1b8fa389a8de39966c833956820659..bea35d068f63042a04fd7b27b6d691f3778ad0fb 100644 (file)
@@ -151,14 +151,12 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 
        if (num_logic_channels > 0) {
                /* Logic channels, all in one channel group. */
-               cg = g_malloc0(sizeof(struct sr_channel_group));
-               cg->name = g_strdup("Logic");
+               cg = sr_channel_group_new(sdi, "Logic", NULL);
                for (i = 0; i < num_logic_channels; i++) {
                        sprintf(channel_name, "D%d", i);
                        ch = sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_name);
                        cg->channels = g_slist_append(cg->channels, ch);
                }
-               sdi->channel_groups = g_slist_append(NULL, cg);
        }
 
        /* Analog channels, channel groups and pattern generators. */
@@ -173,9 +171,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 
                pattern = 0;
                /* An "Analog" channel group with all analog channels in it. */
-               acg = g_malloc0(sizeof(struct sr_channel_group));
-               acg->name = g_strdup("Analog");
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, acg);
+               acg = sr_channel_group_new(sdi, "Analog", NULL);
 
                for (i = 0; i < num_analog_channels; i++) {
                        snprintf(channel_name, 16, "A%d", i);
@@ -184,10 +180,8 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
                        acg->channels = g_slist_append(acg->channels, ch);
 
                        /* Every analog channel gets its own channel group as well. */
-                       cg = g_malloc0(sizeof(struct sr_channel_group));
-                       cg->name = g_strdup(channel_name);
+                       cg = sr_channel_group_new(sdi, channel_name, NULL);
                        cg->channels = g_slist_append(NULL, ch);
-                       sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
 
                        /* Every channel gets a generator struct. */
                        ag = g_malloc(sizeof(struct analog_gen));
index 98f4acdb159269efed773f517a18d96f9e119503..6d5b7fc7d6cd009d5bf90c8f043fa0cc28162993 100644 (file)
@@ -240,15 +240,13 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
                sdi->connection_id = g_strdup(connection_id);
 
                /* Logic channels, all in one channel group. */
-               cg = g_malloc0(sizeof(struct sr_channel_group));
-               cg->name = g_strdup("Logic");
+               cg = sr_channel_group_new(sdi, "Logic", NULL);
                for (j = 0; j < NUM_CHANNELS; j++) {
                        sprintf(channel_name, "%d", j);
                        ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC,
                                                TRUE, channel_name);
                        cg->channels = g_slist_append(cg->channels, ch);
                }
-               sdi->channel_groups = g_slist_append(NULL, cg);
 
                devc = dslogic_dev_new();
                devc->profile = prof;
index 5acb0016d0b8e6ab5ad204aea7e238f55e2f5fa8..4665bca2419deae0f0347e6e2aa5039462ef04d0 100644 (file)
@@ -306,15 +306,13 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
                num_analog_channels = prof->dev_caps & DEV_CAPS_AX_ANALOG ? 1 : 0;
 
                /* Logic channels, all in one channel group. */
-               cg = g_malloc0(sizeof(struct sr_channel_group));
-               cg->name = g_strdup("Logic");
+               cg = sr_channel_group_new(sdi, "Logic", NULL);
                for (j = 0; j < num_logic_channels; j++) {
                        sprintf(channel_name, "D%d", j);
                        ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC,
                                                TRUE, channel_name);
                        cg->channels = g_slist_append(cg->channels, ch);
                }
-               sdi->channel_groups = g_slist_append(NULL, cg);
 
                for (j = 0; j < num_analog_channels; j++) {
                        snprintf(channel_name, 16, "A%d", j);
@@ -322,10 +320,8 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
                                        SR_CHANNEL_ANALOG, TRUE, channel_name);
 
                        /* Every analog channel gets its own channel group. */
-                       cg = g_malloc0(sizeof(struct sr_channel_group));
-                       cg->name = g_strdup(channel_name);
+                       cg = sr_channel_group_new(sdi, channel_name, NULL);
                        cg->channels = g_slist_append(NULL, ch);
-                       sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
                }
 
                devc = fx2lafw_dev_new();
index 22ac40e6c77ef0192e64601f24d53abf8aecd00c..6e9b85bbbb6d89374cf71e43cd3e67cedf03fc21 100644 (file)
@@ -76,12 +76,9 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
        sr_channel_new(sdi, 0, SR_CHANNEL_ANALOG, TRUE, "CH1");
        sr_channel_new(sdi, 1, SR_CHANNEL_ANALOG, TRUE, "CH2");
 
-       cg = g_malloc0(sizeof(struct sr_channel_group));
-       cg->name = g_strdup("");
+       cg = sr_channel_group_new(sdi, "", NULL);
        cg->channels = g_slist_append(cg->channels, g_slist_nth_data(sdi->channels, 0));
        cg->channels = g_slist_append(cg->channels, g_slist_nth_data(sdi->channels, 1));
-       cg->priv = NULL;
-       sdi->channel_groups = g_slist_append(NULL, cg);
 
        return sdi;
 }
index 2b685202733612b8e6db6262f47841c8080b69bf..a85be2ed3d433746338580b0544e0aecac5ccbe9 100644 (file)
@@ -194,11 +194,8 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
                for (i = 0; i < model->num_channels; i++) {
                        snprintf(channel, sizeof(channel), "CH%d", i + 1);
                        ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel);
-                       cg = g_malloc(sizeof(struct sr_channel_group));
-                       cg->name = g_strdup(channel);
+                       cg = sr_channel_group_new(sdi, channel, NULL);
                        cg->channels = g_slist_append(NULL, ch);
-                       cg->priv = NULL;
-                       sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
                }
 
                devc = g_malloc0(sizeof(struct dev_context));
index 26dac0cb037f34de3a8e370bc2d74a99285a799d..1e9622af16db9329de6bc827678202cb20737f53 100644 (file)
@@ -1192,6 +1192,7 @@ SR_PRIV int hmo_init_device(struct sr_dev_inst *sdi)
        unsigned int i, j, group;
        struct sr_channel *ch;
        struct dev_context *devc;
+       const char *cg_name;
        int ret;
 
        devc = sdi->priv;
@@ -1232,27 +1233,20 @@ SR_PRIV int hmo_init_device(struct sr_dev_inst *sdi)
                ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE,
                           (*scope_models[model_index].analog_names)[i]);
 
-               devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
-
-               devc->analog_groups[i]->name = g_strdup(
-                       (char *)(*scope_models[model_index].analog_names)[i]);
+               cg_name = (*scope_models[model_index].analog_names)[i];
+               devc->analog_groups[i] = sr_channel_group_new(sdi, cg_name, NULL);
                devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
-
-               sdi->channel_groups = g_slist_append(sdi->channel_groups,
-                                                  devc->analog_groups[i]);
        }
 
        /* Add digital channel groups. */
        ret = SR_OK;
        for (i = 0; i < scope_models[model_index].digital_pods; i++) {
-               devc->digital_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
+               devc->digital_groups[i] = sr_channel_group_new(sdi, NULL, NULL);
                if (!devc->digital_groups[i]) {
                        ret = SR_ERR_MALLOC;
                        break;
                }
                devc->digital_groups[i]->name = g_strdup_printf("POD%d", i + 1);
-               sdi->channel_groups = g_slist_append(sdi->channel_groups,
-                                  devc->digital_groups[i]);
        }
        if (ret != SR_OK)
                return ret;
index 26a9315e5035024c9559f679a950576a72246b95..7e823f8c7935cb9eb1422fcc6e1fdb5b389f991c 100644 (file)
@@ -233,10 +233,9 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 
                struct sr_channel_group *channel_groups[2];
                for (int j = 0; j < 2; j++) {
-                       cg = g_malloc0(sizeof(struct sr_channel_group));
+                       cg = sr_channel_group_new(sdi, NULL, NULL);
                        cg->name = g_strdup_printf("%c", 'A' + j);
                        channel_groups[j] = cg;
-                       sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
                }
 
                /* Assemble channel list and add channel to channel groups. */
index 408d1fcdcc03ec026edd2a57ba9c140855d7c9d2..41a77795cee84ed5916457b3bc156b8240ccf2c0 100644 (file)
@@ -140,10 +140,8 @@ static struct sr_dev_inst *hantek_6xxx_dev_new(const struct hantek_6xxx_profile
 
        for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
                ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel_names[i]);
-               cg = g_malloc0(sizeof(struct sr_channel_group));
-               cg->name = g_strdup(channel_names[i]);
+               cg = sr_channel_group_new(sdi, channel_names[i], NULL);
                cg->channels = g_slist_append(cg->channels, ch);
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
        }
 
        devc = g_malloc0(sizeof(struct dev_context));
index a3cc8a283304ae233ebb1c857ad13eb08be2e094..f0cbb6158276048186c11a6e970f76adb6b683ce 100644 (file)
@@ -199,10 +199,8 @@ static struct sr_dev_inst *dso_dev_new(const struct dso_profile *prof)
         */
        for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
                ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel_names[i]);
-               cg = g_malloc0(sizeof(struct sr_channel_group));
-               cg->name = g_strdup(channel_names[i]);
+               cg = sr_channel_group_new(sdi, channel_names[i], NULL);
                cg->channels = g_slist_append(cg->channels, ch);
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
        }
 
        devc = g_malloc0(sizeof(struct dev_context));
index 4cfc2d758b54e79625609d408ef0f506d028a5b7..9f006df5600f43889b8a58bfde775c079c49c14d 100644 (file)
@@ -52,12 +52,9 @@ static int create_front_channel(struct sr_dev_inst *sdi, int chan_idx)
                                 TRUE, "Front");
        channel->priv = chanc;
 
-       front = g_malloc0(sizeof(*front));
-       front->name = g_strdup("Front");
+       front = sr_channel_group_new(sdi, "Front", NULL);
        front->channels = g_slist_append(front->channels, channel);
 
-       sdi->channel_groups = g_slist_append(sdi->channel_groups, front);
-
        return chan_idx;
 }
 
@@ -74,10 +71,7 @@ static int create_rear_channels(struct sr_dev_inst *sdi, int chan_idx,
        if (!card)
                return chan_idx;
 
-       group = g_malloc0(sizeof(*group));
-       group->priv = NULL;
-       group->name = g_strdup(card->cg_name);
-       sdi->channel_groups = g_slist_append(sdi->channel_groups, group);
+       group = sr_channel_group_new(sdi, card->cg_name, NULL);
 
        for (i = 0; i < card->num_channels; i++) {
 
index 2e9130b022a9ab01832701ebdae41eb0c1533c47..ed8878bec5a25c8560950713b0ba21caf942d740 100644 (file)
@@ -489,7 +489,7 @@ SR_PRIV int hp_3478a_receive_data(int fd, int revents, void *cb_data)
         */
        if (sr_scpi_gpib_spoll(scpi, &status_register) != SR_OK)
                return FALSE;
-       if (!(((uint8_t)status_register) & 0x01))
+       if (!(((uint8_t)status_register) & SRQ_BUS_AVAIL))
                return TRUE;
 
        /* Get a reading from the DMM. */
index c7a0afca5b2ad34d11309313754c0aa0a5fbb45e..d2b840041d36dc227979f5b6dfde0a8f353372a4 100644 (file)
@@ -47,6 +47,7 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
        struct channel_group_context *cgc;
        size_t idx, nr;
        struct sr_channel_group *cg;
+       char cg_name[24];
 
        /*
         * The device cannot get identified by means of SCPI queries.
@@ -73,15 +74,11 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
        devc->channel_count = 6;
        for (idx = 0; idx < devc->channel_count; idx++) {
                nr = idx + 1;
-
-               cg = g_malloc0(sizeof(*cg));
-               cg->name = g_strdup_printf("R%zu", nr);
-
+               snprintf(cg_name, sizeof(cg_name), "R%zu", nr);
                cgc = g_malloc0(sizeof(*cgc));
                cgc->number = nr;
-               cg->priv = cgc;
-
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
+               cg = sr_channel_group_new(sdi, cg_name, cgc);
+               (void)cg;
        }
 
        return sdi;
index f3d94d2003d386de64760e37d31d4499f20b2bb0..88423357592dd6eeefa230abf980ddab09015fbf 100644 (file)
@@ -138,11 +138,9 @@ static GSList *scan_port(GSList *devices, struct parport *port)
        ieee1284_ref(port);
 
        for (i = 0; i < NUM_CHANNELS; i++) {
-               cg = g_malloc0(sizeof(struct sr_channel_group));
-               cg->name = g_strdup(trigger_sources[i]);
+               cg = sr_channel_group_new(sdi, trigger_sources[i], NULL);
                ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, FALSE, trigger_sources[i]);
                cg->channels = g_slist_append(cg->channels, ch);
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
        }
 
        devc = g_malloc0(sizeof(struct dev_context));
index a720af5207aea98f414025aa983c4ed91f092e18..f6156f761de6d72bd0dc03c1099fc6161275dec8 100644 (file)
@@ -270,9 +270,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
        sdi->version = g_strdup_printf("%x.%02x", fw_major, fw_minor);
        sdi->serial_num = unit_serial;
 
-       cg = g_malloc0(sizeof(*cg));
-       cg->name = g_strdup("1");
-       sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
+       cg = sr_channel_group_new(sdi, "1", NULL);
        ch = sr_channel_new(sdi, 0, SR_CHANNEL_ANALOG, TRUE, "V1");
        cg->channels = g_slist_append(cg->channels, ch);
        ch = sr_channel_new(sdi, 1, SR_CHANNEL_ANALOG, TRUE, "I1");
index 216869ed8f222b29bb7599712a24e26ee72b01c4..ab44d3b380a26b7974d15aca2529a8f066a8c4d2 100644 (file)
@@ -1,6 +1,7 @@
 /*
  * This file is part of the libsigrok project.
  *
+ * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net>
  * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
  * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/* mostly stolen from src/hardware/saleae-logic16/ */
+/*
+ * This driver implementation initially was derived from the
+ * src/hardware/saleae-logic16/ source code.
+ */
 
 #include <config.h>
-#include <glib.h>
-#include <libusb.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
+
 #include <libsigrok/libsigrok.h>
+#include <string.h>
+
 #include "libsigrok-internal.h"
 #include "protocol.h"
 
@@ -38,18 +40,32 @@ static const uint32_t scanopts[] = {
 
 static const uint32_t drvopts[] = {
        SR_CONF_LOGIC_ANALYZER,
+       SR_CONF_SIGNAL_GENERATOR,
 };
 
 static const uint32_t devopts[] = {
-       /* TODO: SR_CONF_CONTINUOUS, */
        SR_CONF_CONN | SR_CONF_GET,
        SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
-       SR_CONF_LIMIT_SAMPLES | SR_CONF_SET | SR_CONF_GET | SR_CONF_LIST,
+       SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+       SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
+#if WITH_THRESHOLD_DEVCFG
        SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
-       SR_CONF_LOGIC_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
-       SR_CONF_LOGIC_THRESHOLD_CUSTOM | SR_CONF_GET | SR_CONF_SET,
+#endif
        SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
        SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
+       SR_CONF_CONTINUOUS | SR_CONF_GET | SR_CONF_SET,
+};
+
+static const uint32_t devopts_cg_logic[] = {
+#if !WITH_THRESHOLD_DEVCFG
+       SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+#endif
+};
+
+static const uint32_t devopts_cg_pwm[] = {
+       SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
+       SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET | SR_CONF_SET,
+       SR_CONF_DUTY_CYCLE | SR_CONF_GET | SR_CONF_SET,
 };
 
 static const int32_t trigger_matches[] = {
@@ -59,12 +75,35 @@ static const int32_t trigger_matches[] = {
        SR_TRIGGER_FALLING,
 };
 
-static const char *channel_names[] = {
-       "0", "1", "2", "3", "4", "5", "6", "7",
-       "8", "9", "10", "11", "12", "13", "14", "15",
+static const char *channel_names_logic[] = {
+       "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7",
+       "CH8", "CH9", "CH10", "CH11", "CH12", "CH13", "CH14", "CH15",
+       "CH16", "CH17", "CH18", "CH19", "CH20", "CH21", "CH22", "CH23",
+       "CH24", "CH25", "CH26", "CH27", "CH28", "CH29", "CH30", "CH31",
+};
+
+static const char *channel_names_pwm[] = {
+       "PWM1", "PWM2",
 };
 
-static const uint64_t samplerates_la2016[] = {
+/*
+ * The devices have an upper samplerate limit of 100/200/500 MHz each.
+ * But their hardware uses different base clocks (100/200/800MHz, this
+ * is _not_ a typo) and a 16bit divider. Which results in per-model ranges
+ * of supported rates which not only differ in the upper boundary, but
+ * also at the lower boundary. It's assumed that the 10kHz rate is not
+ * useful enough to provide by all means. Starting at 20kHz for all models
+ * simplfies the implementation of the config API routines, and eliminates
+ * redundancy in these samplerates tables.
+ *
+ * Streaming mode is constrained by the channel count and samplerate
+ * product (the bits per second which need to travel the USB connection
+ * while the acquisition is executing). Because streaming mode does not
+ * compress the capture data, a later implementation may desire a finer
+ * resolution. For now let's just stick with the 1/2/5 steps.
+ */
+
+static const uint64_t rates_500mhz[] = {
        SR_KHZ(20),
        SR_KHZ(50),
        SR_KHZ(100),
@@ -72,17 +111,16 @@ static const uint64_t samplerates_la2016[] = {
        SR_KHZ(500),
        SR_MHZ(1),
        SR_MHZ(2),
-       SR_MHZ(4),
        SR_MHZ(5),
-       SR_MHZ(8),
        SR_MHZ(10),
        SR_MHZ(20),
        SR_MHZ(50),
        SR_MHZ(100),
        SR_MHZ(200),
+       SR_MHZ(500),
 };
 
-static const uint64_t samplerates_la1016[] = {
+static const uint64_t rates_200mhz[] = {
        SR_KHZ(20),
        SR_KHZ(50),
        SR_KHZ(100),
@@ -90,63 +128,319 @@ static const uint64_t samplerates_la1016[] = {
        SR_KHZ(500),
        SR_MHZ(1),
        SR_MHZ(2),
-       SR_MHZ(4),
        SR_MHZ(5),
-       SR_MHZ(8),
        SR_MHZ(10),
        SR_MHZ(20),
        SR_MHZ(50),
        SR_MHZ(100),
+       SR_MHZ(200),
 };
 
-static const float logic_threshold_value[] = {
-       1.58,
-       2.5,
-       1.165,
-       1.5,
-       1.25,
-       0.9,
-       0.75,
-       0.60,
-       0.45,
+static const uint64_t rates_100mhz[] = {
+       SR_KHZ(20),
+       SR_KHZ(50),
+       SR_KHZ(100),
+       SR_KHZ(200),
+       SR_KHZ(500),
+       SR_MHZ(1),
+       SR_MHZ(2),
+       SR_MHZ(5),
+       SR_MHZ(10),
+       SR_MHZ(20),
+       SR_MHZ(50),
+       SR_MHZ(100),
 };
 
-static const char *logic_threshold[] = {
-       "TTL 5V",
-       "CMOS 5V",
-       "CMOS 3.3V",
-       "CMOS 3.0V",
-       "CMOS 2.5V",
-       "CMOS 1.8V",
-       "CMOS 1.5V",
-       "CMOS 1.2V",
-       "CMOS 0.9V",
-       "USER",
+/*
+ * Only list a few discrete voltages, to form a useful set which covers
+ * most logic families. Too many choices can make some applications use
+ * a slider again. Which may lack a scale for the current value, and
+ * leave users without feedback what the currently used value might be.
+ */
+static const double threshold_ranges[][2] = {
+       { 0.4, 0.4, },
+       { 0.6, 0.6, },
+       { 0.9, 0.9, },
+       { 1.2, 1.2, },
+       { 1.4, 1.4, }, /* Default, 1.4V, index 4. */
+       { 2.0, 2.0, },
+       { 2.5, 2.5, },
+       { 4.0, 4.0, },
 };
+#define LOGIC_THRESHOLD_IDX_DFLT       4
+
+static double threshold_voltage(const struct sr_dev_inst *sdi, double *high)
+{
+       struct dev_context *devc;
+       size_t idx;
+       double voltage;
+
+       devc = sdi->priv;
+       idx = devc->threshold_voltage_idx;
+       voltage = threshold_ranges[idx][0];
+       if (high)
+               *high = threshold_ranges[idx][1];
+
+       return voltage;
+}
+
+/* Convenience. Release an allocated devc from error paths. */
+static void kingst_la2016_free_devc(struct dev_context *devc)
+{
+       if (!devc)
+               return;
+       g_free(devc->mcu_firmware);
+       g_free(devc->fpga_bitstream);
+       g_free(devc);
+}
+
+/* Convenience. Release an allocated sdi from error paths. */
+static void kingst_la2016_free_sdi(struct sr_dev_inst *sdi)
+{
+       if (!sdi)
+               return;
+       g_free(sdi->vendor);
+       g_free(sdi->model);
+       g_free(sdi->version);
+       g_free(sdi->serial_num);
+       g_free(sdi->connection_id);
+       sr_usb_dev_inst_free(sdi->conn);
+       kingst_la2016_free_devc(sdi->priv);
+}
+
+/* Convenience. Open a USB device (including claiming an interface). */
+static int la2016_open_usb(struct sr_usb_dev_inst *usb,
+       libusb_device *dev, gboolean show_message)
+{
+       int ret;
+
+       ret = libusb_open(dev, &usb->devhdl);
+       if (ret != 0) {
+               if (show_message) {
+                       sr_err("Cannot open device: %s.",
+                               libusb_error_name(ret));
+               }
+               return SR_ERR_IO;
+       }
+
+       if (usb->address == 0xff) {
+               /*
+                * First encounter after firmware upload.
+                * Grab current address after enumeration.
+                */
+               usb->address = libusb_get_device_address(dev);
+       }
+
+       ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE);
+       if (ret == LIBUSB_ERROR_BUSY) {
+               sr_err("Cannot claim USB interface. Another program or driver using it?");
+               return SR_ERR_IO;
+       } else if (ret == LIBUSB_ERROR_NO_DEVICE) {
+               sr_err("Device has been disconnected.");
+               return SR_ERR_IO;
+       } else if (ret != 0) {
+               sr_err("Cannot claim USB interface: %s.",
+                       libusb_error_name(ret));
+               return SR_ERR_IO;
+       }
+
+       return SR_OK;
+}
 
-#define MAX_NUM_LOGIC_THRESHOLD_ENTRIES ARRAY_SIZE(logic_threshold)
+/* Convenience. Close an opened USB device (and release the interface). */
+static void la2016_close_usb(struct sr_usb_dev_inst *usb)
+{
+
+       if (!usb)
+               return;
+
+       if (usb->devhdl) {
+               libusb_release_interface(usb->devhdl, USB_INTERFACE);
+               libusb_close(usb->devhdl);
+               usb->devhdl = NULL;
+       }
+}
+
+/* Communicate to an USB device to identify the Kingst LA model. */
+static int la2016_identify_read(struct sr_dev_inst *sdi,
+       struct sr_usb_dev_inst *usb, libusb_device *dev,
+       gboolean show_message)
+{
+       int ret;
+
+       ret = la2016_open_usb(usb, dev, show_message);
+       if (ret != SR_OK) {
+               if (show_message)
+                       sr_err("Cannot communicate to MCU firmware.");
+               return ret;
+       }
+
+       /*
+        * Also complete the hardware configuration (FPGA bitstream)
+        * when MCU firmware communication became operational. Either
+        * failure is considered fatal when probing for the device.
+        */
+       ret = la2016_identify_device(sdi, show_message);
+       if (ret == SR_OK) {
+               ret = la2016_init_hardware(sdi);
+       }
+
+       la2016_close_usb(usb);
+
+       return ret;
+}
+
+/* Find given conn_id in another USB enum. Identify Kingst LA model. */
+static int la2016_identify_enum(struct sr_dev_inst *sdi)
+{
+       struct sr_dev_driver *di;
+       struct drv_context *drvc;
+       struct sr_context *ctx;
+       libusb_device **devlist, *dev;
+       struct libusb_device_descriptor des;
+       int ret, id_ret;
+       size_t device_count, dev_idx;
+       char conn_id[64];
+
+       di = sdi->driver;
+       drvc = di->context;
+       ctx = drvc->sr_ctx;;
+
+       ret = libusb_get_device_list(ctx->libusb_ctx, &devlist);
+       if (ret < 0)
+               return SR_ERR_IO;
+       device_count = ret;
+       if (!device_count)
+               return SR_ERR_IO;
+       id_ret = SR_ERR_IO;
+       for (dev_idx = 0; dev_idx < device_count; dev_idx++) {
+               dev = devlist[dev_idx];
+               libusb_get_device_descriptor(dev, &des);
+               if (des.idVendor != LA2016_VID || des.idProduct != LA2016_PID)
+                       continue;
+               if (des.iProduct != LA2016_IPRODUCT_INDEX)
+                       continue;
+               ret = usb_get_port_path(dev, conn_id, sizeof(conn_id));
+               if (ret < 0)
+                       continue;
+               if (strcmp(sdi->connection_id, conn_id) != 0)
+                       continue;
+               id_ret = la2016_identify_read(sdi, sdi->conn, dev, FALSE);
+               break;
+       }
+       libusb_free_device_list(devlist, 1);
+
+       return id_ret;
+}
+
+/* Wait for a device to re-appear after firmware upload. */
+static int la2016_identify_wait(struct sr_dev_inst *sdi)
+{
+       struct dev_context *devc;
+       uint64_t reset_done, now, elapsed_ms;
+       int ret;
+
+       devc = sdi->priv;
+
+       sr_info("Waiting for device to reset after firmware upload.");
+       now = g_get_monotonic_time();
+       reset_done = devc->fw_uploaded + RENUM_GONE_DELAY_MS * 1000;
+       if (now < reset_done)
+               g_usleep(reset_done - now);
+       do {
+               now = g_get_monotonic_time();
+               elapsed_ms = (now - devc->fw_uploaded) / 1000;
+               sr_spew("Waited %" PRIu64 "ms.", elapsed_ms);
+               ret = la2016_identify_enum(sdi);
+               if (ret == SR_OK) {
+                       devc->fw_uploaded = 0;
+                       break;
+               }
+               g_usleep(RENUM_POLL_INTERVAL_MS * 1000);
+       } while (elapsed_ms < RENUM_CHECK_PERIOD_MS);
+       if (ret != SR_OK) {
+               sr_err("Device failed to re-enumerate.");
+               return ret;
+       }
+       sr_info("Device came back after %" PRIi64 "ms.", elapsed_ms);
+
+       return SR_OK;
+}
+
+/*
+ * Open given conn_id from another USB enum. Used by dev_open(). Similar
+ * to, and should be kept in sync with la2016_identify_enum().
+ */
+static int la2016_open_enum(struct sr_dev_inst *sdi)
+{
+       struct sr_dev_driver *di;
+       struct drv_context *drvc;
+       struct sr_context *ctx;
+       libusb_device **devlist, *dev;
+       struct libusb_device_descriptor des;
+       int ret, open_ret;
+       size_t device_count, dev_idx;
+       char conn_id[64];
+
+       di = sdi->driver;
+       drvc = di->context;
+       ctx = drvc->sr_ctx;;
+
+       ret = libusb_get_device_list(ctx->libusb_ctx, &devlist);
+       if (ret < 0)
+               return SR_ERR_IO;
+       device_count = ret;
+       if (!device_count)
+               return SR_ERR_IO;
+       open_ret = SR_ERR_IO;
+       for (dev_idx = 0; dev_idx < device_count; dev_idx++) {
+               dev = devlist[dev_idx];
+               libusb_get_device_descriptor(dev, &des);
+               if (des.idVendor != LA2016_VID || des.idProduct != LA2016_PID)
+                       continue;
+               if (des.iProduct != LA2016_IPRODUCT_INDEX)
+                       continue;
+               ret = usb_get_port_path(dev, conn_id, sizeof(conn_id));
+               if (ret < 0)
+                       continue;
+               if (strcmp(sdi->connection_id, conn_id) != 0)
+                       continue;
+               open_ret = la2016_open_usb(sdi->conn, dev, TRUE);
+               break;
+       }
+       libusb_free_device_list(devlist, 1);
+
+       return open_ret;
+}
 
 static GSList *scan(struct sr_dev_driver *di, GSList *options)
 {
        struct drv_context *drvc;
+       struct sr_context *ctx;
        struct dev_context *devc;
        struct sr_dev_inst *sdi;
        struct sr_usb_dev_inst *usb;
        struct sr_config *src;
        GSList *l;
-       GSList *devices;
+       GSList *devices, *found_devices, *renum_devices;
        GSList *conn_devices;
        struct libusb_device_descriptor des;
-       libusb_device **devlist;
-       unsigned int i, j;
+       libusb_device **devlist, *dev;
+       size_t dev_count, dev_idx, ch_idx;
+       uint8_t bus, addr;
+       uint16_t pid;
        const char *conn;
-       char connection_id[64];
-       int64_t fw_updated;
-       unsigned int dev_addr;
+       char conn_id[64];
+       int ret;
+       size_t ch_off, ch_max;
+       struct sr_channel *ch;
+       struct sr_channel_group *cg;
 
        drvc = di->context;
+       ctx = drvc->sr_ctx;;
 
        conn = NULL;
+       conn_devices = NULL;
        for (l = options; l; l = l->next) {
                src = l->data;
                switch (src->key) {
@@ -156,225 +450,225 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
                }
        }
        if (conn)
-               conn_devices = sr_usb_find(drvc->sr_ctx->libusb_ctx, conn);
-       else
-               conn_devices = NULL;
+               conn_devices = sr_usb_find(ctx->libusb_ctx, conn);
+       if (conn && !conn_devices) {
+               sr_err("Cannot find the specified connection '%s'.", conn);
+               return NULL;
+       }
 
-       /* Find all LA2016 devices and upload firmware to them. */
+       /*
+        * Find all LA2016 devices, optionally upload firmware to them.
+        * Defer completion of sdi/devc creation until all (selected)
+        * devices were found in a usable state, and their models got
+        * identified which affect their feature set. It appears that
+        * we cannot communicate to the device within the same USB enum
+        * cycle, needs another USB enumeration after firmware upload.
+        */
        devices = NULL;
-       libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist);
-       for (i = 0; devlist[i]; i++) {
-               if (conn) {
-                       usb = NULL;
-                       for (l = conn_devices; l; l = l->next) {
-                               usb = l->data;
-                               if (usb->bus == libusb_get_bus_number(devlist[i]) &&
-                                   usb->address == libusb_get_device_address(devlist[i]))
-                                       break;
-                       }
-                       if (!l) {
-                               /* This device matched none of the ones that
-                                * matched the conn specification. */
-                               continue;
-                       }
+       found_devices = NULL;
+       renum_devices = NULL;
+       ret = libusb_get_device_list(ctx->libusb_ctx, &devlist);
+       if (ret < 0) {
+               sr_err("Cannot get device list: %s.", libusb_error_name(ret));
+               return devices;
+       }
+       dev_count = ret;
+       for (dev_idx = 0; dev_idx < dev_count; dev_idx++) {
+               dev = devlist[dev_idx];
+               bus = libusb_get_bus_number(dev);
+               addr = libusb_get_device_address(dev);
+
+               /* Filter by connection when externally specified. */
+               for (l = conn_devices; l; l = l->next) {
+                       usb = l->data;
+                       if (usb->bus == bus && usb->address == addr)
+                               break;
                }
-
-               libusb_get_device_descriptor(devlist[i], &des);
-
-               if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
+               if (conn_devices && !l) {
+                       sr_spew("Bus %hhu, addr %hhu do not match specified filter.",
+                               bus, addr);
                        continue;
+               }
 
+               /* Check USB VID:PID. Get the connection string. */
+               libusb_get_device_descriptor(dev, &des);
                if (des.idVendor != LA2016_VID || des.idProduct != LA2016_PID)
                        continue;
+               pid = des.idProduct;
+               ret = usb_get_port_path(dev, conn_id, sizeof(conn_id));
+               if (ret < 0)
+                       continue;
+               sr_dbg("USB enum found %04x:%04x at path %s, %d.%d.",
+                       des.idVendor, des.idProduct, conn_id, bus, addr);
+               usb = sr_usb_dev_inst_new(bus, addr, NULL);
 
-               /* Already has the firmware */
-               sr_dbg("Found a LA2016 device.");
-               sdi = g_malloc0(sizeof(struct sr_dev_inst));
+               sdi = g_malloc0(sizeof(*sdi));
+               sdi->driver = di;
                sdi->status = SR_ST_INITIALIZING;
-               sdi->connection_id = g_strdup(connection_id);
+               sdi->inst_type = SR_INST_USB;
+               sdi->connection_id = g_strdup(conn_id);
+               sdi->conn = usb;
 
-               fw_updated = 0;
-               dev_addr = libusb_get_device_address(devlist[i]);
-               if (des.iProduct != 2) {
-                       sr_info("device at '%s' has no firmware loaded!", connection_id);
+               devc = g_malloc0(sizeof(*devc));
+               sdi->priv = devc;
 
-                       if (la2016_upload_firmware(drvc->sr_ctx, devlist[i], des.idProduct) != SR_OK) {
-                               sr_err("uC firmware upload failed!");
-                               g_free(sdi->connection_id);
-                               g_free(sdi);
+               /*
+                * Load MCU firmware if it is currently missing. Which
+                * makes the device disappear and renumerate in USB.
+                * We need to come back another time to communicate to
+                * this device.
+                */
+               devc->fw_uploaded = 0;
+               devc->usb_pid = pid;
+               if (des.iProduct != LA2016_IPRODUCT_INDEX) {
+                       sr_info("Uploading MCU firmware to '%s'.", conn_id);
+                       ret = la2016_upload_firmware(sdi, ctx, dev, FALSE);
+                       if (ret != SR_OK) {
+                               sr_err("MCU firmware upload failed.");
+                               kingst_la2016_free_sdi(sdi);
+                               continue;
+                       }
+                       devc->fw_uploaded = g_get_monotonic_time();
+                       usb->address = 0xff;
+                       renum_devices = g_slist_append(renum_devices, sdi);
+                       continue;
+               } else {
+                       ret = la2016_upload_firmware(sdi, NULL, NULL, TRUE);
+                       if (ret != SR_OK) {
+                               sr_err("MCU firmware filename check failed.");
+                               kingst_la2016_free_sdi(sdi);
                                continue;
                        }
-                       fw_updated = g_get_monotonic_time();
-                       dev_addr = 0xff; /* to mark that we don't know address yet... ugly */
                }
 
-               sdi->vendor = g_strdup("Kingst");
-               sdi->model = g_strdup("LA2016");
-
-               for (j = 0; j < ARRAY_SIZE(channel_names); j++)
-                       sr_channel_new(sdi, j, SR_CHANNEL_LOGIC, TRUE, channel_names[j]);
-
-               devices = g_slist_append(devices, sdi);
-
-               devc = g_malloc0(sizeof(struct dev_context));
-               sdi->priv = devc;
-               devc->fw_updated = fw_updated;
-               devc->threshold_voltage_idx = 0;
-               devc->threshold_voltage = logic_threshold_value[devc->threshold_voltage_idx];
-
-               sdi->status = SR_ST_INACTIVE;
-               sdi->inst_type = SR_INST_USB;
-
-               sdi->conn = sr_usb_dev_inst_new(
-                       libusb_get_bus_number(devlist[i]),
-                       dev_addr, NULL);
+               /*
+                * Communicate to the MCU firmware to access EEPROM data
+                * which lets us identify the device type. Then stop, to
+                * share remaining sdi/devc creation with those devices
+                * which had their MCU firmware uploaded above and which
+                * get revisited later.
+                */
+               ret = la2016_identify_read(sdi, usb, dev, TRUE);
+               if (ret != SR_OK || !devc->model) {
+                       sr_err("Unknown or unsupported device type.");
+                       kingst_la2016_free_sdi(sdi);
+                       continue;
+               }
+               found_devices = g_slist_append(found_devices, sdi);
        }
        libusb_free_device_list(devlist, 1);
-       g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
+       g_slist_free_full(conn_devices, sr_usb_dev_inst_free_cb);
 
-       return std_scan_complete(di, devices);
-}
-
-static int la2016_dev_open(struct sr_dev_inst *sdi)
-{
-       struct sr_dev_driver *di;
-       libusb_device **devlist;
-       struct sr_usb_dev_inst *usb;
-       struct libusb_device_descriptor des;
-       struct drv_context *drvc;
-       int ret, i, device_count;
-       char connection_id[64];
-
-       di = sdi->driver;
-       drvc = di->context;
-       usb = sdi->conn;
-       ret = SR_ERR;
-
-       device_count = libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist);
-       if (device_count < 0) {
-               sr_err("Failed to get device list: %s.", libusb_error_name(device_count));
-               return SR_ERR;
-       }
-
-       for (i = 0; i < device_count; i++) {
-               libusb_get_device_descriptor(devlist[i], &des);
-
-               if (des.idVendor != LA2016_VID || des.idProduct != LA2016_PID || des.iProduct != 2)
+       /*
+        * Wait for devices to re-appear after firmware upload. Append
+        * the yet unidentified device to the list of found devices, or
+        * release the previously allocated sdi/devc.
+        */
+       for (l = renum_devices; l; l = l->next) {
+               sdi = l->data;
+               devc = sdi->priv;
+               ret = la2016_identify_wait(sdi);
+               if (ret != SR_OK || !devc->model) {
+                       sr_dbg("Skipping unusable '%s'.", sdi->connection_id);
+                       kingst_la2016_free_sdi(sdi);
                        continue;
+               }
+               found_devices = g_slist_append(found_devices, sdi);
+       }
+       g_slist_free(renum_devices);
 
-               if ((sdi->status == SR_ST_INITIALIZING) || (sdi->status == SR_ST_INACTIVE)) {
-                       /*
-                        * Check device by its physical USB bus/port address.
-                        */
-                       if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
-                               continue;
+       /*
+        * All found devices got identified, their type is known here.
+        * Complete the sdi/devc creation. Assign default settings
+        * because the vendor firmware would not let us read back the
+        * previously written configuration.
+        */
+       for (l = found_devices; l; l = l->next) {
+               sdi = l->data;
+               devc = sdi->priv;
 
-                       if (strcmp(sdi->connection_id, connection_id))
-                               /* This is not the one. */
-                               continue;
+               sdi->vendor = g_strdup("Kingst");
+               sdi->model = g_strdup(devc->model->name);
+               ch_off = 0;
+
+               /* Create the "Logic" channel group. */
+               ch_max = ARRAY_SIZE(channel_names_logic);
+               if (ch_max > devc->model->channel_count)
+                       ch_max = devc->model->channel_count;
+               cg = sr_channel_group_new(sdi, "Logic", NULL);
+               devc->cg_logic = cg;
+               for (ch_idx = 0; ch_idx < ch_max; ch_idx++) {
+                       ch = sr_channel_new(sdi, ch_off,
+                               SR_CHANNEL_LOGIC, TRUE,
+                               channel_names_logic[ch_idx]);
+                       ch_off++;
+                       cg->channels = g_slist_append(cg->channels, ch);
                }
 
-               if (!(ret = libusb_open(devlist[i], &usb->devhdl))) {
-                       if (usb->address == 0xff)
-                               /*
-                                * First time we touch this device after FW
-                                * upload, so we don't know the address yet.
-                                */
-                               usb->address = libusb_get_device_address(devlist[i]);
-               } else {
-                       sr_err("Failed to open device: %s.", libusb_error_name(ret));
-                       ret = SR_ERR;
-                       break;
+               /* Create the "PWMx" channel groups. */
+               ch_max = ARRAY_SIZE(channel_names_pwm);
+               for (ch_idx = 0; ch_idx < ch_max; ch_idx++) {
+                       const char *name;
+                       name = channel_names_pwm[ch_idx];
+                       cg = sr_channel_group_new(sdi, name, NULL);
+                       if (!devc->cg_pwm)
+                               devc->cg_pwm = cg;
+                       ch = sr_channel_new(sdi, ch_off,
+                               SR_CHANNEL_ANALOG, FALSE, name);
+                       ch_off++;
+                       cg->channels = g_slist_append(cg->channels, ch);
                }
 
-               ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE);
-               if (ret == LIBUSB_ERROR_BUSY) {
-                       sr_err("Unable to claim USB interface. Another "
-                              "program or driver has already claimed it.");
-                       ret = SR_ERR;
-                       break;
-               } else if (ret == LIBUSB_ERROR_NO_DEVICE) {
-                       sr_err("Device has been disconnected.");
-                       ret = SR_ERR;
-                       break;
-               } else if (ret != 0) {
-                       sr_err("Unable to claim interface: %s.", libusb_error_name(ret));
-                       ret = SR_ERR;
-                       break;
+               /*
+                * Ideally we'd get the previous configuration from the
+                * hardware, but this device is write-only. So we have
+                * to assign a fixed set of initial configuration values.
+                */
+               sr_sw_limits_init(&devc->sw_limits);
+               devc->sw_limits.limit_samples = 0;
+               devc->capture_ratio = 50;
+               devc->samplerate = devc->model->samplerate;
+               if (!devc->model->memory_bits)
+                       devc->continuous = TRUE;
+               devc->threshold_voltage_idx = LOGIC_THRESHOLD_IDX_DFLT;
+               if  (ARRAY_SIZE(devc->pwm_setting) >= 1) {
+                       devc->pwm_setting[0].enabled = FALSE;
+                       devc->pwm_setting[0].freq = SR_KHZ(1);
+                       devc->pwm_setting[0].duty = 50;
                }
-
-               if ((ret = la2016_init_device(sdi)) != SR_OK) {
-                       sr_err("Failed to init device.");
-                       break;
+               if  (ARRAY_SIZE(devc->pwm_setting) >= 2) {
+                       devc->pwm_setting[1].enabled = FALSE;
+                       devc->pwm_setting[1].freq = SR_KHZ(100);
+                       devc->pwm_setting[1].duty = 50;
                }
 
-               sr_info("Opened device on %d.%d (logical) / %s (physical), interface %d.",
-                       usb->bus, usb->address, sdi->connection_id, USB_INTERFACE);
-
-               ret = SR_OK;
-
-               break;
-       }
-
-       libusb_free_device_list(devlist, 1);
-
-       if (ret != SR_OK) {
-               if (usb->devhdl) {
-                       libusb_release_interface(usb->devhdl, USB_INTERFACE);
-                       libusb_close(usb->devhdl);
-                       usb->devhdl = NULL;
-               }
-               return SR_ERR;
+               sdi->status = SR_ST_INACTIVE;
+               devices = g_slist_append(devices, sdi);
        }
+       g_slist_free(found_devices);
 
-       return SR_OK;
+       return std_scan_complete(di, devices);
 }
 
 static int dev_open(struct sr_dev_inst *sdi)
 {
        struct dev_context *devc;
-       int64_t timediff_us, timediff_ms;
-       uint64_t reset_done;
-       uint64_t now;
        int ret;
+       size_t ch;
 
        devc = sdi->priv;
 
-       /*
-        * If the firmware was recently uploaded, wait up to MAX_RENUM_DELAY_MS
-        * milliseconds for the FX2 to renumerate.
-        */
-       ret = SR_ERR;
-       if (devc->fw_updated > 0) {
-               sr_info("Waiting for device to reset after firmware upload.");
-               /* Takes >= 2000ms for the uC to be gone from the USB bus. */
-               reset_done = devc->fw_updated + 18 * (uint64_t)1e5; /* 1.8 seconds */
-               now = g_get_monotonic_time();
-               if (reset_done > now)
-                       g_usleep(reset_done - now);
-               timediff_ms = 0;
-               while (timediff_ms < MAX_RENUM_DELAY_MS) {
-                       g_usleep(200 * 1000);
-
-                       timediff_us = g_get_monotonic_time() - devc->fw_updated;
-                       timediff_ms = timediff_us / 1000;
-
-                       if ((ret = la2016_dev_open(sdi)) == SR_OK)
-                               break;
-                       sr_spew("Waited %" PRIi64 "ms.", timediff_ms);
-               }
-               if (ret != SR_OK) {
-                       sr_err("Device failed to re-enumerate.");
-                       return SR_ERR;
-               }
-               sr_info("Device came back after %" PRIi64 "ms.", timediff_ms);
-       } else {
-               ret = la2016_dev_open(sdi);
+       ret = la2016_open_enum(sdi);
+       if (ret != SR_OK) {
+               sr_err("Cannot open device.");
+               return ret;
        }
 
-       if (ret != SR_OK) {
-               sr_err("Unable to open device.");
-               return SR_ERR;
+       /* Send most recent PWM configuration to the device. */
+       for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) {
+               ret = la2016_write_pwm_config(sdi, ch);
+               if (ret != SR_OK)
+                       return ret;
        }
 
        return SR_OK;
@@ -389,62 +683,151 @@ static int dev_close(struct sr_dev_inst *sdi)
        if (!usb->devhdl)
                return SR_ERR_BUG;
 
-       la2016_deinit_device(sdi);
+       la2016_release_resources(sdi);
+
+       if (WITH_DEINIT_IN_CLOSE)
+               la2016_deinit_hardware(sdi);
 
        sr_info("Closing device on %d.%d (logical) / %s (physical) interface %d.",
                usb->bus, usb->address, sdi->connection_id, USB_INTERFACE);
-       libusb_release_interface(usb->devhdl, USB_INTERFACE);
-       libusb_close(usb->devhdl);
-       usb->devhdl = NULL;
+       la2016_close_usb(sdi->conn);
 
        return SR_OK;
 }
 
+/* Config API helper. Get type and index of a channel group. */
+static int get_cg_index(const struct sr_dev_inst *sdi,
+       const struct sr_channel_group *cg,
+       int *type, size_t *logic, size_t *analog)
+{
+       struct dev_context *devc;
+       GSList *l;
+       size_t idx;
+
+       /* Preset return values. */
+       if (type)
+               *type = 0;
+       if (logic)
+               *logic = 0;
+       if (analog)
+               *analog = 0;
+
+       /* Start categorizing the received cg. */
+       if (!sdi)
+               return SR_ERR_ARG;
+       devc = sdi->priv;
+       if (!cg)
+               return SR_OK;
+       l = sdi->channel_groups;
+
+       /* First sdi->channelgroups item is "Logic". */
+       if (!l)
+               return SR_ERR_BUG;
+       if (cg == l->data) {
+               if (type)
+                       *type = SR_CHANNEL_LOGIC;
+               if (logic)
+                       *logic = 0;
+               return SR_OK;
+       }
+       l = l->next;
+
+       /* Next sdi->channelgroups items are "PWMx". */
+       idx = 0;
+       while (l && l->data != cg) {
+               idx++;
+               l = l->next;
+       }
+       if (l && idx < ARRAY_SIZE(devc->pwm_setting)) {
+               if (type)
+                       *type = SR_CHANNEL_ANALOG;
+               if (analog)
+                       *analog = idx;
+               return SR_OK;
+       }
+
+       return SR_ERR_ARG;
+}
+
 static int config_get(uint32_t key, GVariant **data,
        const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
 {
        struct dev_context *devc;
+       int ret, cg_type;
+       size_t logic_idx, analog_idx;
+       struct pwm_setting *pwm;
        struct sr_usb_dev_inst *usb;
-       double rounded;
+       double voltage, rounded;
 
-       (void)cg;
+       (void)rounded;
+       (void)voltage;
 
        if (!sdi)
                return SR_ERR_ARG;
        devc = sdi->priv;
 
+       /* Check for types (and index) of channel groups. */
+       ret = get_cg_index(sdi, cg, &cg_type, &logic_idx, &analog_idx);
+       if (cg && ret != SR_OK)
+               return SR_ERR_ARG;
+
+       /* Handle requests for the "Logic" channel group. */
+       if (cg && cg_type == SR_CHANNEL_LOGIC) {
+               switch (key) {
+#if !WITH_THRESHOLD_DEVCFG
+               case SR_CONF_VOLTAGE_THRESHOLD:
+                       voltage = threshold_voltage(sdi, NULL);
+                       *data = std_gvar_tuple_double(voltage, voltage);
+                       break;
+#endif /* WITH_THRESHOLD_DEVCFG */
+               default:
+                       return SR_ERR_NA;
+               }
+               return SR_OK;
+       }
+
+       /* Handle requests for the "PWMx" channel groups. */
+       if (cg && cg_type == SR_CHANNEL_ANALOG) {
+               pwm = &devc->pwm_setting[analog_idx];
+               switch (key) {
+               case SR_CONF_ENABLED:
+                       *data = g_variant_new_boolean(pwm->enabled);
+                       break;
+               case SR_CONF_OUTPUT_FREQUENCY:
+                       *data = g_variant_new_double(pwm->freq);
+                       break;
+               case SR_CONF_DUTY_CYCLE:
+                       *data = g_variant_new_double(pwm->duty);
+                       break;
+               default:
+                       return SR_ERR_NA;
+               }
+               return SR_OK;
+       }
+
        switch (key) {
        case SR_CONF_CONN:
-               if (!sdi->conn)
-                       return SR_ERR_ARG;
                usb = sdi->conn;
-               if (usb->address == 255) {
-                       /* Device still needs to re-enumerate after firmware
-                        * upload, so we don't know its (future) address. */
-                       return SR_ERR;
-               }
                *data = g_variant_new_printf("%d.%d", usb->bus, usb->address);
                break;
        case SR_CONF_SAMPLERATE:
-               *data = g_variant_new_uint64(devc->cur_samplerate);
+               *data = g_variant_new_uint64(devc->samplerate);
                break;
        case SR_CONF_LIMIT_SAMPLES:
-               *data = g_variant_new_uint64(devc->limit_samples);
-               break;
+       case SR_CONF_LIMIT_MSEC:
+               return sr_sw_limits_config_get(&devc->sw_limits, key, data);
        case SR_CONF_CAPTURE_RATIO:
                *data = g_variant_new_uint64(devc->capture_ratio);
                break;
+#if WITH_THRESHOLD_DEVCFG
        case SR_CONF_VOLTAGE_THRESHOLD:
-               rounded = (int)(devc->threshold_voltage / 0.1) * 0.1;
-               *data = std_gvar_tuple_double(rounded, rounded + 0.1);
-               return SR_OK;
-       case SR_CONF_LOGIC_THRESHOLD:
-               *data = g_variant_new_string(logic_threshold[devc->threshold_voltage_idx]);
+               voltage = threshold_voltage(sdi, NULL);
+               *data = std_gvar_tuple_double(voltage, voltage);
                break;
-       case SR_CONF_LOGIC_THRESHOLD_CUSTOM:
-               *data = g_variant_new_double(devc->threshold_voltage);
+#endif /* WITH_THRESHOLD_DEVCFG */
+       case SR_CONF_CONTINUOUS:
+               *data = g_variant_new_boolean(devc->continuous);
                break;
-
        default:
                return SR_ERR_NA;
        }
@@ -456,41 +839,96 @@ static int config_set(uint32_t key, GVariant *data,
        const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
 {
        struct dev_context *devc;
-       double low, high;
+       int ret, cg_type;
+       size_t logic_idx, analog_idx;
+       struct pwm_setting *pwm;
+       double value_f;
        int idx;
-
-       (void)cg;
+       gboolean on;
 
        devc = sdi->priv;
 
+       /* Check for types (and index) of channel groups. */
+       ret = get_cg_index(sdi, cg, &cg_type, &logic_idx, &analog_idx);
+       if (cg && ret != SR_OK)
+               return SR_ERR_ARG;
+
+       /* Handle requests for the "Logic" channel group. */
+       if (cg && cg_type == SR_CHANNEL_LOGIC) {
+               switch (key) {
+#if !WITH_THRESHOLD_DEVCFG
+               case SR_CONF_LOGIC_THRESHOLD:
+                       idx = std_double_tuple_idx(data,
+                               ARRAY_AND_SIZE(threshold_ranges));
+                       if (idx < 0)
+                               return SR_ERR_ARG;
+                       devc->threshold_voltage_idx = idx;
+                       break;
+#endif /* WITH_THRESHOLD_DEVCFG */
+               default:
+                       return SR_ERR_NA;
+               }
+               return SR_OK;
+       }
+
+       /* Handle requests for the "PWMx" channel groups. */
+       if (cg && cg_type == SR_CHANNEL_ANALOG) {
+               pwm = &devc->pwm_setting[analog_idx];
+               switch (key) {
+               case SR_CONF_ENABLED:
+                       pwm->enabled = g_variant_get_boolean(data);
+                       ret = la2016_write_pwm_config(sdi, analog_idx);
+                       if (ret != SR_OK)
+                               return ret;
+                       break;
+               case SR_CONF_OUTPUT_FREQUENCY:
+                       value_f = g_variant_get_double(data);
+                       if (value_f <= 0.0 || value_f > MAX_PWM_FREQ)
+                               return SR_ERR_ARG;
+                       pwm->freq = value_f;
+                       ret = la2016_write_pwm_config(sdi, analog_idx);
+                       if (ret != SR_OK)
+                               return ret;
+                       break;
+               case SR_CONF_DUTY_CYCLE:
+                       value_f = g_variant_get_double(data);
+                       if (value_f <= 0.0 || value_f > 100.0)
+                               return SR_ERR_ARG;
+                       pwm->duty = value_f;
+                       ret = la2016_write_pwm_config(sdi, analog_idx);
+                       if (ret != SR_OK)
+                               return ret;
+                       break;
+               default:
+                       return SR_ERR_NA;
+               }
+               return SR_OK;
+       }
+
        switch (key) {
        case SR_CONF_SAMPLERATE:
-               devc->cur_samplerate = g_variant_get_uint64(data);
+               devc->samplerate = g_variant_get_uint64(data);
                break;
        case SR_CONF_LIMIT_SAMPLES:
-               devc->limit_samples = g_variant_get_uint64(data);
-               break;
+       case SR_CONF_LIMIT_MSEC:
+               return sr_sw_limits_config_set(&devc->sw_limits, key, data);
        case SR_CONF_CAPTURE_RATIO:
                devc->capture_ratio = g_variant_get_uint64(data);
                break;
+#if WITH_THRESHOLD_DEVCFG
        case SR_CONF_VOLTAGE_THRESHOLD:
-               g_variant_get(data, "(dd)", &low, &high);
-               devc->threshold_voltage = (low + high) / 2.0;
-               devc->threshold_voltage_idx = MAX_NUM_LOGIC_THRESHOLD_ENTRIES - 1; /* USER */
-               break;
-       case SR_CONF_LOGIC_THRESHOLD: {
-               if ((idx = std_str_idx(data, logic_threshold, MAX_NUM_LOGIC_THRESHOLD_ENTRIES)) < 0)
+               idx = std_double_tuple_idx(data,
+                       ARRAY_AND_SIZE(threshold_ranges));
+               if (idx < 0)
                        return SR_ERR_ARG;
-               if (idx == MAX_NUM_LOGIC_THRESHOLD_ENTRIES - 1) {
-                       /* user threshold */
-               } else {
-                       devc->threshold_voltage = logic_threshold_value[idx];
-               }
                devc->threshold_voltage_idx = idx;
                break;
-       }
-       case SR_CONF_LOGIC_THRESHOLD_CUSTOM:
-               devc->threshold_voltage = g_variant_get_double(data);
+#endif /* WITH_THRESHOLD_DEVCFG */
+       case SR_CONF_CONTINUOUS:
+               on = g_variant_get_boolean(data);
+               if (!devc->model->memory_bits && !on)
+                       return SR_ERR_ARG;
+               devc->continuous = on;
                break;
        default:
                return SR_ERR_NA;
@@ -503,36 +941,79 @@ static int config_list(uint32_t key, GVariant **data,
        const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
 {
        struct dev_context *devc;
+       int ret, cg_type;
+       size_t logic_idx, analog_idx;
+
+       devc = sdi ? sdi->priv : NULL;
+
+       /* Check for types (and index) of channel groups. */
+       ret = get_cg_index(sdi, cg, &cg_type, &logic_idx, &analog_idx);
+       if (cg && ret != SR_OK)
+               return SR_ERR_ARG;
+
+       /* Handle requests for the "Logic" channel group. */
+       if (cg && cg_type == SR_CHANNEL_LOGIC) {
+               switch (key) {
+               case SR_CONF_DEVICE_OPTIONS:
+                       if (ARRAY_SIZE(devopts_cg_logic) == 0)
+                               return SR_ERR_NA;
+                       *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
+                               devopts_cg_logic, ARRAY_SIZE(devopts_cg_logic),
+                               sizeof(devopts_cg_logic[0]));
+                       break;
+#if !WITH_THRESHOLD_DEVCFG
+               case SR_CONF_VOLTAGE_THRESHOLD:
+                       *data = std_gvar_thresholds(ARRAY_AND_SIZE(threshold_ranges));
+                       break;
+#endif /* WITH_THRESHOLD_DEVCFG */
+               default:
+                       return SR_ERR_NA;
+               }
+               return SR_OK;
+       }
+
+       /* Handle requests for the "PWMx" channel groups. */
+       if (cg && cg_type == SR_CHANNEL_ANALOG) {
+               switch (key) {
+               case SR_CONF_DEVICE_OPTIONS:
+                       *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
+                               devopts_cg_pwm, ARRAY_SIZE(devopts_cg_pwm),
+                               sizeof(devopts_cg_pwm[0]));
+                       break;
+               default:
+                       return SR_ERR_NA;
+               }
+               return SR_OK;
+       }
 
        switch (key) {
        case SR_CONF_SCAN_OPTIONS:
        case SR_CONF_DEVICE_OPTIONS:
-               return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
+               return STD_CONFIG_LIST(key, data, sdi, cg,
+                       scanopts, drvopts, devopts);
        case SR_CONF_SAMPLERATE:
                if (!sdi)
                        return SR_ERR_ARG;
-               devc = sdi->priv;
-               if (devc->max_samplerate == SR_MHZ(200)) {
-                       *data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates_la2016));
-               }
-               else {
-                       *data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates_la1016));
-               }
+               if (devc->model->samplerate == SR_MHZ(500))
+                       *data = std_gvar_samplerates(ARRAY_AND_SIZE(rates_500mhz));
+               else if (devc->model->samplerate == SR_MHZ(200))
+                       *data = std_gvar_samplerates(ARRAY_AND_SIZE(rates_200mhz));
+               else if (devc->model->samplerate == SR_MHZ(100))
+                       *data = std_gvar_samplerates(ARRAY_AND_SIZE(rates_100mhz));
+               else
+                       return SR_ERR_BUG;
                break;
        case SR_CONF_LIMIT_SAMPLES:
-               *data = std_gvar_tuple_u64(LA2016_NUM_SAMPLES_MIN, LA2016_NUM_SAMPLES_MAX);
+               *data = std_gvar_tuple_u64(0, LA2016_NUM_SAMPLES_MAX);
                break;
+#if WITH_THRESHOLD_DEVCFG
        case SR_CONF_VOLTAGE_THRESHOLD:
-               *data = std_gvar_min_max_step_thresholds(
-                       LA2016_THR_VOLTAGE_MIN,
-                       LA2016_THR_VOLTAGE_MAX, 0.1);
+               *data = std_gvar_thresholds(ARRAY_AND_SIZE(threshold_ranges));
                break;
+#endif /* WITH_THRESHOLD_DEVCFG */
        case SR_CONF_TRIGGER_MATCH:
                *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
                break;
-       case SR_CONF_LOGIC_THRESHOLD:
-               *data = g_variant_new_strv(logic_threshold, MAX_NUM_LOGIC_THRESHOLD_ENTRIES);
-               break;
        default:
                return SR_ERR_NA;
        }
@@ -540,247 +1021,60 @@ static int config_list(uint32_t key, GVariant **data,
        return SR_OK;
 }
 
-static void send_chunk(struct sr_dev_inst *sdi,
-       const uint8_t *packets, unsigned int num_tfers)
-{
-       struct dev_context *devc;
-       struct sr_datafeed_logic logic;
-       struct sr_datafeed_packet sr_packet;
-       unsigned int max_samples, n_samples, total_samples, free_n_samples;
-       unsigned int i, j, k;
-       int do_signal_trigger;
-       uint16_t *wp;
-       const uint8_t *rp;
-       uint16_t state;
-       uint8_t repetitions;
-
-       devc = sdi->priv;
-
-       logic.unitsize = 2;
-       logic.data = devc->convbuffer;
-
-       sr_packet.type = SR_DF_LOGIC;
-       sr_packet.payload = &logic;
-
-       max_samples = devc->convbuffer_size / 2;
-       n_samples = 0;
-       wp = (uint16_t *)devc->convbuffer;
-       total_samples = 0;
-       do_signal_trigger = 0;
-
-       if (devc->had_triggers_configured && devc->reading_behind_trigger == 0 && devc->info.n_rep_packets_before_trigger == 0) {
-               std_session_send_df_trigger(sdi);
-               devc->reading_behind_trigger = 1;
-       }
-
-       rp = packets;
-       for (i = 0; i < num_tfers; i++) {
-               for (k = 0; k < NUM_PACKETS_IN_CHUNK; k++) {
-                       free_n_samples = max_samples - n_samples;
-                       if (free_n_samples < 256 || do_signal_trigger) {
-                               logic.length = n_samples * 2;
-                               sr_session_send(sdi, &sr_packet);
-                               n_samples = 0;
-                               wp = (uint16_t *)devc->convbuffer;
-                               if (do_signal_trigger) {
-                                       std_session_send_df_trigger(sdi);
-                                       do_signal_trigger = 0;
-                               }
-                       }
-
-                       state = read_u16le_inc(&rp);
-                       repetitions = read_u8_inc(&rp);
-                       for (j = 0; j < repetitions; j++)
-                               *wp++ = state;
-
-                       n_samples += repetitions;
-                       total_samples += repetitions;
-                       devc->total_samples += repetitions;
-                       if (!devc->reading_behind_trigger) {
-                               devc->n_reps_until_trigger--;
-                               if (devc->n_reps_until_trigger == 0) {
-                                       devc->reading_behind_trigger = 1;
-                                       do_signal_trigger = 1;
-                                       sr_dbg("  here is trigger position after %" PRIu64 " samples, %.6fms",
-                                              devc->total_samples,
-                                              (double)devc->total_samples / devc->cur_samplerate * 1e3);
-                               }
-                       }
-               }
-               (void)read_u8_inc(&rp); /* Skip sequence number. */
-       }
-       if (n_samples) {
-               logic.length = n_samples * 2;
-               sr_session_send(sdi, &sr_packet);
-               if (do_signal_trigger) {
-                       std_session_send_df_trigger(sdi);
-               }
-       }
-       sr_dbg("send_chunk done after %d samples", total_samples);
-}
-
-static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer)
-{
-       struct sr_dev_inst *sdi;
-       struct dev_context *devc;
-       struct sr_usb_dev_inst *usb;
-       int ret;
-
-       sdi = transfer->user_data;
-       devc = sdi->priv;
-       usb = sdi->conn;
-
-       sr_dbg("receive_transfer(): status %s received %d bytes.",
-              libusb_error_name(transfer->status), transfer->actual_length);
-
-       if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) {
-               sr_err("bulk transfer timeout!");
-               devc->transfer_finished = 1;
-       }
-       send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH);
-
-       devc->n_bytes_to_read -= transfer->actual_length;
-       if (devc->n_bytes_to_read) {
-               uint32_t to_read = devc->n_bytes_to_read;
-               /* determine read size for the next usb transfer */
-               if (to_read >= LA2016_USB_BUFSZ)
-                       to_read = LA2016_USB_BUFSZ;
-               else /* last transfer, make read size some multiple of LA2016_EP6_PKTSZ */
-                       to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1);
-               libusb_fill_bulk_transfer(
-                       transfer, usb->devhdl,
-                       0x86, transfer->buffer, to_read,
-                       receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS);
-
-               if ((ret = libusb_submit_transfer(transfer)) == 0)
-                       return;
-               sr_err("Failed to submit further transfer: %s.", libusb_error_name(ret));
-       }
-
-       g_free(transfer->buffer);
-       libusb_free_transfer(transfer);
-       devc->transfer_finished = 1;
-}
-
-static int handle_event(int fd, int revents, void *cb_data)
-{
-       const struct sr_dev_inst *sdi;
-       struct dev_context *devc;
-       struct drv_context *drvc;
-       struct timeval tv;
-
-       (void)fd;
-       (void)revents;
-
-       sdi = cb_data;
-       devc = sdi->priv;
-       drvc = sdi->driver->context;
-
-       if (devc->have_trigger == 0) {
-               if (la2016_has_triggered(sdi) == 0) {
-                       /* not yet ready for download */
-                       return TRUE;
-               }
-               devc->have_trigger = 1;
-               devc->transfer_finished = 0;
-               devc->reading_behind_trigger = 0;
-               devc->total_samples = 0;
-               /* we can start retrieving data! */
-               if (la2016_start_retrieval(sdi, receive_transfer) != SR_OK) {
-                       sr_err("failed to start retrieval!");
-                       return FALSE;
-               }
-               sr_dbg("retrieval is started...");
-               std_session_send_df_frame_begin(sdi);
-
-               return TRUE;
-       }
-
-       tv.tv_sec = tv.tv_usec = 0;
-       libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
-
-       if (devc->transfer_finished) {
-               sr_dbg("transfer is finished!");
-               std_session_send_df_frame_end(sdi);
-
-               usb_source_remove(sdi->session, drvc->sr_ctx);
-               std_session_send_df_end(sdi);
-
-               la2016_stop_acquisition(sdi);
-
-               g_free(devc->convbuffer);
-               devc->convbuffer = NULL;
-
-               devc->transfer = NULL;
-
-               sr_dbg("transfer is now finished");
-       }
-
-       return TRUE;
-}
-
-static void abort_acquisition(struct dev_context *devc)
-{
-       if (devc->transfer)
-               libusb_cancel_transfer(devc->transfer);
-}
-
-static int configure_channels(const struct sr_dev_inst *sdi)
-{
-       struct dev_context *devc;
-
-       devc = sdi->priv;
-       devc->cur_channels = 0;
-       devc->num_channels = 0;
-
-       for (GSList *l = sdi->channels; l; l = l->next) {
-               struct sr_channel *ch = (struct sr_channel*)l->data;
-               if (ch->enabled == FALSE)
-                       continue;
-               devc->cur_channels |= 1 << ch->index;
-               devc->num_channels++;
-       }
-
-       return SR_OK;
-}
-
 static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 {
        struct sr_dev_driver *di;
        struct drv_context *drvc;
+       struct sr_context *ctx;
        struct dev_context *devc;
+       size_t unitsize;
+       double voltage;
        int ret;
 
        di = sdi->driver;
        drvc = di->context;
+       ctx = drvc->sr_ctx;;
        devc = sdi->priv;
 
-       if (configure_channels(sdi) != SR_OK) {
-               sr_err("Failed to configure channels.");
-               return SR_ERR;
+       if (!devc->feed_queue) {
+               if (devc->model->channel_count == 32)
+                       unitsize = sizeof(uint32_t);
+               else if (devc->model->channel_count == 16)
+                       unitsize = sizeof(uint16_t);
+               else
+                       return SR_ERR_ARG;
+               devc->feed_queue = feed_queue_logic_alloc(sdi,
+                       LA2016_CONVBUFFER_SIZE, unitsize);
+               if (!devc->feed_queue) {
+                       sr_err("Cannot allocate buffer for session feed.");
+                       return SR_ERR_MALLOC;
+               }
+               devc->packets_per_chunk = TRANSFER_PACKET_LENGTH;
+               devc->packets_per_chunk--;
+               devc->packets_per_chunk /= unitsize + sizeof(uint8_t);
        }
 
-       devc->convbuffer_size = 4 * 1024 * 1024;
-       if (!(devc->convbuffer = g_try_malloc(devc->convbuffer_size))) {
-               sr_err("Conversion buffer malloc failed.");
-               return SR_ERR_MALLOC;
-       }
+       sr_sw_limits_acquisition_start(&devc->sw_limits);
 
-       if ((ret = la2016_setup_acquisition(sdi)) != SR_OK) {
-               g_free(devc->convbuffer);
-               devc->convbuffer = NULL;
+       voltage = threshold_voltage(sdi, NULL);
+       ret = la2016_setup_acquisition(sdi, voltage);
+       if (ret != SR_OK) {
+               feed_queue_logic_free(devc->feed_queue);
+               devc->feed_queue = NULL;
                return ret;
        }
 
-       devc->ctx = drvc->sr_ctx;
-
-       if ((ret = la2016_start_acquisition(sdi)) != SR_OK) {
-               abort_acquisition(devc);
+       ret = la2016_start_acquisition(sdi);
+       if (ret != SR_OK) {
+               la2016_abort_acquisition(sdi);
+               feed_queue_logic_free(devc->feed_queue);
+               devc->feed_queue = NULL;
                return ret;
        }
 
-       devc->have_trigger = 0;
-       usb_source_add(sdi->session, drvc->sr_ctx, 50, handle_event, (void *)sdi);
+       devc->completion_seen = FALSE;
+       usb_source_add(sdi->session, ctx, 50,
+               la2016_receive_data, (void *)sdi);
 
        std_session_send_df_header(sdi);
 
@@ -792,7 +1086,6 @@ static int dev_acquisition_stop(struct sr_dev_inst *sdi)
        int ret;
 
        ret = la2016_abort_acquisition(sdi);
-       abort_acquisition(sdi->priv);
 
        return ret;
 }
index ecb21e3faa7af4c34eabccc3a6f85edf576f6a62..fdc447285e926e3f828a3c2140e2eda3bc2432aa 100644 (file)
@@ -1,6 +1,7 @@
 /*
  * This file is part of the libsigrok project.
  *
+ * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net>
  * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
  * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
  */
 
 #include <config.h>
-#include <stdint.h>
-#include <string.h>
-#include <glib.h>
-#include <glib/gstdio.h>
-#include <stdio.h>
-#include <errno.h>
-#include <math.h>
-#include <inttypes.h>
+
 #include <libsigrok/libsigrok.h>
+#include <string.h>
+
 #include "libsigrok-internal.h"
 #include "protocol.h"
 
-#define UC_FIRMWARE    "kingst-la-%04x.fw"
-#define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream"
-#define FPGA_FW_LA2016A        "kingst-la2016a1-fpga.bitstream"
-#define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream"
-#define FPGA_FW_LA1016A        "kingst-la1016a1-fpga.bitstream"
+/* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */
+#define MCU_FWFILE_FMT "kingst-la-%04x.fw"
+#define FPGA_FWFILE_FMT        "kingst-%s-fpga.bitstream"
 
-#define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200)
-#define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100)
-#define MAX_SAMPLE_DEPTH 10e9
-#define MAX_PWM_FREQ     SR_MHZ(20)
-#define PWM_CLOCK        SR_MHZ(200)   /* this is 200MHz for both the LA2016 and LA1016 */
-
-/* usb vendor class control requests to the cypress FX2 microcontroller */
+/*
+ * List of known devices and their features. See @ref kingst_model
+ * for the fields' type and meaning. Table is sorted by EEPROM magic.
+ * More specific items need to go first (additional byte[2/6]). Not
+ * all devices are covered by this driver implementation, but telling
+ * users what was detected is considered useful.
+ *
+ * TODO Verify the identification of models that were not tested before.
+ */
+static const struct kingst_model models[] = {
+       {  2, 1, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
+       {  2, 0, "LA2016", "la2016",   SR_MHZ(200), 16, 1, 0, },
+       {  3, 1, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
+       {  3, 0, "LA1016", "la1016",   SR_MHZ(100), 16, 1, 0, },
+       {  4, 0, "LA1010", "la1010a0", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+       {  5, 0, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), },
+       {  6, 0, "LA5032", "la5032a0", SR_MHZ(500), 32, 4, SR_MHZ(800), },
+       {  7, 0, "LA1010", "la1010a1", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+       {  8, 0, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
+       {  9, 0, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
+       { 10, 0, "LA1010", "la1010a2", SR_MHZ(100), 16, 0, SR_MHZ(800), },
+       { 65, 0, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), },
+};
+
+/* USB vendor class control requests, executed by the Cypress FX2 MCU. */
 #define CMD_FPGA_ENABLE        0x10
-#define CMD_FPGA_SPI   0x20    /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */
-#define CMD_BULK_START 0x30    /* begin transfer of capture data via usb endpoint 6 IN */
-#define CMD_BULK_RESET 0x38    /* flush FX2 usb endpoint 6 IN fifos */
-#define CMD_FPGA_INIT  0x50    /* used before and after FPGA bitstream loading */
-#define CMD_KAUTH      0x60    /* communicate with authentication ic U10, not used */
-#define CMD_EEPROM     0xa2    /* ctrl_in reads, ctrl_out writes */
+#define CMD_FPGA_SPI   0x20    /* R/W access to FPGA registers via SPI. */
+#define CMD_BULK_START 0x30    /* Start sample data download via USB EP6 IN. */
+#define CMD_BULK_RESET 0x38    /* Flush FIFO of FX2 USB EP6 IN. */
+#define CMD_FPGA_INIT  0x50    /* Used before and after FPGA bitstream upload. */
+#define CMD_KAUTH      0x60    /* Communicate to auth IC (U10). Not used. */
+#define CMD_EEPROM     0xa2    /* R/W access to EEPROM content. */
 
 /*
- * fpga spi register addresses for control request CMD_FPGA_SPI:
- * There are around 60 byte-wide registers within the fpga and
- * these are the base addresses used for accessing them.
- * On the spi bus, the msb of the address byte is set for read
- * and cleared for write, but that is handled by the fx2 mcu
- * as appropriate. In this driver code just use IN transactions
- * to read, OUT to write.
+ * FPGA register addresses (base addresses when registers span multiple
+ * bytes, in that case data is kept in little endian format). Passed to
+ * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail
+ * of SPI transfers encoding the read (1) or write (0) direction in the
+ * MSB of the address field. There are some 60 byte-wide FPGA registers.
+ *
+ * Unfortunately the FPGA registers change their meaning between the
+ * read and write directions of access, or exclusively provide one of
+ * these directions and not the other. This is an arbitrary vendor's
+ * choice, there is nothing which the sigrok driver could do about it.
+ * Values written to registers typically cannot get read back, neither
+ * verified after writing a configuration, nor queried upon startup for
+ * automatic detection of the current configuration. Neither appear to
+ * be there echo registers for presence and communication checks, nor
+ * version identifying registers, as far as we know.
  */
-#define REG_RUN                0x00    /* read capture status, write capture start */
-#define REG_PWM_EN     0x02    /* user pwm channels on/off */
-#define REG_CAPT_MODE  0x03    /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */
-#define REG_BULK       0x08    /* write start address and number of bytes for capture data bulk upload */
-#define REG_SAMPLING   0x10    /* write capture config, read capture data location in sdram */
-#define REG_TRIGGER    0x20    /* write level and edge trigger config */
-#define REG_THRESHOLD  0x68    /* write two pwm configs to control input threshold dac */
-#define REG_PWM1       0x70    /* write config for user pwm1 */
-#define REG_PWM2       0x78    /* write config for user pwm2 */
+#define REG_RUN                0x00    /* Read capture status, write start capture. */
+#define REG_PWM_EN     0x02    /* User PWM channels on/off. */
+#define REG_CAPT_MODE  0x03    /* Write 0x00 capture to SDRAM, 0x01 streaming. */
+#define REG_PIN_STATE  0x04    /* Read current pin state (real time display). */
+#define REG_BULK       0x08    /* Write start addr, byte count to download samples. */
+#define REG_SAMPLING   0x10    /* Write capture config, read capture SDRAM location. */
+#define REG_TRIGGER    0x20    /* Write level and edge trigger config. */
+#define REG_UNKNOWN_30 0x30
+#define REG_THRESHOLD  0x68    /* Write PWM config to setup input threshold DAC. */
+#define REG_PWM1       0x70    /* Write config for user PWM1. */
+#define REG_PWM2       0x78    /* Write config for user PWM2. */
+
+/* Bit patterns to write to REG_CAPT_MODE. */
+#define CAPTMODE_TO_RAM        0x00
+#define CAPTMODE_STREAM        0x01
+
+/* Bit patterns to write to REG_RUN, setup run mode. */
+#define RUNMODE_HALT   0x00
+#define RUNMODE_RUN    0x03
+
+/* Bit patterns when reading from REG_RUN, get run state. */
+#define RUNSTATE_IDLE_BIT      (1UL << 0)
+#define RUNSTATE_DRAM_BIT      (1UL << 1)
+#define RUNSTATE_TRGD_BIT      (1UL << 2)
+#define RUNSTATE_POST_BIT      (1UL << 3)
 
 static int ctrl_in(const struct sr_dev_inst *sdi,
-                  uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
-                  void *data, uint16_t wLength)
+       uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
+       void *data, uint16_t wLength)
 {
        struct sr_usb_dev_inst *usb;
        int ret;
 
        usb = sdi->conn;
 
-       if ((ret = libusb_control_transfer(
-                    usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
-                    bRequest, wValue, wIndex, (unsigned char *)data, wLength,
-                    DEFAULT_TIMEOUT_MS)) != wLength) {
-               sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.",
-                      wLength, bRequest, wValue, wIndex,
-                      libusb_error_name(ret));
-               return SR_ERR;
+       ret = libusb_control_transfer(usb->devhdl,
+               LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
+               bRequest, wValue, wIndex, data, wLength,
+               DEFAULT_TIMEOUT_MS);
+       if (ret != wLength) {
+               sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.",
+                       wLength, bRequest, wValue, wIndex,
+                       libusb_error_name(ret));
+               sr_err("Cannot read %d bytes from USB: %s.",
+                       wLength, libusb_error_name(ret));
+               return SR_ERR_IO;
        }
 
        return SR_OK;
 }
 
 static int ctrl_out(const struct sr_dev_inst *sdi,
-                   uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
-                   void *data, uint16_t wLength)
+       uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
+       void *data, uint16_t wLength)
 {
        struct sr_usb_dev_inst *usb;
        int ret;
 
        usb = sdi->conn;
 
-       if ((ret = libusb_control_transfer(
-                    usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
-                    bRequest, wValue, wIndex, (unsigned char*)data, wLength,
-                    DEFAULT_TIMEOUT_MS)) != wLength) {
-               sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.",
-                      wLength, bRequest, wValue, wIndex,
-                      libusb_error_name(ret));
-               return SR_ERR;
+       ret = libusb_control_transfer(usb->devhdl,
+               LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
+               bRequest, wValue, wIndex, data, wLength,
+               DEFAULT_TIMEOUT_MS);
+       if (ret != wLength) {
+               sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.",
+                       wLength, bRequest, wValue, wIndex,
+                       libusb_error_name(ret));
+               sr_err("Cannot write %d bytes to USB: %s.",
+                       wLength, libusb_error_name(ret));
+               return SR_ERR_IO;
        }
 
        return SR_OK;
 }
 
-static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bitstream_fname)
+/* HACK Experiment to spot FPGA registers of interest. */
+static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi,
+       const char *caption, size_t reg_lower, size_t reg_upper)
+{
+       static const size_t dump_chunk_len = 16;
+
+       size_t rdlen;
+       uint8_t rdbuf[0x80 - 0x00];     /* Span all FPGA registers. */
+       const uint8_t *rdptr;
+       int ret;
+       size_t dump_addr, indent, dump_len;
+       GString *txt;
+
+       if (sr_log_loglevel_get() < SR_LOG_SPEW)
+               return;
+
+       if (!reg_lower && !reg_upper) {
+               reg_lower = 0;
+               reg_upper = sizeof(rdbuf);
+       }
+       if (reg_upper - reg_lower > sizeof(rdbuf))
+               reg_upper = sizeof(rdbuf) - reg_lower;
+
+       rdlen = reg_upper - reg_lower;
+       ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen);
+       if (ret != SR_OK) {
+               sr_err("Cannot get registers space.");
+               return;
+       }
+       rdptr = rdbuf;
+
+       sr_spew("FPGA registers dump: %s", caption ? : "for fun");
+       dump_addr = reg_lower;
+       while (rdlen) {
+               dump_len = rdlen;
+               indent = dump_addr % dump_chunk_len;
+               if (dump_len > dump_chunk_len)
+                       dump_len = dump_chunk_len;
+               if (dump_len + indent > dump_chunk_len)
+                       dump_len = dump_chunk_len - indent;
+               txt = sr_hexdump_new(rdptr, dump_len);
+               sr_spew("  %04zx  %*s%s",
+                       dump_addr, (int)(3 * indent), "", txt->str);
+               sr_hexdump_free(txt);
+               dump_addr += dump_len;
+               rdptr += dump_len;
+               rdlen -= dump_len;
+       }
+}
+
+/*
+ * Check the necessity for FPGA bitstream upload, because another upload
+ * would take some 600ms which is undesirable after program startup. Try
+ * to access some FPGA registers and check the values' plausibility. The
+ * check should fail on the safe side, request another upload when in
+ * doubt. A positive response (the request to continue operation with the
+ * currently active bitstream) should be conservative. Accessing multiple
+ * registers is considered cheap compared to the cost of bitstream upload.
+ *
+ * It helps though that both the vendor software and the sigrok driver
+ * use the same bundle of MCU firmware and FPGA bitstream for any of the
+ * supported models. We don't expect to successfully communicate to the
+ * device yet disagree on its protocol. Ideally we would access version
+ * identifying registers for improved robustness, but are not aware of
+ * any. A bitstream reload can always be forced by a power cycle.
+ */
+static int check_fpga_bitstream(const struct sr_dev_inst *sdi)
+{
+       uint8_t init_rsp;
+       uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */
+       int ret;
+       uint16_t run_state;
+       uint8_t pwm_en;
+       size_t read_len;
+       const uint8_t *rdptr;
+
+       sr_dbg("Checking operation of the FPGA bitstream.");
+       la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0);
+
+       init_rsp = ~0;
+       ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp));
+       if (ret != SR_OK || init_rsp != 0) {
+               sr_dbg("FPGA init query failed, or unexpected response.");
+               return SR_ERR_IO;
+       }
+
+       read_len = sizeof(run_state);
+       ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len);
+       if (ret != SR_OK) {
+               sr_dbg("FPGA register access failed (run state).");
+               return SR_ERR_IO;
+       }
+       rdptr = buff;
+       run_state = read_u16le_inc(&rdptr);
+       sr_spew("FPGA register: run state 0x%04x.", run_state);
+       if (run_state && (run_state & 0x3) != 0x1) {
+               sr_dbg("Unexpected FPGA register content (run state).");
+               return SR_ERR_DATA;
+       }
+       if (run_state && (run_state & ~0xf) != 0x85e0) {
+               sr_dbg("Unexpected FPGA register content (run state).");
+               return SR_ERR_DATA;
+       }
+
+       read_len = sizeof(pwm_en);
+       ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len);
+       if (ret != SR_OK) {
+               sr_dbg("FPGA register access failed (PWM enable).");
+               return SR_ERR_IO;
+       }
+       rdptr = buff;
+       pwm_en = read_u8_inc(&rdptr);
+       sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en);
+       if ((pwm_en & 0x3) != 0x0) {
+               sr_dbg("Unexpected FPGA register content (PWM enable).");
+               return SR_ERR_DATA;
+       }
+
+       sr_info("Could re-use current FPGA bitstream. No upload required.");
+       return SR_OK;
+}
+
+static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
+       const char *bitstream_fname)
 {
-       struct dev_context *devc;
        struct drv_context *drvc;
        struct sr_usb_dev_inst *usb;
        struct sr_resource bitstream;
+       uint32_t bitstream_size;
        uint8_t buffer[sizeof(uint32_t)];
        uint8_t *wrptr;
-       uint8_t cmd_resp;
        uint8_t block[4096];
        int len, act_len;
        unsigned int pos;
        int ret;
-       unsigned int zero_pad_to = 0x2c000;
+       unsigned int zero_pad_to;
 
-       devc = sdi->priv;
        drvc = sdi->driver->context;
        usb = sdi->conn;
 
        sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname);
 
-       ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname);
+       ret = sr_resource_open(drvc->sr_ctx, &bitstream,
+               SR_RESOURCE_FIRMWARE, bitstream_fname);
        if (ret != SR_OK) {
-               sr_err("could not find fpga firmware %s!", bitstream_fname);
+               sr_err("Cannot find FPGA bitstream %s.", bitstream_fname);
                return ret;
        }
 
-       devc->bitstream_size = (uint32_t)bitstream.size;
+       bitstream_size = (uint32_t)bitstream.size;
        wrptr = buffer;
-       write_u32le_inc(&wrptr, devc->bitstream_size);
-       if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
-               sr_err("failed to give upload init command");
+       write_u32le_inc(&wrptr, bitstream_size);
+       ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer);
+       if (ret != SR_OK) {
+               sr_err("Cannot initiate FPGA bitstream upload.");
                sr_resource_close(drvc->sr_ctx, &bitstream);
                return ret;
        }
+       zero_pad_to = bitstream_size;
+       zero_pad_to += LA2016_EP2_PADDING - 1;
+       zero_pad_to /= LA2016_EP2_PADDING;
+       zero_pad_to *= LA2016_EP2_PADDING;
 
        pos = 0;
        while (1) {
                if (pos < bitstream.size) {
-                       len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block));
+                       len = (int)sr_resource_read(drvc->sr_ctx, &bitstream,
+                               block, sizeof(block));
                        if (len < 0) {
-                               sr_err("failed to read from fpga bitstream!");
+                               sr_err("Cannot read FPGA bitstream.");
                                sr_resource_close(drvc->sr_ctx, &bitstream);
-                               return SR_ERR;
+                               return SR_ERR_IO;
                        }
                } else {
-                       // fill with zero's until zero_pad_to
+                       /*  Zero-pad until 'zero_pad_to'. */
                        len = zero_pad_to - pos;
                        if ((unsigned)len > sizeof(block))
                                len = sizeof(block);
@@ -172,101 +342,103 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bits
                if (len == 0)
                        break;
 
-               ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
+               ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM,
+                       &block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
                if (ret != 0) {
-                       sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret));
-                       ret = SR_ERR;
+                       sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.",
+                               pos, (int)len, libusb_error_name(ret));
+                       ret = SR_ERR_IO;
                        break;
                }
                if (act_len != len) {
-                       sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len);
-                       ret = SR_ERR;
+                       sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.",
+                               pos, (int)len, act_len);
+                       ret = SR_ERR_IO;
                        break;
                }
                pos += len;
        }
        sr_resource_close(drvc->sr_ctx, &bitstream);
-       if (ret != 0)
+       if (ret != SR_OK)
                return ret;
-       sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size);
+       sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.",
+               bitstream.size);
+
+       return SR_OK;
+}
 
-       if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
-               sr_err("failed to read response after FPGA bitstream upload");
+static int enable_fpga_bitstream(const struct sr_dev_inst *sdi)
+{
+       int ret;
+       uint8_t resp;
+
+       ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp));
+       if (ret != SR_OK) {
+               sr_err("Cannot read response after FPGA bitstream upload.");
                return ret;
        }
-       if (cmd_resp != 0) {
-               sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp);
-               return SR_ERR;
+       if (resp != 0) {
+               sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.",
+                       resp);
+               return SR_ERR_DATA;
        }
+       g_usleep(30 * 1000);
 
-       g_usleep(30000);
-
-       if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) {
-               sr_err("failed enable fpga");
+       ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0);
+       if (ret != SR_OK) {
+               sr_err("Cannot enable FPGA after bitstream upload.");
                return ret;
        }
+       g_usleep(40 * 1000);
 
-       g_usleep(40000);
        return SR_OK;
 }
 
 static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
 {
-       struct dev_context *devc;
        int ret;
-
-       devc = sdi->priv;
-
-       uint16_t duty_R79,duty_R56;
-       uint8_t buf[2 * sizeof(uint16_t)];
+       uint16_t duty_R79, duty_R56;
+       uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */
        uint8_t *wrptr;
 
-       /* clamp threshold setting within valid range for LA2016 */
-       if (voltage > 4.0) {
-               voltage = 4.0;
-       }
-       else if (voltage < -4.0) {
-               voltage = -4.0;
+       /* Clamp threshold setting to valid range for LA2016. */
+       if (voltage > LA2016_THR_VOLTAGE_MAX) {
+               voltage = LA2016_THR_VOLTAGE_MAX;
+       } else if (voltage < -LA2016_THR_VOLTAGE_MAX) {
+               voltage = -LA2016_THR_VOLTAGE_MAX;
        }
 
        /*
-        * The fpga has two programmable pwm outputs which feed a dac that
-        * is used to adjust input offset. The dac changes the input
-        * swing around the fixed fpga input threshold.
-        * The two pwm outputs can be seen on R79 and R56 respectvely.
-        * Frequency is fixed at 100kHz and duty is varied.
-        * The R79 pwm uses just three settings.
-        * The R56 pwm varies with required threshold and its behaviour
-        * also changes depending on the setting of R79 PWM.
-        */
-
-       /*
-        * calculate required pwm duty register values from requested threshold voltage
-        * see last page of schematic (on wiki) for an explanation of these numbers
+        * Two PWM output channels feed one DAC which generates a bias
+        * voltage, which offsets the input probe's voltage level, and
+        * in combination with the FPGA pins' fixed threshold result in
+        * a programmable input threshold from the user's perspective.
+        * The PWM outputs can be seen on R79 and R56 respectively, the
+        * frequency is 100kHz and the duty cycle varies. The R79 PWM
+        * uses three discrete settings. The R56 PWM varies with desired
+        * thresholds and depends on the R79 PWM configuration. See the
+        * schematics comments which discuss the formulae.
         */
        if (voltage >= 2.9) {
-               duty_R79 = 0;           /* this pwm is off (0V)*/
+               duty_R79 = 0;           /* PWM off (0V). */
                duty_R56 = (uint16_t)(302 * voltage - 363);
-       }
-       else if (voltage <= -0.4) {
-               duty_R79 = 0x02D7;      /* 72% duty */
-               duty_R56 = (uint16_t)(302 * voltage + 1090);
-       }
-       else {
-               duty_R79 = 0x00f2;      /* 25% duty */
+       } else if (voltage > -0.4) {
+               duty_R79 = 0x00f2;      /* 25% duty cycle. */
                duty_R56 = (uint16_t)(302 * voltage + 121);
+       } else {
+               duty_R79 = 0x02d7;      /* 72% duty cycle. */
+               duty_R56 = (uint16_t)(302 * voltage + 1090);
        }
 
-       /* clamp duty register values at sensible limits */
+       /* Clamp duty register values to sensible limits. */
        if (duty_R56 < 10) {
                duty_R56 = 10;
-       }
-       else if (duty_R56 > 1100) {
+       } else if (duty_R56 > 1100) {
                duty_R56 = 1100;
        }
 
-       sr_dbg("set threshold voltage %.2fV", voltage);
-       sr_dbg("duty_R56=0x%04x, duty_R79=0x%04x", duty_R56, duty_R79);
+       sr_dbg("Set threshold voltage %.2fV.", voltage);
+       sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79);
 
        wrptr = buf;
        write_u16le_inc(&wrptr, duty_R56);
@@ -274,149 +446,190 @@ static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
 
        ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf);
        if (ret != SR_OK) {
-               sr_err("error setting new threshold voltage of %.2fV", voltage);
+               sr_err("Cannot set threshold voltage %.2fV.", voltage);
                return ret;
        }
-       devc->threshold_voltage = voltage;
 
        return SR_OK;
 }
 
-static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2)
+/*
+ * Communicates a channel's configuration to the device after the
+ * parameters may have changed. Configuration of one channel may
+ * interfere with other channels since they share FPGA registers.
+ */
+static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
 {
+       static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, };
+
        struct dev_context *devc;
-       uint8_t cfg;
+       struct pwm_setting *params;
+       uint8_t reg_base;
+       double val_f;
+       uint32_t val_u;
+       uint32_t period, duty;
+       size_t ch;
        int ret;
+       uint8_t enable_all, enable_cfg, reg_val;
+       uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */
+       uint8_t *wrptr;
 
        devc = sdi->priv;
-       cfg = 0;
+       if (idx >= ARRAY_SIZE(devc->pwm_setting))
+               return SR_ERR_ARG;
+       params = &devc->pwm_setting[idx];
+       if (idx >= ARRAY_SIZE(reg_bases))
+               return SR_ERR_ARG;
+       reg_base = reg_bases[idx];
 
-       if (p1) cfg |= 1 << 0;
-       if (p2) cfg |= 1 << 1;
+       /*
+        * Map application's specs to hardware register values. Do math
+        * in floating point initially, but convert to u32 eventually.
+        */
+       sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.",
+               idx, params->enabled ? 1 : 0, params->freq, params->duty);
+       val_f = PWM_CLOCK;
+       val_f /= params->freq;
+       val_u = val_f;
+       period = val_u;
+       val_f = period;
+       val_f *= params->duty;
+       val_f /= 100.0;
+       val_f += 0.5;
+       val_u = val_f;
+       duty = val_u;
+       sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.",
+               (unsigned)reg_base, (unsigned)period, (unsigned)duty);
+
+       /* Get the "enabled" state of all supported PWM channels. */
+       enable_all = 0;
+       for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) {
+               if (!devc->pwm_setting[ch].enabled)
+                       continue;
+               enable_all |= 1U << ch;
+       }
+       enable_cfg = 1U << idx;
+       sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.",
+               enable_all, enable_cfg);
 
-       sr_dbg("set pwm enable %d %d", p1, p2);
-       ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg));
+       /*
+        * Disable the to-get-configured channel before its parameters
+        * will change. Or disable and exit when the channel is supposed
+        * to get turned off.
+        */
+       sr_spew("PWM config, disabling before param change.");
+       reg_val = enable_all & ~enable_cfg;
+       ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
+               &reg_val, sizeof(reg_val));
        if (ret != SR_OK) {
-               sr_err("error setting new pwm enable 0x%02x", cfg);
+               sr_err("Cannot adjust PWM enabled state.");
                return ret;
        }
-       devc->pwm_setting[0].enabled = (p1) ? 1 : 0;
-       devc->pwm_setting[1].enabled = (p2) ? 1 : 0;
+       if (!params->enabled)
+               return SR_OK;
 
-       return SR_OK;
-}
-
-static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty)
-{
-       int CTRL_PWM[] = { REG_PWM1, REG_PWM2 };
-       struct dev_context *devc;
-       pwm_setting_dev_t cfg;
-       pwm_setting_t *setting;
-       int ret;
-       uint8_t buf[2 * sizeof(uint32_t)];
-       uint8_t *wrptr;
-
-       devc = sdi->priv;
-
-       if (which < 1 || which > 2) {
-               sr_err("invalid pwm channel: %d", which);
-               return SR_ERR;
-       }
-       if (freq > MAX_PWM_FREQ) {
-               sr_err("pwm frequency too high: %.1f", freq);
-               return SR_ERR;
-       }
-       if (duty > 100 || duty < 0) {
-               sr_err("invalid pwm percentage: %f", duty);
-               return SR_ERR;
+       /* Write register values to device. */
+       sr_spew("PWM config, sending new parameters.");
+       wrptr = buf;
+       write_u32le_inc(&wrptr, period);
+       write_u32le_inc(&wrptr, duty);
+       ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf);
+       if (ret != SR_OK) {
+               sr_err("Cannot change PWM parameters.");
+               return ret;
        }
 
-       cfg.period = (uint32_t)(PWM_CLOCK / freq);
-       cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.));
-       sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty);
-
-       wrptr = buf;
-       write_u32le_inc(&wrptr, cfg.period);
-       write_u32le_inc(&wrptr, cfg.duty);
-       ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf);
+       /* Enable configured channel after write completion. */
+       sr_spew("PWM config, enabling after param change.");
+       reg_val = enable_all | enable_cfg;
+       ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
+               &reg_val, sizeof(reg_val));
        if (ret != SR_OK) {
-               sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty);
+               sr_err("Cannot adjust PWM enabled state.");
                return ret;
        }
-       setting = &devc->pwm_setting[which - 1];
-       setting->freq = freq;
-       setting->duty = duty;
 
        return SR_OK;
 }
 
-static int set_defaults(const struct sr_dev_inst *sdi)
+/*
+ * Determine the number of enabled channels as well as their bitmask
+ * representation. Derive data here which later simplifies processing
+ * of raw capture data memory content in streaming mode.
+ */
+static void la2016_prepare_stream(const struct sr_dev_inst *sdi)
 {
        struct dev_context *devc;
-       int ret;
+       struct stream_state_t *stream;
+       size_t channel_mask;
+       GSList *l;
+       struct sr_channel *ch;
 
        devc = sdi->priv;
-
-       devc->capture_ratio = 5; /* percent */
-       devc->cur_channels = 0xffff;
-       devc->limit_samples = 5000000;
-       devc->cur_samplerate = SR_MHZ(100);
-
-       ret = set_threshold_voltage(sdi, devc->threshold_voltage);
-       if (ret)
-               return ret;
-
-       ret = enable_pwm(sdi, 0, 0);
-       if (ret)
-               return ret;
-
-       ret = set_pwm(sdi, 1, 1e3, 50);
-       if (ret)
-               return ret;
-
-       ret = set_pwm(sdi, 2, 100e3, 50);
-       if (ret)
-               return ret;
-
-       ret = enable_pwm(sdi, 1, 1);
-       if (ret)
-               return ret;
-
-       return SR_OK;
+       stream = &devc->stream;
+       memset(stream, 0, sizeof(*stream));
+
+       stream->enabled_count = 0;
+       for (l = sdi->channels; l; l = l->next) {
+               ch = l->data;
+               if (ch->type != SR_CHANNEL_LOGIC)
+                       continue;
+               if (!ch->enabled)
+                       continue;
+               channel_mask = 1UL << ch->index;
+               stream->enabled_mask |= channel_mask;
+               stream->channel_masks[stream->enabled_count++] = channel_mask;
+       }
+       stream->channel_index = 0;
 }
 
+/*
+ * This routine configures the set of enabled channels, as well as the
+ * trigger condition (if one was specified). Also prepares the capture
+ * data processing in stream mode, where the memory layout dramatically
+ * differs from normal mode.
+ */
 static int set_trigger_config(const struct sr_dev_inst *sdi)
 {
        struct dev_context *devc;
        struct sr_trigger *trigger;
-       trigger_cfg_t cfg;
+       struct trigger_cfg {
+               uint32_t channels;      /* Actually: Enabled channels? */
+               uint32_t enabled;       /* Actually: Triggering channels? */
+               uint32_t level;
+               uint32_t high_or_falling;
+       } cfg;
        GSList *stages;
        GSList *channel;
        struct sr_trigger_stage *stage1;
        struct sr_trigger_match *match;
-       uint16_t ch_mask;
+       uint32_t ch_mask;
        int ret;
-       uint8_t buf[4 * sizeof(uint32_t)];
+       uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */
        uint8_t *wrptr;
 
        devc = sdi->priv;
-       trigger = sr_session_trigger_get(sdi->session);
 
-       memset(&cfg, 0, sizeof(cfg));
-
-       cfg.channels = devc->cur_channels;
+       la2016_prepare_stream(sdi);
 
+       memset(&cfg, 0, sizeof(cfg));
+       cfg.channels = devc->stream.enabled_mask;
+       if (!cfg.channels) {
+               sr_err("Need at least one enabled logic channel.");
+               return SR_ERR_ARG;
+       }
+       trigger = sr_session_trigger_get(sdi->session);
        if (trigger && trigger->stages) {
                stages = trigger->stages;
                stage1 = stages->data;
                if (stages->next) {
                        sr_err("Only one trigger stage supported for now.");
-                       return SR_ERR;
+                       return SR_ERR_ARG;
                }
                channel = stage1->matches;
                while (channel) {
                        match = channel->data;
-                       ch_mask = 1 << match->channel->index;
+                       ch_mask = 1UL << match->channel->index;
 
                        switch (match->match) {
                        case SR_TRIGGER_ZERO:
@@ -429,162 +642,318 @@ static int set_trigger_config(const struct sr_dev_inst *sdi)
                                break;
                        case SR_TRIGGER_RISING:
                                if ((cfg.enabled & ~cfg.level)) {
-                                       sr_err("Only one trigger signal with falling-/rising-edge allowed.");
-                                       return SR_ERR;
+                                       sr_err("Device only supports one edge trigger.");
+                                       return SR_ERR_ARG;
                                }
                                cfg.level &= ~ch_mask;
                                cfg.high_or_falling &= ~ch_mask;
                                break;
                        case SR_TRIGGER_FALLING:
                                if ((cfg.enabled & ~cfg.level)) {
-                                       sr_err("Only one trigger signal with falling-/rising-edge allowed.");
-                                       return SR_ERR;
+                                       sr_err("Device only supports one edge trigger.");
+                                       return SR_ERR_ARG;
                                }
                                cfg.level &= ~ch_mask;
                                cfg.high_or_falling |= ch_mask;
                                break;
                        default:
-                               sr_err("Unknown trigger value.");
-                               return SR_ERR;
+                               sr_err("Unknown trigger condition.");
+                               return SR_ERR_ARG;
                        }
                        cfg.enabled |= ch_mask;
                        channel = channel->next;
                }
        }
-       sr_dbg("set trigger configuration channels: 0x%04x, "
-              "trigger-enabled 0x%04x, level-triggered 0x%04x, "
-              "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level,
-              cfg.high_or_falling);
+       sr_dbg("Set trigger config: "
+               "enabled-channels 0x%04x, triggering-channels 0x%04x, "
+               "level-triggered 0x%04x, high/falling 0x%04x.",
+               cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling);
+
+       /*
+        * Don't configure hardware trigger parameters in streaming mode
+        * or when the device lacks local memory. Yet the above dump of
+        * derived parameters from user specs is considered valueable.
+        *
+        * TODO Add support for soft triggers when hardware triggers in
+        * the device are not used or are not available at all.
+        */
+       if (!devc->model->memory_bits || devc->continuous) {
+               if (!devc->model->memory_bits)
+                       sr_dbg("Device without memory. No hardware triggers.");
+               else if (devc->continuous)
+                       sr_dbg("Streaming mode. No hardware triggers.");
+               cfg.enabled = 0;
+               cfg.level = 0;
+               cfg.high_or_falling = 0;
+       }
 
-       devc->had_triggers_configured = cfg.enabled != 0;
+       devc->trigger_involved = cfg.enabled != 0;
 
        wrptr = buf;
        write_u32le_inc(&wrptr, cfg.channels);
        write_u32le_inc(&wrptr, cfg.enabled);
        write_u32le_inc(&wrptr, cfg.level);
        write_u32le_inc(&wrptr, cfg.high_or_falling);
+       /* TODO
+        * Comment on this literal 16. Origin, meaning? Cannot be the
+        * register offset, nor the transfer length. Is it a channels
+        * count that is relevant for 16 and 32 channel models? Is it
+        * an obsolete experiment?
+        */
        ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf);
        if (ret != SR_OK) {
-               sr_err("error setting trigger config!");
+               sr_err("Cannot setup trigger configuration.");
                return ret;
        }
 
        return SR_OK;
 }
 
+/*
+ * This routine communicates the sample configuration to the device:
+ * Total samples count and samplerate, pre-trigger configuration.
+ */
 static int set_sample_config(const struct sr_dev_inst *sdi)
 {
        struct dev_context *devc;
-       double clock_divisor;
-       uint64_t total;
-       int ret;
-       uint16_t divisor;
-       uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)];
+       uint64_t baseclock;
+       uint64_t min_samplerate, eff_samplerate;
+       uint64_t stream_bandwidth;
+       uint16_t divider_u16;
+       uint64_t limit_samples;
+       uint64_t pre_trigger_samples;
+       uint64_t pre_trigger_memory;
+       uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
        uint8_t *wrptr;
+       int ret;
 
        devc = sdi->priv;
-       total = 128 * 1024 * 1024;
 
-       if (devc->cur_samplerate > devc->max_samplerate) {
-               sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate);
-               return SR_ERR;
+       /*
+        * The base clock need not be identical to the maximum samplerate,
+        * and differs between models. The 500MHz devices even use a base
+        * clock of 800MHz, and communicate divider 1 to the hardware to
+        * configure the 500MHz samplerate. This allows them to operate at
+        * a 200MHz samplerate which uses divider 4.
+        */
+       if (devc->samplerate > devc->model->samplerate) {
+               sr_err("Too high a sample rate: %" PRIu64 ".",
+                       devc->samplerate);
+               return SR_ERR_ARG;
        }
-
-       clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate;
-       if (clock_divisor > 0xffff)
-               clock_divisor = 0xffff;
-       divisor = (uint16_t)(clock_divisor + 0.5);
-       devc->cur_samplerate = devc->max_samplerate / divisor;
-
-       if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
-               sr_err("too high sample depth: %" PRIu64, devc->limit_samples);
-               return SR_ERR;
+       baseclock = devc->model->baseclock;
+       if (!baseclock)
+               baseclock = devc->model->samplerate;
+       min_samplerate = baseclock;
+       min_samplerate /= 65536;
+       if (devc->samplerate < min_samplerate) {
+               sr_err("Too low a sample rate: %" PRIu64 ".",
+                       devc->samplerate);
+               return SR_ERR_ARG;
        }
+       divider_u16 = baseclock / devc->samplerate;
+       eff_samplerate = baseclock / divider_u16;
+       if (eff_samplerate > devc->model->samplerate)
+               eff_samplerate = devc->model->samplerate;
 
-       devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100;
+       ret = sr_sw_limits_get_remain(&devc->sw_limits,
+               &limit_samples, NULL, NULL, NULL);
+       if (ret != SR_OK) {
+               sr_err("Cannot get acquisition limits.");
+               return ret;
+       }
+       if (limit_samples > LA2016_NUM_SAMPLES_MAX) {
+               sr_warn("Too high a sample depth: %" PRIu64 ", capping.",
+                       limit_samples);
+               limit_samples = LA2016_NUM_SAMPLES_MAX;
+       }
+       if (limit_samples == 0) {
+               limit_samples = LA2016_NUM_SAMPLES_MAX;
+               sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.",
+                       limit_samples);
+       }
 
-       sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%",
-              devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio);
+       /*
+        * The acquisition configuration communicates "pre-trigger"
+        * specs in several formats. sigrok users provide a percentage
+        * (0-100%), which translates to a pre-trigger samples count
+        * (assuming that a total samples count limit was specified).
+        * The device supports hardware compression, which depends on
+        * slowly changing input data to be effective. Fast changing
+        * input data may occupy more space in sample memory than its
+        * uncompressed form would. This is why a third parameter can
+        * limit the amount of sample memory to use for pre-trigger
+        * data. Only the upper 24 bits of that memory size spec get
+        * communicated to the device (written to its FPGA register).
+        */
+       if (!devc->model->memory_bits) {
+               sr_dbg("Memory-less device, skipping pre-trigger config.");
+               pre_trigger_samples = 0;
+               pre_trigger_memory = 0;
+       } else if (devc->trigger_involved) {
+               pre_trigger_samples = limit_samples;
+               pre_trigger_samples *= devc->capture_ratio;
+               pre_trigger_samples /= 100;
+               pre_trigger_memory = devc->model->memory_bits;
+               pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024);
+               pre_trigger_memory /= 8; /* devc->model->channel_count ? */
+               pre_trigger_memory *= devc->capture_ratio;
+               pre_trigger_memory /= 100;
+       } else {
+               sr_dbg("No trigger setup, skipping pre-trigger config.");
+               pre_trigger_samples = 0;
+               pre_trigger_memory = 0;
+       }
+       /* Ensure non-zero value after LSB shift out in HW reg. */
+       if (pre_trigger_memory < 0x100)
+               pre_trigger_memory = 0x100;
+
+       sr_dbg("Set sample config: %" PRIu64 "kHz (div %" PRIu16 "), %" PRIu64 " samples.",
+               eff_samplerate / SR_KHZ(1), divider_u16, limit_samples);
+       sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".",
+               devc->capture_ratio, pre_trigger_samples, pre_trigger_memory);
+
+       if (devc->continuous) {
+               stream_bandwidth = eff_samplerate;
+               stream_bandwidth *= devc->stream.enabled_count;
+               sr_dbg("Streaming: channel count %zu, product %" PRIu64 ".",
+                       devc->stream.enabled_count, stream_bandwidth);
+               stream_bandwidth /= 1000 * 1000;
+               if (stream_bandwidth >= LA2016_STREAM_MBPS_MAX) {
+                       sr_warn("High USB stream bandwidth: %" PRIu64 "Mbps.",
+                               stream_bandwidth);
+               }
+               if (stream_bandwidth < LA2016_STREAM_PUSH_THR) {
+                       sr_dbg("Streaming: low Mbps, suggest periodic flush.");
+                       devc->stream.flush_period_ms = LA2016_STREAM_PUSH_IVAL;
+               }
+       }
 
+       /*
+        * The acquisition configuration occupies a total of 16 bytes:
+        * - A 34bit total samples count limit (up to 10 billions) that
+        *   is kept in a 40bit register.
+        * - A 34bit pre-trigger samples count limit (up to 10 billions)
+        *   in another 40bit register.
+        * - A 32bit pre-trigger memory space limit (in bytes) of which
+        *   the upper 24bits are kept in an FPGA register.
+        * - A 16bit clock divider which gets applied to the maximum
+        *   samplerate of the device.
+        * - An 8bit register of unknown meaning. Currently always 0.
+        */
        wrptr = buf;
-       write_u32le_inc(&wrptr, devc->limit_samples);
-       write_u8_inc(&wrptr, 0);
-       write_u32le_inc(&wrptr, devc->pre_trigger_size);
-       write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00);
-       write_u16le_inc(&wrptr, divisor);
+       write_u40le_inc(&wrptr, limit_samples);
+       write_u40le_inc(&wrptr, pre_trigger_samples);
+       write_u24le_inc(&wrptr, pre_trigger_memory >> 8);
+       write_u16le_inc(&wrptr, divider_u16);
        write_u8_inc(&wrptr, 0);
-
        ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf);
        if (ret != SR_OK) {
-               sr_err("error setting sample config!");
+               sr_err("Cannot setup acquisition configuration.");
                return ret;
        }
 
        return SR_OK;
 }
 
-/* The run state is read from FPGA registers 1[hi-byte] and 0[lo-byte]
- * and the bits are interpreted as follows:
- *
- * register 0:
- *     bit0 1= idle
- *     bit1 1= writing to sdram
- *     bit2 0= waiting_for_trigger 1=been_triggered
- *     bit3 0= pretrigger_sampling 1=posttrigger_sampling
- *     ...unknown...
- * register 1:
- *     meaning of bits unknown (but vendor software reads this, so just do the same)
+/*
+ * FPGA register REG_RUN holds the run state (u16le format). Bit fields
+ * of interest:
+ *   bit 0: value 1 = idle
+ *   bit 1: value 1 = writing to SDRAM
+ *   bit 2: value 0 = waiting for trigger, 1 = trigger seen
+ *   bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling
+ * The meaning of other bit fields is unknown.
  *
- * The run state values occur in this order:
- * 0x85E2: pre-sampling (for samples before trigger position, capture ratio > 0%)
- * 0x85EA: pre-sampling complete, now waiting for trigger (whilst sampling continuously)
- * 0x85EE: running
- * 0x85ED: idle
+ * Typical values in order of appearance during execution:
+ *   0x85e1: idle, no acquisition pending
+ *     IDLE set, TRGD don't care, POST don't care; DRAM don't care
+ *     "In idle state." Takes precedence over all others.
+ *   0x85e2: pre-sampling, samples before the trigger position,
+ *     when capture ratio > 0%
+ *     IDLE clear, TRGD clear, POST clear; DRAM don't care
+ *     "Not idle any more, no post yet, not triggered yet."
+ *   0x85ea: pre-sampling complete, now waiting for the trigger
+ *     (whilst sampling continuously)
+ *     IDLE clear, TRGD clear, POST set; DRAM don't care
+ *     "Post set thus after pre, not triggered yet"
+ *   0x85ee: trigger seen, capturing post-trigger samples, running
+ *     IDLE clear, TRGD set, POST set; DRAM don't care
+ *     "Triggered and in post, not idle yet."
+ *   0x85ed: idle
+ *     IDLE set, TRGD don't care, POST don't care; DRAM don't care
+ *     "In idle state." TRGD/POST don't care, same meaning as above.
  */
+static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT;
+static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT;
+static const uint16_t runstate_mask_step =
+       RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT;
+static const uint16_t runstate_patt_pre_trig = 0;
+static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT;
+static const uint16_t runstate_patt_post_trig =
+       RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT;
+
 static uint16_t run_state(const struct sr_dev_inst *sdi)
 {
-       uint16_t state;
-       static uint16_t previous_state = 0;
+       static uint16_t previous_state;
+
        int ret;
+       uint16_t state;
+       uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */
+       const uint8_t *rdptr;
+       const char *label;
 
-       if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) {
-               sr_err("failed to read run state!");
+       ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state));
+       if (ret != SR_OK) {
+               sr_err("Cannot read run state.");
                return ret;
        }
+       rdptr = buff;
+       state = read_u16le_inc(&rdptr);
 
-       /* This function is called about every 50ms.
-        * To avoid filling the log file with redundant information during long captures,
-        * just print a log message if status has changed.
+       /*
+        * Avoid flooding the log, only dump values as they change.
+        * The routine is called about every 50ms.
         */
-
-       if (state != previous_state) {
-               previous_state = state;
-               if ((state & 0x0003) == 0x01) {
-                       sr_dbg("run_state: 0x%04x (%s)", state, "idle");
-               }
-               else if ((state & 0x000f) == 0x02) {
-                       sr_dbg("run_state: 0x%04x (%s)", state, "pre-trigger sampling");
-               }
-               else if ((state & 0x000f) == 0x0a) {
-                       sr_dbg("run_state: 0x%04x (%s)", state, "sampling, waiting for trigger");
-               }
-               else if ((state & 0x000f) == 0x0e) {
-                       sr_dbg("run_state: 0x%04x (%s)", state, "post-trigger sampling");
-               }
-               else {
-                       sr_dbg("run_state: 0x%04x", state);
-               }
-       }
+       if (state == previous_state)
+               return state;
+
+       previous_state = state;
+       label = NULL;
+       if ((state & runstate_mask_idle) == runstate_patt_idle)
+               label = "idle";
+       if ((state & runstate_mask_step) == runstate_patt_pre_trig)
+               label = "pre-trigger sampling";
+       if ((state & runstate_mask_step) == runstate_patt_wait_trig)
+               label = "sampling, waiting for trigger";
+       if ((state & runstate_mask_step) == runstate_patt_post_trig)
+               label = "post-trigger sampling";
+       if (label && *label)
+               sr_dbg("Run state: 0x%04x (%s).", state, label);
+       else
+               sr_dbg("Run state: 0x%04x.", state);
 
        return state;
 }
 
-static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking)
+static gboolean la2016_is_idle(const struct sr_dev_inst *sdi)
+{
+       uint16_t state;
+
+       state = run_state(sdi);
+       if ((state & runstate_mask_idle) == runstate_patt_idle)
+               return TRUE;
+
+       return FALSE;
+}
+
+static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode)
 {
        int ret;
 
-       if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) {
-               sr_err("failed to send set-run-mode command %d", fast_blinking);
+       ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode));
+       if (ret != SR_OK) {
+               sr_err("Cannot configure run mode %d.", mode);
                return ret;
        }
 
@@ -595,13 +964,14 @@ static int get_capture_info(const struct sr_dev_inst *sdi)
 {
        struct dev_context *devc;
        int ret;
-       uint8_t buf[3 * sizeof(uint32_t)];
+       uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
        const uint8_t *rdptr;
 
        devc = sdi->priv;
 
-       if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) {
-               sr_err("failed to read capture info!");
+       ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf));
+       if (ret != SR_OK) {
+               sr_err("Cannot read capture info.");
                return ret;
        }
 
@@ -610,25 +980,199 @@ static int get_capture_info(const struct sr_dev_inst *sdi)
        devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
        devc->info.write_pos = read_u32le_inc(&rdptr);
 
-       sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d",
-              devc->info.n_rep_packets, devc->info.n_rep_packets,
-              devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger,
-              devc->info.write_pos, devc->info.write_pos);
+       sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.",
+               devc->info.n_rep_packets, devc->info.n_rep_packets,
+               devc->info.n_rep_packets_before_trigger,
+               devc->info.n_rep_packets_before_trigger,
+               devc->info.write_pos, devc->info.write_pos);
+
+       if (devc->info.n_rep_packets % devc->packets_per_chunk) {
+               sr_warn("Unexpected packets count %lu, not a multiple of %lu.",
+                       (unsigned long)devc->info.n_rep_packets,
+                       (unsigned long)devc->packets_per_chunk);
+       }
+
+       return SR_OK;
+}
+
+SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi,
+       struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload)
+{
+       struct dev_context *devc;
+       uint16_t pid;
+       char *fw;
+       int ret;
+
+       devc = sdi ? sdi->priv : NULL;
+       if (!devc || !devc->usb_pid)
+               return SR_ERR_ARG;
+       pid = devc->usb_pid;
+
+       fw = g_strdup_printf(MCU_FWFILE_FMT, pid);
+       sr_info("USB PID %04hx, MCU firmware '%s'.", pid, fw);
+       devc->mcu_firmware = g_strdup(fw);
+
+       if (skip_upload)
+               ret = SR_OK;
+       else
+               ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw);
+       g_free(fw);
+       if (ret != SR_OK)
+               return ret;
+
+       return SR_OK;
+}
+
+static void LIBUSB_CALL receive_transfer(struct libusb_transfer *xfer);
+
+static void la2016_usbxfer_release_cb(gpointer p)
+{
+       struct libusb_transfer *xfer;
+
+       xfer = p;
+       g_free(xfer->buffer);
+       libusb_free_transfer(xfer);
+}
+
+static int la2016_usbxfer_release(const struct sr_dev_inst *sdi)
+{
+       struct dev_context *devc;
+
+       devc = sdi ? sdi->priv : NULL;
+       if (!devc)
+               return SR_ERR_ARG;
+
+       /* Release all USB transfers. */
+       g_slist_free_full(devc->transfers, la2016_usbxfer_release_cb);
+       devc->transfers = NULL;
+
+       return SR_OK;
+}
+
+static int la2016_usbxfer_allocate(const struct sr_dev_inst *sdi)
+{
+       struct dev_context *devc;
+       size_t bufsize, xfercount;
+       uint8_t *buffer;
+       struct libusb_transfer *xfer;
+
+       devc = sdi ? sdi->priv : NULL;
+       if (!devc)
+               return SR_ERR_ARG;
 
-       if (devc->info.n_rep_packets % 5)
-               sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets);
+       /* Transfers were already allocated before? */
+       if (devc->transfers)
+               return SR_OK;
+
+       /*
+        * Allocate all USB transfers and their buffers. Arrange for a
+        * buffer size which is within the device's capabilities, and
+        * is a multiple of the USB endpoint's size, to make use of the
+        * RAW_IO performance feature.
+        *
+        * Implementation detail: The LA2016_USB_BUFSZ value happens
+        * to match all those constraints. No additional arithmetics is
+        * required in this location.
+        */
+       bufsize = LA2016_USB_BUFSZ;
+       xfercount = LA2016_USB_XFER_COUNT;
+       while (xfercount--) {
+               buffer = g_try_malloc(bufsize);
+               if (!buffer) {
+                       sr_err("Cannot allocate USB transfer buffer.");
+                       return SR_ERR_MALLOC;
+               }
+               xfer = libusb_alloc_transfer(0);
+               if (!xfer) {
+                       sr_err("Cannot allocate USB transfer.");
+                       g_free(buffer);
+                       return SR_ERR_MALLOC;
+               }
+               xfer->buffer = buffer;
+               devc->transfers = g_slist_append(devc->transfers, xfer);
+       }
+       devc->transfer_bufsize = bufsize;
 
        return SR_OK;
 }
 
-SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id)
+static int la2016_usbxfer_cancel_all(const struct sr_dev_inst *sdi)
 {
-       char fw_file[1024];
-       snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id);
-       return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
+       struct dev_context *devc;
+       GSList *l;
+       struct libusb_transfer *xfer;
+
+       devc = sdi ? sdi->priv : NULL;
+       if (!devc)
+               return SR_ERR_ARG;
+
+       /* Unconditionally cancel the transfer. Ignore errors. */
+       for (l = devc->transfers; l; l = l->next) {
+               xfer = l->data;
+               if (!xfer)
+                       continue;
+               libusb_cancel_transfer(xfer);
+       }
+
+       return SR_OK;
 }
 
-SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
+static int la2016_usbxfer_resubmit(const struct sr_dev_inst *sdi,
+       struct libusb_transfer *xfer)
+{
+       struct dev_context *devc;
+       struct sr_usb_dev_inst *usb;
+       libusb_transfer_cb_fn cb;
+       int ret;
+
+       devc = sdi ? sdi->priv : NULL;
+       usb = sdi ? sdi->conn : NULL;
+       if (!devc || !usb)
+               return SR_ERR_ARG;
+
+       if (!xfer)
+               return SR_ERR_ARG;
+
+       cb = receive_transfer;
+       libusb_fill_bulk_transfer(xfer, usb->devhdl,
+               USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN,
+               xfer->buffer, devc->transfer_bufsize,
+               cb, (void *)sdi, CAPTURE_TIMEOUT_MS);
+       ret = libusb_submit_transfer(xfer);
+       if (ret != 0) {
+               sr_err("Cannot submit USB transfer: %s.",
+                       libusb_error_name(ret));
+               return SR_ERR_IO;
+       }
+
+       return SR_OK;
+}
+
+static int la2016_usbxfer_submit_all(const struct sr_dev_inst *sdi)
+{
+       struct dev_context *devc;
+       GSList *l;
+       struct libusb_transfer *xfer;
+       int ret;
+
+       devc = sdi ? sdi->priv : NULL;
+       if (!devc)
+               return SR_ERR_ARG;
+
+       for (l = devc->transfers; l; l = l->next) {
+               xfer = l->data;
+               if (!xfer)
+                       return SR_ERR_ARG;
+               ret = la2016_usbxfer_resubmit(sdi, xfer);
+               if (ret != SR_OK)
+                       return ret;
+       }
+
+       return SR_OK;
+}
+
+SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi,
+       double voltage)
 {
        struct dev_context *devc;
        int ret;
@@ -636,13 +1180,14 @@ SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
 
        devc = sdi->priv;
 
-       ret = set_threshold_voltage(sdi, devc->threshold_voltage);
+       ret = set_threshold_voltage(sdi, voltage);
        if (ret != SR_OK)
                return ret;
 
-       cmd = 0;
-       if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) {
-               sr_err("failed to send stop sampling command");
+       cmd = devc->continuous ? CAPTMODE_STREAM : CAPTMODE_TO_RAM;
+       ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd));
+       if (ret != SR_OK) {
+               sr_err("Cannot send command to stop sampling.");
                return ret;
        }
 
@@ -659,225 +1204,718 @@ SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
 
 SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi)
 {
-       return set_run_mode(sdi, 3);
+       struct dev_context *devc;
+       int ret;
+
+       devc = sdi->priv;
+
+       ret = la2016_usbxfer_allocate(sdi);
+       if (ret != SR_OK)
+               return ret;
+
+       if (devc->continuous) {
+               ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
+               if (ret != SR_OK)
+                       return ret;
+
+               ret = la2016_usbxfer_submit_all(sdi);
+               if (ret != SR_OK)
+                       return ret;
+
+               /*
+                * Periodic receive callback will set runmode. This
+                * activity MUST be close to data reception, a pause
+                * between these steps breaks the stream's operation.
+                */
+       } else {
+               ret = set_run_mode(sdi, RUNMODE_RUN);
+               if (ret != SR_OK)
+                       return ret;
+       }
+
+       return SR_OK;
 }
 
-SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
+static int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
 {
-       return set_run_mode(sdi, 0);
+       struct dev_context *devc;
+       int ret;
+
+       ret = set_run_mode(sdi, RUNMODE_HALT);
+       if (ret != SR_OK)
+               return ret;
+
+       devc = sdi->priv;
+       if (devc->continuous)
+               devc->download_finished = TRUE;
+
+       return SR_OK;
 }
 
 SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi)
 {
-       return la2016_stop_acquisition(sdi);
-}
+       int ret;
 
-SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi)
-{
-       uint16_t state;
+       ret = la2016_stop_acquisition(sdi);
+       if (ret != SR_OK)
+               return ret;
 
-       state = run_state(sdi);
+       (void)la2016_usbxfer_cancel_all(sdi);
 
-       return (state & 0x3) == 1;
+       return SR_OK;
 }
 
-SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb)
+static int la2016_start_download(const struct sr_dev_inst *sdi)
 {
        struct dev_context *devc;
-       struct sr_usb_dev_inst *usb;
        int ret;
-       uint8_t wrbuf[2 * sizeof(uint32_t)];
+       uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */
        uint8_t *wrptr;
-       uint32_t to_read;
-       uint8_t *buffer;
 
        devc = sdi->priv;
-       usb = sdi->conn;
 
-       if ((ret = get_capture_info(sdi)) != SR_OK)
+       ret = get_capture_info(sdi);
+       if (ret != SR_OK)
                return ret;
 
-       devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
-       devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH;
+       devc->n_transfer_packets_to_read = devc->info.n_rep_packets;
+       devc->n_transfer_packets_to_read /= devc->packets_per_chunk;
+       devc->n_bytes_to_read = devc->n_transfer_packets_to_read;
+       devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH;
        devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
        devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
 
-       sr_dbg("want to read %d tfer-packets starting from pos %d",
-              devc->n_transfer_packets_to_read, devc->read_pos);
+       sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".",
+               devc->n_transfer_packets_to_read, devc->read_pos);
 
-       if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
-               sr_err("failed to reset bulk state");
+       ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
+       if (ret != SR_OK) {
+               sr_err("Cannot reset USB bulk state.");
                return ret;
        }
-       sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read);
+       sr_dbg("Will read from 0x%08lx, 0x%08x bytes.",
+               (unsigned long)devc->read_pos, devc->n_bytes_to_read);
        wrptr = wrbuf;
        write_u32le_inc(&wrptr, devc->read_pos);
        write_u32le_inc(&wrptr, devc->n_bytes_to_read);
-       if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) {
-               sr_err("failed to send bulk config");
+       ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf);
+       if (ret != SR_OK) {
+               sr_err("Cannot send USB bulk config.");
                return ret;
        }
-       if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) {
-               sr_err("failed to unblock bulk transfers");
+
+       ret = la2016_usbxfer_submit_all(sdi);
+       if (ret != SR_OK) {
+               sr_err("Cannot submit USB bulk transfers.");
                return ret;
        }
 
-       to_read = devc->n_bytes_to_read;
-       /* choose a buffer size for all of the usb transfers */
-       if (to_read >= LA2016_USB_BUFSZ)
-               to_read = LA2016_USB_BUFSZ; /* multiple transfers */
-       else /* one transfer, make buffer size some multiple of LA2016_EP6_PKTSZ */
-               to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1);
-       buffer = g_try_malloc(to_read);
-       if (!buffer) {
-               sr_err("Failed to allocate %d bytes for bulk transfer", to_read);
-               return SR_ERR_MALLOC;
+       ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0);
+       if (ret != SR_OK) {
+               sr_err("Cannot start USB bulk transfers.");
+               return ret;
        }
 
-       devc->transfer = libusb_alloc_transfer(0);
-       libusb_fill_bulk_transfer(
-               devc->transfer, usb->devhdl,
-               0x86, buffer, to_read,
-               cb, (void *)sdi, DEFAULT_TIMEOUT_MS);
+       return SR_OK;
+}
+
+/*
+ * A chunk (received via USB) contains a number of transfers (USB length
+ * divided by 16) which contain a number of packets (5 per transfer) which
+ * contain a number of samples (8bit repeat count per 16bit sample data).
+ */
+static void send_chunk(struct sr_dev_inst *sdi,
+       const uint8_t *data_buffer, size_t data_length)
+{
+       struct dev_context *devc;
+       size_t num_xfers, num_pkts;
+       const uint8_t *rp;
+       uint32_t sample_value;
+       size_t repetitions;
+       uint8_t sample_buff[sizeof(sample_value)];
+
+       devc = sdi->priv;
+
+       /* Ignore incoming USB data after complete sample data download. */
+       if (devc->download_finished)
+               return;
 
-       if ((ret = libusb_submit_transfer(devc->transfer)) != 0) {
-               sr_err("Failed to submit transfer: %s.", libusb_error_name(ret));
-               libusb_free_transfer(devc->transfer);
-               devc->transfer = NULL;
-               g_free(buffer);
-               return SR_ERR;
+       if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) {
+               feed_queue_logic_send_trigger(devc->feed_queue);
+               devc->trigger_marked = TRUE;
        }
 
-       return SR_OK;
+       /*
+        * Adjust the number of remaining bytes to read from the device
+        * before the processing of the currently received chunk affects
+        * the variable which holds the number of received bytes.
+        */
+       if (data_length > devc->n_bytes_to_read)
+               devc->n_bytes_to_read = 0;
+       else
+               devc->n_bytes_to_read -= data_length;
+
+       /* Process the received chunk of capture data. */
+       sample_value = 0;
+       rp = data_buffer;
+       num_xfers = data_length / TRANSFER_PACKET_LENGTH;
+       while (num_xfers--) {
+               num_pkts = devc->packets_per_chunk;
+               while (num_pkts--) {
+
+                       /* TODO Verify 32channel layout. */
+                       if (devc->model->channel_count == 32)
+                               sample_value = read_u32le_inc(&rp);
+                       else if (devc->model->channel_count == 16)
+                               sample_value = read_u16le_inc(&rp);
+                       repetitions = read_u8_inc(&rp);
+
+                       devc->total_samples += repetitions;
+
+                       write_u32le(sample_buff, sample_value);
+                       feed_queue_logic_submit(devc->feed_queue,
+                               sample_buff, repetitions);
+                       sr_sw_limits_update_samples_read(&devc->sw_limits,
+                               repetitions);
+
+                       if (devc->trigger_involved && !devc->trigger_marked) {
+                               if (!--devc->n_reps_until_trigger) {
+                                       feed_queue_logic_send_trigger(devc->feed_queue);
+                                       devc->trigger_marked = TRUE;
+                                       sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.",
+                                               devc->total_samples,
+                                               (double)devc->total_samples / devc->samplerate * 1e3);
+                               }
+                       }
+               }
+               (void)read_u8_inc(&rp); /* Skip sequence number. */
+       }
+
+       /*
+        * Check for several conditions which shall terminate the
+        * capture data download: When the amount of capture data in
+        * the device is exhausted. When the user specified samples
+        * count limit is reached.
+        */
+       if (!devc->n_bytes_to_read) {
+               devc->download_finished = TRUE;
+       } else {
+               sr_dbg("%" PRIu32 " more bytes to download from the device.",
+                       devc->n_bytes_to_read);
+       }
+       if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) {
+               sr_dbg("Acquisition limit reached.");
+               devc->download_finished = TRUE;
+       }
+       if (devc->download_finished) {
+               sr_dbg("Download finished, flushing session feed queue.");
+               feed_queue_logic_flush(devc->feed_queue);
+       }
+       sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples);
 }
 
-SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi)
+/*
+ * Process a chunk of capture data in streaming mode. The memory layout
+ * is rather different from "normal mode" (see the send_chunk() routine
+ * above). In streaming mode data is not compressed, and memory cells
+ * neither contain raw sampled pin values at a given point in time. The
+ * memory content needs transformation.
+ * - The memory content can be seen as a sequence of memory cells.
+ * - Each cell contains samples that correspond to the same channel.
+ *   The next cell contains samples for the next channel, etc.
+ * - Only enabled channels occupy memory cells. Disabled channels are
+ *   not part of the capture data memory layout.
+ * - The LSB bit position in a cell is the sample which was taken first
+ *   for this channel. Upper bit positions were taken later.
+ *
+ * Implementor's note: This routine is inspired by convert_sample_data()
+ * in the https://github.com/AlexUg/sigrok implementation. Which in turn
+ * appears to have been derived from the saleae-logic16 sigrok driver.
+ * The code is phrased conservatively to verify the layout as discussed
+ * above, performance was not a priority. Operation was verified with an
+ * LA2016 device. The memory layout of 32 channel models is yet to get
+ * determined.
+ */
+static void stream_data(struct sr_dev_inst *sdi,
+       const uint8_t *data_buffer, size_t data_length)
 {
        struct dev_context *devc;
-       uint16_t state;
-       uint8_t buf[8];
-       int16_t purchase_date_bcd[2];
-       uint8_t magic;
+       struct stream_state_t *stream;
+       size_t bit_count;
+       const uint8_t *rp;
+       uint32_t sample_value;
+       uint8_t sample_buff[sizeof(sample_value)];
+       size_t bit_idx;
+       uint32_t ch_mask;
+
+       devc = sdi->priv;
+       stream = &devc->stream;
+
+       /* Ignore incoming USB data after complete sample data download. */
+       if (devc->download_finished)
+               return;
+       sr_dbg("Stream mode, got another chunk: %p, length %zu.",
+               data_buffer, data_length);
+
+       /* TODO Add soft trigger support when in stream mode? */
+
+       /*
+        * TODO Are memory cells always as wide as the channel count?
+        * Are they always 16bits wide? Verify for 32 channel devices.
+        */
+       bit_count = devc->model->channel_count;
+       if (bit_count == 32) {
+               data_length /= sizeof(uint32_t);
+       } else if (bit_count == 16) {
+               data_length /= sizeof(uint16_t);
+       } else {
+               /*
+                * Unhandled case. Acquisition should not start.
+                * The statement silences the compiler.
+                */
+               return;
+       }
+       rp = data_buffer;
+       sample_value = 0;
+       while (data_length--) {
+               /* Get another entity. */
+               if (bit_count == 32)
+                       sample_value = read_u32le_inc(&rp);
+               else if (bit_count == 16)
+                       sample_value = read_u16le_inc(&rp);
+
+               /* Map the entity's bits to a channel's samples. */
+               ch_mask = stream->channel_masks[stream->channel_index];
+               for (bit_idx = 0; bit_idx < bit_count; bit_idx++) {
+                       if (sample_value & (1UL << bit_idx))
+                               stream->sample_data[bit_idx] |= ch_mask;
+               }
+
+               /*
+                * Advance to the next channel. Submit a block of
+                * samples when all channels' data was seen.
+                */
+               stream->channel_index++;
+               if (stream->channel_index != stream->enabled_count)
+                       continue;
+               for (bit_idx = 0; bit_idx < bit_count; bit_idx++) {
+                       sample_value = stream->sample_data[bit_idx];
+                       write_u32le(sample_buff, sample_value);
+                       feed_queue_logic_submit(devc->feed_queue, sample_buff, 1);
+               }
+               sr_sw_limits_update_samples_read(&devc->sw_limits, bit_count);
+               devc->total_samples += bit_count;
+               memset(stream->sample_data, 0, sizeof(stream->sample_data));
+               stream->channel_index = 0;
+       }
+
+       /*
+        * Need we count empty or failed USB transfers? This version
+        * doesn't, assumes that timeouts are perfectly legal because
+        * transfers are started early, and slow samplerates or trigger
+        * support in hardware are plausible causes for empty transfers.
+        *
+        * TODO Maybe a good condition would be (rather large) a timeout
+        * after a previous capture data chunk was seen? So that stalled
+        * streaming gets detected which _is_ an exceptional condition.
+        * We have observed these when "runmode" is set early but bulk
+        * transfers start late with a pause after setting the runmode.
+        */
+       if (sr_sw_limits_check(&devc->sw_limits)) {
+               sr_dbg("Acquisition end reached (sw limits).");
+               devc->download_finished = TRUE;
+       }
+       if (devc->download_finished) {
+               sr_dbg("Stream receive done, flushing session feed queue.");
+               feed_queue_logic_flush(devc->feed_queue);
+       }
+       sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples);
+}
+
+static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer)
+{
+       struct sr_dev_inst *sdi;
+       struct dev_context *devc;
+       gboolean was_cancelled, device_gone;
        int ret;
 
+       sdi = transfer->user_data;
        devc = sdi->priv;
 
-       /* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit
-        * complemented checksum; e.g. 2004DFFB = 2020-April.
-        * This helps to identify the age of devices if unknown magic numbers occur.
+       was_cancelled = transfer->status == LIBUSB_TRANSFER_CANCELLED;
+       device_gone = transfer->status == LIBUSB_TRANSFER_NO_DEVICE;
+       sr_dbg("receive_transfer(): status %s received %d bytes.",
+               libusb_error_name(transfer->status), transfer->actual_length);
+       if (device_gone) {
+               sr_warn("Lost communication to USB device.");
+               devc->download_finished = TRUE;
+               return;
+       }
+
+       /*
+        * Implementation detail: A USB transfer timeout is not fatal
+        * here. We just process whatever was received, empty input is
+        * perfectly acceptable. Reaching (or exceeding) the sw limits
+        * or exhausting the device's captured data will complete the
+        * sample data download.
         */
-       if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) {
-               sr_err("failed to read eeprom purchase_date_bcd");
+       if (devc->continuous)
+               stream_data(sdi, transfer->buffer, transfer->actual_length);
+       else
+               send_chunk(sdi, transfer->buffer, transfer->actual_length);
+
+       /*
+        * Re-submit completed transfers (regardless of timeout or
+        * data reception), unless the transfer was cancelled when
+        * the acquisition was terminated or has completed.
+        */
+       if (!was_cancelled && !devc->download_finished) {
+               ret = la2016_usbxfer_resubmit(sdi, transfer);
+               if (ret == SR_OK)
+                       return;
+               devc->download_finished = TRUE;
        }
-       else {
-               sr_dbg("purchase date: 20%02hx-%02hx", (purchase_date_bcd[0]) & 0x00ff, (purchase_date_bcd[0] >> 8) & 0x00ff);
-               if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) {
-                       sr_err("purchase date: checksum failure");
+}
+
+SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data)
+{
+       const struct sr_dev_inst *sdi;
+       struct dev_context *devc;
+       struct drv_context *drvc;
+       struct timeval tv;
+       int ret;
+
+       (void)fd;
+       (void)revents;
+
+       sdi = cb_data;
+       devc = sdi->priv;
+       drvc = sdi->driver->context;
+
+       /* Arrange for the start of stream mode when requested. */
+       if (devc->continuous && !devc->frame_begin_sent) {
+               sr_dbg("First receive callback in stream mode.");
+               devc->download_finished = FALSE;
+               devc->trigger_marked = FALSE;
+               devc->total_samples = 0;
+
+               std_session_send_df_frame_begin(sdi);
+               devc->frame_begin_sent = TRUE;
+
+               ret = set_run_mode(sdi, RUNMODE_RUN);
+               if (ret != SR_OK) {
+                       sr_err("Cannot set 'runmode' to 'run'.");
+                       return FALSE;
+               }
+
+               ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0);
+               if (ret != SR_OK) {
+                       sr_err("Cannot start USB bulk transfers.");
+                       return FALSE;
+               }
+               sr_dbg("Stream data reception initiated.");
+       }
+
+       /*
+        * Wait for the acquisition to complete in hardware.
+        * Periodically check a potentially configured msecs timeout.
+        */
+       if (!devc->continuous && !devc->completion_seen) {
+               if (!la2016_is_idle(sdi)) {
+                       if (sr_sw_limits_check(&devc->sw_limits)) {
+                               devc->sw_limits.limit_msec = 0;
+                               sr_dbg("Limit reached. Stopping acquisition.");
+                               la2016_stop_acquisition(sdi);
+                       }
+                       /* Not yet ready for sample data download. */
+                       return TRUE;
                }
+               sr_dbg("Acquisition completion seen (hardware).");
+               devc->sw_limits.limit_msec = 0;
+               devc->completion_seen = TRUE;
+               devc->download_finished = FALSE;
+               devc->trigger_marked = FALSE;
+               devc->total_samples = 0;
+
+               la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0);
+
+               /* Initiate the download of acquired sample data. */
+               std_session_send_df_frame_begin(sdi);
+               devc->frame_begin_sent = TRUE;
+               ret = la2016_start_download(sdi);
+               if (ret != SR_OK) {
+                       sr_err("Cannot start acquisition data download.");
+                       return FALSE;
+               }
+               sr_dbg("Acquisition data download started.");
+
+               return TRUE;
        }
 
+       /* Handle USB reception. Drives sample data download. */
+       memset(&tv, 0, sizeof(tv));
+       libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
+
        /*
-        * There are four known kingst logic analyser devices which use this same usb vid and pid:
-        * LA2016, LA1016 and the older revision of each of these. They all use the same hardware
-        * and the same FX2 mcu firmware but each requires a different fpga bitstream. They are
-        * differentiated by a 'magic' byte within the 8 bytes of EEPROM from address 0x08.
-        * For example;
+        * Periodically flush acquisition data in streaming mode.
+        * Without this nudge, previously received and accumulated data
+        * keeps sitting in queues and is not seen by applications.
+        */
+       if (devc->continuous && devc->stream.flush_period_ms) {
+               uint64_t now, elapsed;
+               now = g_get_monotonic_time();
+               if (!devc->stream.last_flushed)
+                       devc->stream.last_flushed = now;
+               elapsed = now - devc->stream.last_flushed;
+               elapsed /= 1000;
+               if (elapsed >= devc->stream.flush_period_ms) {
+                       sr_dbg("Stream mode, flushing.");
+                       feed_queue_logic_flush(devc->feed_queue);
+                       devc->stream.last_flushed = now;
+               }
+       }
+
+       /* Postprocess completion of sample data download. */
+       if (devc->download_finished) {
+               sr_dbg("Download finished, post processing.");
+
+               la2016_stop_acquisition(sdi);
+               usb_source_remove(sdi->session, drvc->sr_ctx);
+
+               la2016_usbxfer_cancel_all(sdi);
+               memset(&tv, 0, sizeof(tv));
+               libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
+
+               feed_queue_logic_flush(devc->feed_queue);
+               feed_queue_logic_free(devc->feed_queue);
+               devc->feed_queue = NULL;
+               if (devc->frame_begin_sent) {
+                       std_session_send_df_frame_end(sdi);
+                       devc->frame_begin_sent = FALSE;
+               }
+               std_session_send_df_end(sdi);
+
+               sr_dbg("Download finished, done post processing.");
+       }
+
+       return TRUE;
+}
+
+SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi,
+       gboolean show_message)
+{
+       struct dev_context *devc;
+       uint8_t buf[8]; /* Larger size of manuf date and device type magic. */
+       size_t rdoff, rdlen;
+       const uint8_t *rdptr;
+       uint8_t date_yy, date_mm;
+       uint8_t dinv_yy, dinv_mm;
+       uint8_t magic, magic2;
+       size_t model_idx;
+       const struct kingst_model *model;
+       int ret;
+
+       devc = sdi->priv;
+
+       /*
+        * Four EEPROM bytes at offset 0x20 are the manufacturing date,
+        * year and month in BCD format, followed by inverted values for
+        * consistency checks. For example bytes 20 04 df fb translate
+        * to 2020-04. This information can help identify the vintage of
+        * devices when unknown magic numbers are seen.
+        */
+       rdoff = 0x20;
+       rdlen = 4 * sizeof(uint8_t);
+       ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen);
+       if (ret != SR_OK && !show_message) {
+               /* Non-fatal weak attempt during probe. Not worth logging. */
+               sr_dbg("Cannot access EEPROM.");
+               return SR_ERR_IO;
+       } else if (ret != SR_OK) {
+               /* Failed attempt in regular use. Non-fatal. Worth logging. */
+               sr_err("Cannot read manufacture date in EEPROM.");
+       } else {
+               if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
+                       GString *txt;
+                       txt = sr_hexdump_new(buf, rdlen);
+                       sr_spew("Manufacture date bytes %s.", txt->str);
+                       sr_hexdump_free(txt);
+               }
+               rdptr = &buf[0];
+               date_yy = read_u8_inc(&rdptr);
+               date_mm = read_u8_inc(&rdptr);
+               dinv_yy = read_u8_inc(&rdptr);
+               dinv_mm = read_u8_inc(&rdptr);
+               sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm);
+               if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff)
+                       sr_warn("Manufacture date fails checksum test.");
+       }
+
+       /*
+        * Several Kingst logic analyzer devices share the same USB VID
+        * and PID. The product ID determines which MCU firmware to load.
+        * The MCU firmware provides access to EEPROM content which then
+        * allows to identify the device model. Which in turn determines
+        * which FPGA bitstream to load. Eight bytes at offset 0x08 are
+        * to get inspected.
         *
-        * magic=0x08
-        *  | ~magic=0xf7
-        *  | |
-        * 08F7000008F710EF
-        *          | |
-        *          | ~magic-backup
-        *          magic-backup
+        * EEPROM content for model identification is kept redundantly
+        * in memory. The values are stored in verbatim and in inverted
+        * form, multiple copies are kept at different offsets. Example
+        * data:
         *
-        * It seems that only these magic bytes are used, other bytes shown above are 'don't care'.
-        * Changing the magic byte on newer device to older magic causes OEM software to load
-        * the older fpga bitstream. The device then functions but has channels out of order.
-        * It's likely the bitstreams were changed to move input channel pins due to PCB changes.
+        *   magic 0x08
+        *    | ~magic 0xf7
+        *    | |
+        *   08f7000008f710ef
+        *            | |
+        *            | ~magic backup
+        *            magic backup
         *
-        * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others)
-        * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others)
-        * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream"
-        * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream"
+        * Exclusively inspecting the magic byte appears to be sufficient,
+        * other fields seem to be 'don't care'.
         *
-        * This was all determined by altering the eeprom contents of an LA2016 and LA1016 and observing
-        * the vendor software actions, either raising errors or loading specific bitstreams.
+        *   magic 2 == LA2016 using "kingst-la2016-fpga.bitstream"
+        *   magic 3 == LA1016 using "kingst-la1016-fpga.bitstream"
+        *   magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream"
+        *              (latest v1.3.0 PCB, perhaps others)
+        *   magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream"
+        *              (latest v1.3.0 PCB, perhaps others)
         *
-        * Note:
-        * An LA1016 cannot be converted to an LA2016 by changing the magic number - the bitstream
-        * will not authenticate with ic U10, which has different security coding for each device type.
+        * When EEPROM content does not match the hardware configuration
+        * (the board layout), the software may load but yield incorrect
+        * results (like swapped channels). The FPGA bitstream itself
+        * will authenticate with IC U10 and fail when its capabilities
+        * do not match the hardware model. An LA1016 won't become a
+        * LA2016 by faking its EEPROM content.
         */
-
-       if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) {
-               sr_err("failed to read eeprom device identifier bytes");
+       devc->identify_magic = 0;
+       rdoff = 0x08;
+       rdlen = 8 * sizeof(uint8_t);
+       ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen);
+       if (ret != SR_OK) {
+               sr_err("Cannot read EEPROM device identifier bytes.");
                return ret;
        }
-
+       if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
+               GString *txt;
+               txt = sr_hexdump_new(buf, rdlen);
+               sr_spew("EEPROM magic bytes %s.", txt->str);
+               sr_hexdump_free(txt);
+       }
        magic = 0;
-       if (buf[0] == (0x0ff & ~buf[1])) {
-               /* primary copy of magic passes complement check */
+       magic2 = 0;
+       if ((buf[0] ^ buf[1]) == 0xff && (buf[2] ^ buf[3]) == 0xff) {
+               /* Primary copy of magic passes complement check (4 bytes). */
                magic = buf[0];
-       }
-       else if (buf[4] == (0x0ff & ~buf[5])) {
-               /* backup copy of magic passes complement check */
-               sr_dbg("device_type: using backup copy of magic number");
+               magic2 = buf[2];
+               sr_dbg("Using primary magic %hhu (%hhu).", magic, magic2);
+       } else if ((buf[4] ^ buf[5]) == 0xff && (buf[6] ^ buf[7]) == 0xff) {
+               /* Backup copy of magic passes complement check (4 bytes). */
+               magic = buf[4];
+               magic2 = buf[6];
+               sr_dbg("Using secondary magic %hhu (%hhu).", magic, magic2);
+       } else if ((buf[0] ^ buf[1]) == 0xff) {
+               /* Primary copy of magic passes complement check (2 bytes). */
+               magic = buf[0];
+               sr_dbg("Using primary magic %hhu.", magic);
+       } else if ((buf[4] ^ buf[5]) == 0xff) {
+               /* Backup copy of magic passes complement check (2 bytes). */
                magic = buf[4];
+               sr_dbg("Using secondary magic %hhu.", magic);
+       } else {
+               sr_err("Cannot find consistent device type identification.");
        }
-
-       sr_dbg("device_type: magic number is %hhu", magic);
-
-       /* select the correct fpga bitstream for this device */
-       switch (magic) {
-       case 2:
-               ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016);
-               devc->max_samplerate = MAX_SAMPLE_RATE_LA2016;
-               break;
-       case 3:
-               ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016);
-               devc->max_samplerate = MAX_SAMPLE_RATE_LA1016;
-               break;
-       case 8:
-               ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A);
-               devc->max_samplerate = MAX_SAMPLE_RATE_LA2016;
-               break;
-       case 9:
-               ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016A);
-               devc->max_samplerate = MAX_SAMPLE_RATE_LA1016;
+       devc->identify_magic = magic;
+       devc->identify_magic2 = magic2;
+
+       devc->model = NULL;
+       for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) {
+               model = &models[model_idx];
+               if (model->magic != magic)
+                       continue;
+               if (model->magic2 && model->magic2 != magic2)
+                       continue;
+               devc->model = model;
+               sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.",
+                       model->name, model->channel_count,
+                       model->samplerate / SR_MHZ(1));
+               devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT,
+                       model->fpga_stem);
+               sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream);
+               if (!model->channel_count) {
+                       sr_warn("Device lacks logic channels. Not supported.");
+                       devc->model = NULL;
+               }
                break;
-       default:
-               sr_err("device_type: device not supported; magic number indicates this is not a LA2016 or LA1016");
-               return SR_ERR;
        }
+       if (!devc->model) {
+               sr_err("Cannot identify as one of the supported models.");
+               return SR_ERR_DATA;
+       }
+
+       return SR_OK;
+}
+
+SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi)
+{
+       struct dev_context *devc;
+       const char *bitstream_fn;
+       int ret;
+       uint16_t state;
+
+       devc = sdi->priv;
+       bitstream_fn = devc ? devc->fpga_bitstream : "";
 
+       ret = check_fpga_bitstream(sdi);
+       if (ret != SR_OK) {
+               ret = upload_fpga_bitstream(sdi, bitstream_fn);
+               if (ret != SR_OK) {
+                       sr_err("Cannot upload FPGA bitstream.");
+                       return ret;
+               }
+       }
+       ret = enable_fpga_bitstream(sdi);
        if (ret != SR_OK) {
-               sr_err("failed to upload fpga bitstream");
+               sr_err("Cannot enable FPGA bitstream after upload.");
                return ret;
        }
 
        state = run_state(sdi);
-       if (state != 0x85e9) {
-               sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state);
+       if ((state & 0xfff0) != 0x85e0) {
+               sr_warn("Unexpected run state, want 0x85eX, got 0x%04x.", state);
        }
 
-       if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
-               sr_err("failed to send CMD_BULK_RESET");
+       ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
+       if (ret != SR_OK) {
+               sr_err("Cannot reset USB bulk transfer.");
                return ret;
        }
 
-       sr_dbg("device should be initialized");
+       sr_dbg("Device should be initialized.");
 
-       return set_defaults(sdi);
+       return SR_OK;
 }
 
-SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi)
+SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi)
 {
        int ret;
 
-       if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) {
-               sr_err("failed to send deinit command");
+       ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0);
+       if (ret != SR_OK) {
+               sr_err("Cannot deinitialize device's FPGA.");
                return ret;
        }
 
        return SR_OK;
 }
+
+SR_PRIV void la2016_release_resources(const struct sr_dev_inst *sdi)
+{
+       (void)la2016_usbxfer_release(sdi);
+}
+
+SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
+{
+       return set_pwm_config(sdi, idx);
+}
index 09e12be6577d8739b860745a152f7f67648b0a4c..dd1092446d06d6db15fa1c19007615b465a3fe11 100644 (file)
@@ -1,6 +1,7 @@
 /*
  * This file is part of the libsigrok project.
  *
+ * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net>
  * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
  * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 #ifndef LIBSIGROK_HARDWARE_KINGST_LA2016_PROTOCOL_H
 #define LIBSIGROK_HARDWARE_KINGST_LA2016_PROTOCOL_H
 
-#include <stdint.h>
-#include <glib.h>
 #include <libsigrok/libsigrok.h>
-#include "libsigrok-internal.h"
+#include <stdint.h>
 
-#define LOG_PREFIX "kingst-la2016"
+#define LOG_PREFIX     "kingst-la2016"
 
 #define LA2016_VID             0x77a1
 #define LA2016_PID             0x01a2
+#define LA2016_IPRODUCT_INDEX  2
 #define USB_INTERFACE          0
 #define USB_CONFIGURATION      1
-
-#define LA2016_BULK_MAX         8388608
+#define USB_EP_FPGA_BITSTREAM  2
+#define USB_EP_CAPTURE_DATA    6
 
 /*
  * On Windows sigrok uses WinUSB RAW_IO policy which requires the
  * USB transfer buffer size to be a multiple of the endpoint max packet
- * size, which is 512 bytes in this case. Also, the maximum allowed size of
- * the transfer buffer is normally read from WinUSB_GetPipePolicy API but
- * libusb does not expose this function. Typically, max size is 2MB.
+ * size, which is 512 bytes in this case. Also, the maximum allowed size
+ * of the transfer buffer is normally read from WinUSB_GetPipePolicy API
+ * but libusb does not expose this function. Typically, max size is 2MB.
+ */
+#define LA2016_EP6_PKTSZ       512 /* Max packet size of USB endpoint 6. */
+#define LA2016_USB_BUFSZ       (512 * 1024) /* 512KiB buffer. */
+#define LA2016_USB_XFER_COUNT  8 /* Size of USB bulk transfers pool. */
+
+/* USB communication timeout during regular operation. */
+#define DEFAULT_TIMEOUT_MS     200
+#define CAPTURE_TIMEOUT_MS     500
+
+/*
+ * Check for MCU firmware to take effect after upload. Check the device
+ * presence for a maximum period of time, delay between checks in that
+ * phase. Allow for the device to vanish after upload and before checks,
+ * to not mistake its earlier incarnation for the successful operation
+ * of the most recently loaded firmware.
  */
-#define LA2016_EP6_PKTSZ       512 /* endpoint 6 max packet size */
-#define LA2016_USB_BUFSZ       (256 * 2 * LA2016_EP6_PKTSZ) /* 256KB buffer */
+#define RENUM_CHECK_PERIOD_MS  3000
+#define RENUM_GONE_DELAY_MS    1800
+#define RENUM_POLL_INTERVAL_MS 200
 
-#define MAX_RENUM_DELAY_MS     3000
-#define DEFAULT_TIMEOUT_MS      200
+/*
+ * The device expects some zero padding to follow the content of the
+ * file which contains the FPGA bitstream. Specify the chunk size here.
+ */
+#define LA2016_EP2_PADDING     4096
 
-#define LA2016_THR_VOLTAGE_MIN  0.40
-#define LA2016_THR_VOLTAGE_MAX  4.00
+/*
+ * Whether the logic input threshold voltage is a config item of the
+ * "Logic" channel group or a global config item of the device. Ideally
+ * it would be the former (being strictly related to the Logic channels)
+ * but mainline applications work better with the latter, and many other
+ * device drivers implement it that way, too.
+ */
+#define WITH_THRESHOLD_DEVCFG  1
 
-#define LA2016_NUM_SAMPLES_MIN  256
-#define LA2016_NUM_SAMPLES_MAX  (10UL * 1000 * 1000 * 1000)
+#define LA2016_THR_VOLTAGE_MIN 0.40
+#define LA2016_THR_VOLTAGE_MAX 4.00
 
-typedef struct pwm_setting_dev {
-       uint32_t period;
-       uint32_t duty;
-} pwm_setting_dev_t;
+/* Properties related to the layout of capture data downloads. */
+#define TRANSFER_PACKET_LENGTH 16
+#define LA2016_NUM_SAMPLES_MAX (UINT64_C(10 * 1000 * 1000 * 1000))
 
-typedef struct trigger_cfg {
-       uint32_t channels;
-       uint32_t enabled;
-       uint32_t level;
-       uint32_t high_or_falling;
-} trigger_cfg_t;
+/* Maximum device capabilities. May differ between models. */
+#define MAX_PWM_FREQ           SR_MHZ(20)
+#define PWM_CLOCK              SR_MHZ(200)     /* 200MHz for both LA2016 and LA1016 */
 
-typedef struct capture_info {
-       uint32_t n_rep_packets;
-       uint32_t n_rep_packets_before_trigger;
-       uint32_t write_pos;
-} capture_info_t;
+#define LA2016_NUM_PWMCH_MAX   2
 
-#define NUM_PACKETS_IN_CHUNK 5
-#define TRANSFER_PACKET_LENGTH 16
+/* Streaming mode related thresholds. Not enforced, used for warnings. */
+#define LA2016_STREAM_MBPS_MAX 200     /* In units of Mbps. */
+#define LA2016_STREAM_PUSH_THR 16      /* In units of Mbps. */
+#define LA2016_STREAM_PUSH_IVAL        250     /* In units of ms. */
 
-typedef struct pwm_setting {
-       uint8_t enabled;
-       float freq;
-       float duty;
-} pwm_setting_t;
+/*
+ * Whether to de-initialize the device hardware in the driver's close
+ * callback. It is desirable to e.g. configure PWM channels and leave
+ * the generator running after the application shuts down. Users can
+ * always disable channels on their way out if they want to.
+ */
+#define WITH_DEINIT_IN_CLOSE   0
+
+#define LA2016_CONVBUFFER_SIZE (4 * 1024 * 1024)
+
+struct kingst_model {
+       uint8_t magic, magic2;  /* EEPROM magic byte values. */
+       const char *name;       /* User perceived model name. */
+       const char *fpga_stem;  /* Bitstream filename stem. */
+       uint64_t samplerate;    /* Max samplerate in Hz. */
+       size_t channel_count;   /* Max channel count (16, 32). */
+       uint64_t memory_bits;   /* RAM capacity in Gbit (1, 2, 4). */
+       uint64_t baseclock;     /* Base clock to derive samplerate from. */
+};
 
 struct dev_context {
-       struct sr_context *ctx;
-
-       int64_t fw_updated;
-       pwm_setting_t pwm_setting[2];
-       unsigned int threshold_voltage_idx;
-       float threshold_voltage;
-       uint64_t max_samplerate;
-       uint64_t cur_samplerate;
-       uint64_t limit_samples;
+       uint16_t usb_pid;
+       char *mcu_firmware;
+       char *fpga_bitstream;
+       uint64_t fw_uploaded; /* Timestamp of most recent FW upload. */
+       uint8_t identify_magic, identify_magic2;
+       const struct kingst_model *model;
+       struct sr_channel_group *cg_logic, *cg_pwm;
+
+       /* User specified parameters. */
+       struct pwm_setting {
+               gboolean enabled;
+               float freq;
+               float duty;
+       } pwm_setting[LA2016_NUM_PWMCH_MAX];
+       size_t threshold_voltage_idx;
+       uint64_t samplerate;
+       struct sr_sw_limits sw_limits;
        uint64_t capture_ratio;
-       uint16_t cur_channels;
-       int num_channels;
-
-       uint32_t bitstream_size;
-
-       /* derived stuff */
-       uint64_t pre_trigger_size;
-
-       /* state after sampling */
-       int had_triggers_configured;
-       int have_trigger;
-       int transfer_finished;
-       capture_info_t info;
-       unsigned int n_transfer_packets_to_read; /* each with 5 acq packets */
-       unsigned int n_bytes_to_read;
-       unsigned int n_reps_until_trigger;
-       unsigned int reading_behind_trigger;
+       gboolean continuous;
+
+       /* Internal acquisition and download state. */
+       gboolean trigger_involved;
+       gboolean frame_begin_sent;
+       gboolean completion_seen;
+       gboolean download_finished;
+       uint32_t packets_per_chunk;
+       struct capture_info {
+               uint32_t n_rep_packets;
+               uint32_t n_rep_packets_before_trigger;
+               uint32_t write_pos;
+       } info;
+       uint32_t n_transfer_packets_to_read; /* each with 5 acq packets */
+       uint32_t n_bytes_to_read;
+       uint32_t n_reps_until_trigger;
+       gboolean trigger_marked;
        uint64_t total_samples;
        uint32_t read_pos;
 
-       unsigned int convbuffer_size;
-       uint8_t *convbuffer;
-       struct libusb_transfer *transfer;
+       struct feed_queue_logic *feed_queue;
+       GSList *transfers;
+       size_t transfer_bufsize;
+       struct stream_state_t {
+               size_t enabled_count;
+               uint32_t enabled_mask;
+               uint32_t channel_masks[32];
+               size_t channel_index;
+               uint32_t sample_data[32];
+               uint64_t flush_period_ms;
+               uint64_t last_flushed;
+       } stream;
 };
 
-SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id);
-SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi);
+SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi,
+       struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload);
+SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi,
+       gboolean show_message);
+SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi);
+SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi);
+SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx);
+SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi,
+       double voltage);
 SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi);
-SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi);
-SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi);
-SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb);
-SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi);
-SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi);
+SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data);
+SR_PRIV void la2016_release_resources(const struct sr_dev_inst *sdi);
 
 #endif
index a05ff618d5e4c8eeaa1877f6fc46b6ada7ac7875..8cc2bbd3b060c03b99f9fb49465c7fc5000848bd 100644 (file)
@@ -527,14 +527,9 @@ SR_PRIV int lecroy_xstream_init_device(struct sr_dev_inst *sdi)
                ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, channel_enabled,
                        (*scope_models[model_index].analog_names)[i]);
 
-               devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
-
-               devc->analog_groups[i]->name = g_strdup(
-                       (char *)(*scope_models[model_index].analog_names)[i]);
+               devc->analog_groups[i] = sr_channel_group_new(sdi,
+                       (*scope_models[model_index].analog_names)[i], NULL);
                devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
-
-               sdi->channel_groups = g_slist_append(sdi->channel_groups,
-                       devc->analog_groups[i]);
        }
 
        devc->model_config = &scope_models[model_index];
index 54444d623c6d1484bfbe31f3da3d99d512a91c33..20a922fa215177a139587c94121693ec6bac45a0 100644 (file)
@@ -145,9 +145,7 @@ static struct sr_dev_inst *probe_device(struct sr_modbus_dev_inst *modbus)
        sdi->driver = &maynuo_m97_driver_info;
        sdi->inst_type = SR_INST_MODBUS;
 
-       cg = g_malloc0(sizeof(struct sr_channel_group));
-       cg->name = g_strdup("1");
-       sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
+       cg = sr_channel_group_new(sdi, "1", NULL);
 
        ch = sr_channel_new(sdi, 0, SR_CHANNEL_ANALOG, TRUE, "V1");
        cg->channels = g_slist_append(cg->channels, ch);
index 4eb755d274d057e3eae731e378c8f815b9589e4e..d8a757283655496d10b9a2c2d26eed2c7c875694 100644 (file)
@@ -159,9 +159,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
                sdi->connection_id = g_strdup(conn);
 
                /* Create the logic channels group. */
-               cg = g_malloc0(sizeof(*cg));
-               sdi->channel_groups = g_slist_append(NULL, cg);
-               cg->name = g_strdup("Logic");
+               cg = sr_channel_group_new(sdi, "Logic", NULL);
                ch_count = ARRAY_SIZE(channel_names);
                for (ch_idx = 0; ch_idx < ch_count; ch_idx++) {
                        ch = sr_channel_new(sdi, ch_idx, SR_CHANNEL_LOGIC,
index 31bbfa43827f6c75fecb628bb461f093592fd51e..b29346ca1cbcab166b6e37d6210ed08b11bec310 100644 (file)
@@ -438,13 +438,9 @@ static GSList *do_scan(lps_modelid modelid, struct sr_dev_driver *drv, GSList *o
 
                devc->channel_status[cnt].info = g_slist_append(NULL, ch);
 
-               cg = g_malloc(sizeof(struct sr_channel_group));
                snprintf(channel, sizeof(channel), "CG%d", cnt + 1);
-               cg->name = g_strdup(channel);
-               cg->priv = NULL;
+               cg = sr_channel_group_new(sdi, channel, NULL);
                cg->channels = g_slist_append(NULL, ch);
-
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
        }
 
        /* Query status */
index 9ce2eb66e3a855337dc63f0bed452ba165f511f1..83090d86ac7c2253c6662a305b7beab10015df67 100644 (file)
@@ -132,7 +132,7 @@ static int rdtech_dps_set_reg(const struct sr_dev_inst *sdi,
        modbus = sdi->conn;
 
        wrptr = (void *)registers;
-       write_u16le(wrptr, value);
+       write_u16be(wrptr, value);
 
        g_mutex_lock(&devc->rw_mutex);
        ret = sr_modbus_write_multiple_registers(modbus, address,
@@ -187,8 +187,8 @@ SR_PRIV int rdtech_dps_get_model_version(struct sr_modbus_dev_inst *modbus,
                if (ret != SR_OK)
                        return ret;
                rdptr = (void *)registers;
-               *model = read_u16le_inc(&rdptr);
-               *version = read_u16le_inc(&rdptr);
+               *model = read_u16be_inc(&rdptr);
+               *version = read_u16be_inc(&rdptr);
                *serno = 0;
                sr_info("RDTech DPS/DPH model: %u version: %u",
                        *model, *version);
@@ -327,25 +327,25 @@ SR_PRIV int rdtech_dps_get_state(const struct sr_dev_inst *sdi,
 
                /* Interpret the registers' values. */
                rdptr = (const void *)registers;
-               uset_raw = read_u16le_inc(&rdptr);
+               uset_raw = read_u16be_inc(&rdptr);
                volt_target = uset_raw / devc->voltage_multiplier;
-               iset_raw = read_u16le_inc(&rdptr);
+               iset_raw = read_u16be_inc(&rdptr);
                curr_limit = iset_raw / devc->current_multiplier;
-               uout_raw = read_u16le_inc(&rdptr);
+               uout_raw = read_u16be_inc(&rdptr);
                curr_voltage = uout_raw / devc->voltage_multiplier;
-               iout_raw = read_u16le_inc(&rdptr);
+               iout_raw = read_u16be_inc(&rdptr);
                curr_current = iout_raw / devc->current_multiplier;
-               power_raw = read_u16le_inc(&rdptr);
+               power_raw = read_u16be_inc(&rdptr);
                curr_power = power_raw / 100.0f;
-               (void)read_u16le_inc(&rdptr); /* UIN */
-               reg_val = read_u16le_inc(&rdptr); /* LOCK */
+               (void)read_u16be_inc(&rdptr); /* UIN */
+               reg_val = read_u16be_inc(&rdptr); /* LOCK */
                is_lock = reg_val != 0;
-               reg_val = read_u16le_inc(&rdptr); /* PROTECT */
+               reg_val = read_u16be_inc(&rdptr); /* PROTECT */
                uses_ovp = reg_val == STATE_OVP;
                uses_ocp = reg_val == STATE_OCP;
-               reg_state = read_u16le_inc(&rdptr); /* CV_CC */
+               reg_state = read_u16be_inc(&rdptr); /* CV_CC */
                is_reg_cc = reg_state == MODE_CC;
-               out_state = read_u16le_inc(&rdptr); /* ENABLE */
+               out_state = read_u16be_inc(&rdptr); /* ENABLE */
                is_out_enabled = out_state != 0;
 
                /* Transfer another chunk of registers in a single call. */
@@ -358,9 +358,9 @@ SR_PRIV int rdtech_dps_get_state(const struct sr_dev_inst *sdi,
 
                /* Interpret the second registers chunk's values. */
                rdptr = (const void *)registers;
-               ovpset_raw = read_u16le_inc(&rdptr); /* PRE OVPSET */
+               ovpset_raw = read_u16be_inc(&rdptr); /* PRE OVPSET */
                ovp_threshold = ovpset_raw * devc->voltage_multiplier;
-               ocpset_raw = read_u16le_inc(&rdptr); /* PRE OCPSET */
+               ocpset_raw = read_u16be_inc(&rdptr); /* PRE OCPSET */
                ocp_threshold = ocpset_raw * devc->current_multiplier;
 
                break;
index e8a3aadc8acd4ea2fd8edaa2824bb114abb42f31..a173243264576e2a0ff6e8859d03e240f464f080 100644 (file)
@@ -380,12 +380,9 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
        for (i = 0; i < device->num_channels; i++) {
                ch = sr_channel_new(sdi, ch_idx++, SR_CHANNEL_ANALOG, TRUE,
                                device->channels[i].name);
-               cg = g_malloc0(sizeof(*cg));
                snprintf(tmp, sizeof(tmp), "%u", i + 1);
-               cg->name = g_strdup(tmp);
+               cg = sr_channel_group_new(sdi, tmp, NULL);
                cg->channels = g_slist_append(cg->channels, ch);
-
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
        }
 
        /* Create channels for the frequency counter output. */
index 632c95963cb75e517e6d7abe3cbff783e6cbee70..aab4730265d892e4d158cf0ed9d233452495567e 100644 (file)
@@ -395,17 +395,13 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
                channel_name = g_strdup_printf("CH%d", i + 1);
                ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel_name);
 
-               devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
-
-               devc->analog_groups[i]->name = channel_name;
+               devc->analog_groups[i] = sr_channel_group_new(sdi,
+                       channel_name, NULL);
                devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
-               sdi->channel_groups = g_slist_append(sdi->channel_groups,
-                               devc->analog_groups[i]);
        }
 
        if (devc->model->has_digital) {
-               devc->digital_group = g_malloc0(sizeof(struct sr_channel_group));
-
+               devc->digital_group = sr_channel_group_new(sdi, "LA", NULL);
                for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
                        channel_name = g_strdup_printf("D%d", i);
                        ch = sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_name);
@@ -413,9 +409,6 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
                        devc->digital_group->channels = g_slist_append(
                                        devc->digital_group->channels, ch);
                }
-               devc->digital_group->name = g_strdup("LA");
-               sdi->channel_groups = g_slist_append(sdi->channel_groups,
-                               devc->digital_group);
        }
 
        for (i = 0; i < ARRAY_SIZE(timebases); i++) {
index aa5b945a3349cee0573491709d304efa424ccdc7..bd11f082ae78709fe1b36b8cec1545a28fbadfe5 100644 (file)
@@ -145,8 +145,7 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi,
 
        for (i = 0; i < num_channel_groups; i++) {
                cgs = &channel_groups[i];
-               cg = g_malloc0(sizeof(struct sr_channel_group));
-               cg->name = g_strdup(cgs->name);
+               cg = sr_channel_group_new(sdi, cgs->name, NULL);
                for (j = 0, mask = 1; j < 64; j++, mask <<= 1) {
                        if (cgs->channel_index_mask & mask) {
                                for (l = sdi->channels; l; l = l->next) {
@@ -167,7 +166,6 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi,
                pcg = g_malloc0(sizeof(struct pps_channel_group));
                pcg->features = cgs->features;
                cg->priv = pcg;
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
        }
 
        sr_scpi_hw_info_free(hw_info);
index 846399b678c4a8a3af56864e99ffbf27173b9d87..76955e6da058c211a173b36cfd5beebf40a2bed4 100644 (file)
@@ -305,17 +305,13 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
                channel_name = g_strdup_printf("CH%d", i + 1);
                ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel_name);
 
-               devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
-
-               devc->analog_groups[i]->name = channel_name;
+               devc->analog_groups[i] = sr_channel_group_new(sdi,
+                       channel_name, NULL);
                devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
-               sdi->channel_groups = g_slist_append(sdi->channel_groups,
-                       devc->analog_groups[i]);
        }
 
        if (devc->model->has_digital) {
-               devc->digital_group = g_malloc0(sizeof(struct sr_channel_group));
-
+               devc->digital_group = sr_channel_group_new(sdi, "LA", NULL);
                for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
                        channel_name = g_strdup_printf("D%d", i);
                        ch = sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_name);
@@ -323,9 +319,6 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
                        devc->digital_group->channels = g_slist_append(
                                devc->digital_group->channels, ch);
                }
-               devc->digital_group->name = g_strdup("LA");
-               sdi->channel_groups = g_slist_append(sdi->channel_groups,
-                       devc->digital_group);
        }
 
        for (i = 0; i < ARRAY_SIZE(timebases); i++) {
index d2c51cdac6d4f5ebfebaf61c02c66dfef262d9cb..06dae50f7cd9a3979692371138df4ad8b91b3f0b 100644 (file)
@@ -790,24 +790,17 @@ SR_PRIV int dlm_device_init(struct sr_dev_inst *sdi, int model_index)
                ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE,
                                (*scope_models[model_index].analog_names)[i]);
 
-               devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
-
-               devc->analog_groups[i]->name = g_strdup(
-                               (char *)(*scope_models[model_index].analog_names)[i]);
+               devc->analog_groups[i] = sr_channel_group_new(sdi,
+                       (*scope_models[model_index].analog_names)[i], NULL);
                devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
-
-               sdi->channel_groups = g_slist_append(sdi->channel_groups,
-                               devc->analog_groups[i]);
        }
 
        /* Add digital channel groups. */
        for (i = 0; i < scope_models[model_index].pods; i++) {
-               devc->digital_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
+               devc->digital_groups[i] = sr_channel_group_new(sdi, NULL, NULL);
                if (!devc->digital_groups[i])
                        return SR_ERR_MALLOC;
                devc->digital_groups[i]->name = g_strdup_printf("POD%d", i);
-               sdi->channel_groups = g_slist_append(sdi->channel_groups,
-                               devc->digital_groups[i]);
        }
 
        /* Add digital channels. */
index b5de532bc58a1c25a4d3430d223a8b5b8ee7299b..c4957e7656a957d84379262e847f95663837435d 100644 (file)
@@ -173,7 +173,7 @@ SR_API const char *const *sr_input_extensions_get(
  *
  * @since 0.4.0
  */
-SR_API const struct sr_input_module *sr_input_find(char *id)
+SR_API const struct sr_input_module *sr_input_find(const char *id)
 {
        int i;
 
index 354330ab453e9f800d5926cc2df081a59906e3c2..ea4cb39b252bb406aaf31bcb4a343128ed2dab9b 100644 (file)
 #include <libsigrok/libsigrok.h>
 #include "libsigrok-internal.h"
 
-/* TODO: Move these helpers to some library API routine group. */
-struct sr_channel_group *sr_channel_group_new(const char *name, void *priv);
-void sr_channel_group_free(struct sr_channel_group *cg);
-
 #define LOG_PREFIX     "input/logicport"
 
 #define MAX_CHANNELS   34
@@ -155,26 +151,6 @@ static void free_signal_group(struct signal_group_desc *desc)
        g_free(desc);
 }
 
-struct sr_channel_group *sr_channel_group_new(const char *name, void *priv)
-{
-       struct sr_channel_group *cg;
-
-       cg = g_malloc0(sizeof(*cg));
-       if (name && *name)
-               cg->name = g_strdup(name);
-       cg->priv = priv;
-
-       return cg;
-}
-
-void sr_channel_group_free(struct sr_channel_group *cg)
-{
-       if (!cg)
-               return;
-       g_free(cg->name);
-       g_slist_free(cg->channels);
-}
-
 /* Wrapper for GDestroyNotify compatibility. */
 static void sg_free(void *p)
 {
@@ -802,10 +778,9 @@ static int create_channels_groups(struct sr_input *in)
        sdi = in->sdi;
        for (l = inc->signal_groups; l; l = l->next) {
                desc = l->data;
-               cg = sr_channel_group_new(desc->name, NULL);
+               cg = sr_channel_group_new(sdi, desc->name, NULL);
                if (!cg)
                        return SR_ERR_MALLOC;
-               sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
                mask = UINT64_C(1);
                for (idx = 0; idx < inc->channel_count; idx++, mask <<= 1) {
                        if (!(desc->mask & mask))
index 413712301318787f7201f9389de5748418dbfbeb..acd30e5d7f05ae91420453b221f7b4176d111a69 100644 (file)
@@ -205,15 +205,6 @@ static void free_channel(void *data)
        g_free(vcd_ch);
 }
 
-/* TODO Drop the local decl when this has become a common helper. */
-void sr_channel_group_free(struct sr_channel_group *cg);
-
-/* Wrapper for GDestroyNotify compatibility. */
-static void cg_free(void *p)
-{
-       sr_channel_group_free(p);
-}
-
 /*
  * Another timestamp delta was observed, update statistics: Update the
  * sorted list of minimum values, and increment the occurance counter.
@@ -1074,10 +1065,8 @@ static void create_channels(const struct sr_input *in,
                if (vcd_ch->type != ch_type)
                        continue;
                cg = NULL;
-               if (vcd_ch->size != 1) {
-                       cg = g_malloc0(sizeof(*cg));
-                       cg->name = g_strdup(vcd_ch->name);
-               }
+               if (vcd_ch->size != 1)
+                       cg = sr_channel_group_new(sdi, vcd_ch->name, NULL);
                for (size_idx = 0; size_idx < vcd_ch->size; size_idx++) {
                        ch_name = get_channel_name(vcd_ch, size_idx);
                        sr_dbg("sigrok channel idx %zu, name %s, type %s, en %d.",
@@ -1089,8 +1078,6 @@ static void create_channels(const struct sr_input *in,
                        if (cg)
                                cg->channels = g_slist_append(cg->channels, ch);
                }
-               if (cg)
-                       sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
        }
 }
 
@@ -1135,7 +1122,7 @@ static void keep_header_for_reread(const struct sr_input *in)
 
        inc = in->priv;
 
-       g_slist_free_full(inc->prev.sr_groups, cg_free);
+       g_slist_free_full(inc->prev.sr_groups, sr_channel_group_free_cb);
        inc->prev.sr_groups = in->sdi->channel_groups;
        in->sdi->channel_groups = NULL;
 
@@ -1174,7 +1161,7 @@ static gboolean check_header_in_reread(const struct sr_input *in)
                return FALSE;
        }
 
-       g_slist_free_full(in->sdi->channel_groups, cg_free);
+       g_slist_free_full(in->sdi->channel_groups, sr_channel_group_free_cb);
        in->sdi->channel_groups = inc->prev.sr_groups;
        inc->prev.sr_groups = NULL;
 
index a2350e02ddf3aed2c48c89bcab2ac8eb8f59dfae..db74dcc27e515f04b364c9425b9c5b48a5cb7f9a 100644 (file)
@@ -450,6 +450,19 @@ static inline void write_u16le(uint8_t *p, uint16_t x)
 }
 #define WL16(p, x) write_u16le((uint8_t *)(p), (uint16_t)(x))
 
+/**
+ * Write a 24 bits unsigned integer to memory stored as little endian.
+ * @param p a pointer to the output memory
+ * @param x the input unsigned integer
+ */
+static inline void write_u24le(uint8_t *p, uint32_t x)
+{
+       p[0] = x & 0xff; x >>= 8;
+       p[1] = x & 0xff; x >>= 8;
+       p[2] = x & 0xff; x >>= 8;
+}
+#define WL24(p, x) write_u24le((uint8_t *)(p), (uint32_t)(x))
+
 /**
  * Write a 32 bits unsigned integer to memory stored as big endian.
  * @param p a pointer to the output memory
@@ -478,6 +491,21 @@ static inline void write_u32le(uint8_t *p, uint32_t x)
 }
 #define WL32(p, x) write_u32le((uint8_t *)(p), (uint32_t)(x))
 
+/**
+ * Write a 40 bits unsigned integer to memory stored as little endian.
+ * @param p a pointer to the output memory
+ * @param x the input unsigned integer
+ */
+static inline void write_u40le(uint8_t *p, uint64_t x)
+{
+       p[0] = x & 0xff; x >>= 8;
+       p[1] = x & 0xff; x >>= 8;
+       p[2] = x & 0xff; x >>= 8;
+       p[3] = x & 0xff; x >>= 8;
+       p[4] = x & 0xff; x >>= 8;
+}
+#define WL40(p, x) write_u40le((uint8_t *)(p), (uint64_t)(x))
+
 /**
  * Write a 48 bits unsigned integer to memory stored as little endian.
  * @param p a pointer to the output memory
@@ -898,6 +926,19 @@ static inline void write_u16le_inc(uint8_t **p, uint16_t x)
        *p += sizeof(x);
 }
 
+/**
+ * Write unsigned 24bit liggle endian integer to raw memory, increment write position.
+ * @param[in, out] p Pointer into byte stream.
+ * @param[in] x Value to write.
+ */
+static inline void write_u24le_inc(uint8_t **p, uint32_t x)
+{
+       if (!p || !*p)
+               return;
+       write_u24le(*p, x);
+       *p += 3 * sizeof(uint8_t);
+}
+
 /**
  * Write unsigned 32bit big endian integer to raw memory, increment write position.
  * @param[in, out] p Pointer into byte stream.
@@ -924,6 +965,19 @@ static inline void write_u32le_inc(uint8_t **p, uint32_t x)
        *p += sizeof(x);
 }
 
+/**
+ * Write unsigned 40bit little endian integer to raw memory, increment write position.
+ * @param[in, out] p Pointer into byte stream.
+ * @param[in] x Value to write.
+ */
+static inline void write_u40le_inc(uint8_t **p, uint64_t x)
+{
+       if (!p || !*p)
+               return;
+       write_u40le(*p, x);
+       *p += 5 * sizeof(uint8_t);
+}
+
 /**
  * Write unsigned 48bit little endian integer to raw memory, increment write position.
  * @param[in, out] p Pointer into byte stream.
@@ -1591,6 +1645,11 @@ SR_PRIV struct sr_channel *sr_next_enabled_channel(const struct sr_dev_inst *sdi
 SR_PRIV gboolean sr_channels_differ(struct sr_channel *ch1, struct sr_channel *ch2);
 SR_PRIV gboolean sr_channel_lists_differ(GSList *l1, GSList *l2);
 
+SR_PRIV struct sr_channel_group *sr_channel_group_new(struct sr_dev_inst *sdi,
+       const char *name, void *priv);
+SR_PRIV void sr_channel_group_free(struct sr_channel_group *cg);
+SR_PRIV void sr_channel_group_free_cb(void *cg);
+
 /** Device instance data */
 struct sr_dev_inst {
        /** Device driver. */
@@ -1629,6 +1688,7 @@ SR_PRIV void sr_dev_inst_free(struct sr_dev_inst *sdi);
 SR_PRIV struct sr_usb_dev_inst *sr_usb_dev_inst_new(uint8_t bus,
                uint8_t address, struct libusb_device_handle *hdl);
 SR_PRIV void sr_usb_dev_inst_free(struct sr_usb_dev_inst *usb);
+SR_PRIV void sr_usb_dev_inst_free_cb(gpointer p); /* Glib wrapper. */
 #endif
 
 #ifdef HAVE_SERIAL_COMM
index 81f269fa92dc26ee73b9ca90081dc27039d010d9..959d0005680c5d2ebad6abb1637ca28a9221f035 100644 (file)
--- a/src/std.c
+++ b/src/std.c
@@ -605,7 +605,8 @@ SR_PRIV GVariant *std_gvar_tuple_array(const uint64_t a[][2], unsigned int n)
                rational[1] = g_variant_new_uint64(a[i][1]);
 
                /* FIXME: Valgrind reports a memory leak here. */
-               g_variant_builder_add_value(&gvb, g_variant_new_tuple(rational, 2));
+               g_variant_builder_add_value(&gvb, g_variant_new_tuple(rational,
+                       ARRAY_SIZE(rational)));
        }
 
        return g_variant_builder_end(&gvb);
@@ -624,7 +625,8 @@ SR_PRIV GVariant *std_gvar_tuple_rational(const struct sr_rational *r, unsigned
                rational[1] = g_variant_new_uint64(r[i].q);
 
                /* FIXME: Valgrind reports a memory leak here. */
-               g_variant_builder_add_value(&gvb, g_variant_new_tuple(rational, 2));
+               g_variant_builder_add_value(&gvb, g_variant_new_tuple(rational,
+                       ARRAY_SIZE(rational)));
        }
 
        return g_variant_builder_end(&gvb);
@@ -687,17 +689,17 @@ SR_PRIV GVariant *std_gvar_min_max_step_thresholds(const double min, const doubl
 
        g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
 
-       for (d = min; d <= max; d += step) {
+       for (d = min; d <= max + step / 2.0; d += step) {
                /*
                 * We will never see exactly 0.0 because of the error we're
                 * accumulating, so catch the "zero" value and force it to be 0.
                 */
-               v = ((d > (-step / 2)) && (d < (step / 2))) ? 0 : d;
+               v = ((d > (-step / 2.0)) && (d < (step / 2.0))) ? 0 : d;
 
                range[0] = g_variant_new_double(v);
                range[1] = g_variant_new_double(v);
 
-               gvar = g_variant_new_tuple(range, 2);
+               gvar = g_variant_new_tuple(range, ARRAY_SIZE(range));
                g_variant_builder_add_value(&gvb, gvar);
        }
 
@@ -711,7 +713,7 @@ SR_PRIV GVariant *std_gvar_tuple_u64(uint64_t low, uint64_t high)
        range[0] = g_variant_new_uint64(low);
        range[1] = g_variant_new_uint64(high);
 
-       return g_variant_new_tuple(range, 2);
+       return g_variant_new_tuple(range, ARRAY_SIZE(range));
 }
 
 SR_PRIV GVariant *std_gvar_tuple_double(double low, double high)
@@ -721,7 +723,7 @@ SR_PRIV GVariant *std_gvar_tuple_double(double low, double high)
        range[0] = g_variant_new_double(low);
        range[1] = g_variant_new_double(high);
 
-       return g_variant_new_tuple(range, 2);
+       return g_variant_new_tuple(range, ARRAY_SIZE(range));
 }
 
 SR_PRIV GVariant *std_gvar_array_i32(const int32_t a[], unsigned int n)
@@ -770,7 +772,7 @@ SR_PRIV GVariant *std_gvar_thresholds(const double a[][2], unsigned int n)
        for (i = 0; i < n; i++) {
                range[0] = g_variant_new_double(a[i][0]);
                range[1] = g_variant_new_double(a[i][1]);
-               gvar = g_variant_new_tuple(range, 2);
+               gvar = g_variant_new_tuple(range, ARRAY_SIZE(range));
                g_variant_builder_add_value(&gvb, gvar);
        }
 
index 8490bf9fca2a14e90cb4e04eb4f2f72fc5a9ddb3..904f0cea2fa57ab20aa7bfe4ac56b9f133328944 100644 (file)
@@ -598,7 +598,7 @@ END_TEST
 
 START_TEST(test_mult_rational)
 {
-       const struct sr_rational r[][3] = {
+       static const struct sr_rational r[][3] = {
                /*   a    *    b    =    c   */
                { { 1, 1 }, { 1, 1 }, { 1, 1 }},
                { { 2, 1 }, { 3, 1 }, { 6, 1 }},
@@ -625,13 +625,15 @@ START_TEST(test_mult_rational)
                { { 10000*3, 4 }, { -80000*3, 1 }, { -200000000*9, 1 }},
        };
 
-       for (unsigned i = 0; i < ARRAY_SIZE(r); i++) {
-               struct sr_rational res;
+       size_t i;
+       struct sr_rational res;
+       int rc;
 
-               int rc = sr_rational_mult(&res, &r[i][0], &r[i][1]);
+       for (i = 0; i < ARRAY_SIZE(r); i++) {
+               rc = sr_rational_mult(&res, &r[i][0], &r[i][1]);
                fail_unless(rc == SR_OK);
                fail_unless(sr_rational_eq(&res, &r[i][2]) == 1,
-                       "sr_rational_mult() failed: [%d] %ld/%lu != %ld/%lu.",
+                       "sr_rational_mult() failed: [%zu] %" PRIi64 "/%" PRIu64 " != %" PRIi64 "/%" PRIu64 ".",
                        i, res.p, res.q, r[i][2].p, r[i][2].q);
        }
 }
@@ -639,7 +641,7 @@ END_TEST
 
 START_TEST(test_div_rational)
 {
-       const struct sr_rational r[][3] = {
+       static const struct sr_rational r[][3] = {
                /*   a    *    b    =    c   */
                { { 1, 1 }, { 1, 1 }, { 1, 1 }},
                { { 2, 1 }, { 1, 3 }, { 6, 1 }},
@@ -662,19 +664,20 @@ START_TEST(test_div_rational)
                { { 10000*3, 4 }, { -1, 80000*3 }, { -200000000*9, 1 }},
        };
 
-       for (unsigned i = 0; i < ARRAY_SIZE(r); i++) {
-               struct sr_rational res;
+       size_t i;
+       struct sr_rational res;
+       int rc;
 
-               int rc = sr_rational_div(&res, &r[i][0], &r[i][1]);
+       for (i = 0; i < ARRAY_SIZE(r); i++) {
+               rc = sr_rational_div(&res, &r[i][0], &r[i][1]);
                fail_unless(rc == SR_OK);
                fail_unless(sr_rational_eq(&res, &r[i][2]) == 1,
-                       "sr_rational_mult() failed: [%d] %ld/%lu != %ld/%lu.",
+                       "sr_rational_mult() failed: [%zu] %" PRIi64 "/%" PRIu64 " != %" PRIi64 "/%" PRIu64 ".",
                        i, res.p, res.q, r[i][2].p, r[i][2].q);
        }
 
        {
-               struct sr_rational res;
-               int rc = sr_rational_div(&res, &r[0][0], &((struct sr_rational){ 0, 5 }));
+               rc = sr_rational_div(&res, &r[0][0], &((struct sr_rational){ 0, 5 }));
 
                fail_unless(rc == SR_ERR_ARG);
        }
index 5ef0bab110397914249d85c29fa4e84bc8aa9c74..551365e2a40fc98f62a544c18a3a9752e9cab8fa 100644 (file)
@@ -228,6 +228,13 @@ START_TEST(test_endian_write_inc)
        l = p - &buff[0];
        fail_unless(l == 4 * 48 / 8 * sizeof(uint8_t));
        fail_unless(memcmp(&buff[0], &buff1234large[0], l) == 0);
+
+       p = &buff[0];
+       write_u24le_inc(&p, 0xfe030201);
+       write_u40le_inc(&p, 0xdcba0807060504ul);
+       l = p - &buff[0];
+       fail_unless(l == 24 / 8 + 40 / 8);
+       fail_unless(memcmp(&buff[0], &buff1234large[0], l) == 0);
 }
 END_TEST
 
index ec2233329b769c5eecc9597bdeb6d8e7564f4694..f4bbe9ec64537987d84290e0d7369ad166561eff 100644 (file)
@@ -121,7 +121,7 @@ static void test_rational(const char *input, struct sr_rational expected)
        fail_unless(ret == SR_OK, "Unexpected rc for '%s': %d, errno %d.",
                input, ret, errno);
        fail_unless((expected.p == rational.p) && (expected.q == rational.q),
-                   "Invalid result for '%s': %ld/%ld'.",
+                   "Invalid result for '%s': %" PRIi64 "/%" PRIu64 "'.",
                    input, rational.p, rational.q);
 }