kingst-la2016: spew pretty FPGA register dump for development support

kingst-la2016: spew pretty FPGA register dump for development support

Implement a pretty registers dump, and call it when the FPGA bitstream
content gets checked and when hardware controlled acquisition completes.
Generate this FPGA registers dump at spew log level, accept a caller
provided address range to further reduce verbosity as needed.

This is mostly motivated by developer's curiousity. To suport research
when previously unknown models are seen. Or to see which other details
are available as an acquisition executes. Or to check whether some of
the previously written configuration could be read back.