X-Git-Url: https://sigrok.org/gitweb/?p=libsigrok.git;a=blobdiff_plain;f=src%2Fhardware%2Fsaleae-logic16%2Fprotocol.h;fp=src%2Fhardware%2Fsaleae-logic16%2Fprotocol.h;h=0cadd359517fc043f3fd9c4f35acd06b671de1be;hp=75a2089939968d4fab23c5fa094ad67b14fa91b2;hb=c86813962979777f53432e7e3392b1d2f2b661b4;hpb=da005885c8ebbf98772f75126764f758b2640d11

diff --git a/src/hardware/saleae-logic16/protocol.h b/src/hardware/saleae-logic16/protocol.h
index 75a20899..0cadd359 100644
--- a/src/hardware/saleae-logic16/protocol.h
+++ b/src/hardware/saleae-logic16/protocol.h
@@ -37,6 +37,7 @@ enum voltage_range {
 
 enum fpga_variant {
 	FPGA_VARIANT_ORIGINAL,
+	FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM,
 	FPGA_VARIANT_MCUPRO    /* mcupro clone v4.6 with Actel FPGA */
 };
 
@@ -90,6 +91,10 @@ struct dev_context {
 	unsigned int num_transfers;
 	struct libusb_transfer **transfers;
 	struct sr_context *ctx;
+
+	const uint8_t *fpga_register_map;
+	const uint8_t *fpga_status_control_bit_map;
+	const uint8_t *fpga_mode_bit_map;
 };
 
 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,