X-Git-Url: https://sigrok.org/gitweb/?p=libsigrok.git;a=blobdiff_plain;f=src%2Fhardware%2Fsaleae-logic16%2Fprotocol.c;h=36a688da462c3254c0bf3861292469786f3bb794;hp=7e4cb919c496f5ad16ee51ae5c8bf765a1e04c83;hb=84ab9da11fc9c1c90667f0e234423d4d306580dd;hpb=c86813962979777f53432e7e3392b1d2f2b661b4

diff --git a/src/hardware/saleae-logic16/protocol.c b/src/hardware/saleae-logic16/protocol.c
index 7e4cb919..36a688da 100644
--- a/src/hardware/saleae-logic16/protocol.c
+++ b/src/hardware/saleae-logic16/protocol.c
@@ -363,10 +363,13 @@ static int setup_register_mapping(const struct sr_dev_inst *sdi)
 		if ((ret = read_fpga_register(sdi, 7 /* No mapping */, &reg7)) != SR_OK)
 			return ret;
 
-		if (reg0 == 0 && reg7 > 0x10)
+		if (reg0 == 0 && reg7 > 0x10) {
+			sr_info("Original Saleae Logic16 using new bitstream.");
 			devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM;
-		else
+		} else {
+			sr_info("Original Saleae Logic16 using old bitstream.");
 			devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
+		}
 	}
 
 	if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) {