X-Git-Url: https://sigrok.org/gitweb/?p=libsigrok.git;a=blobdiff_plain;f=src%2Fhardware%2Fopenbench-logic-sniffer%2Fapi.c;h=5e74a5236e745b56de2bfde26e3baa8ebebf212f;hp=c04595350c6bcc562e978a65940c6eadb63c9176;hb=b853eb76fbee3c03d64c03b1cb8af0585684dfcf;hpb=244995a2e3cef0f971e21faf82531e785e552f9e

diff --git a/src/hardware/openbench-logic-sniffer/api.c b/src/hardware/openbench-logic-sniffer/api.c
index c0459535..5e74a523 100644
--- a/src/hardware/openbench-logic-sniffer/api.c
+++ b/src/hardware/openbench-logic-sniffer/api.c
@@ -473,6 +473,14 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 		return SR_ERR;
 	}
 	if (devc->num_stages > 0) {
+		/*
+		 * According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf
+		 * reset command must be send prior each arm command
+		 */
+		sr_dbg("Send reset command before trigger configure");
+		if (ols_send_reset(serial) != SR_OK)
+			return SR_ERR;
+
 		delaycount = readcount * (1 - devc->capture_ratio / 100.0);
 		devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
 		for (i = 0; i <= devc->num_stages; i++) {