X-Git-Url: https://sigrok.org/gitweb/?p=libsigrok.git;a=blobdiff_plain;f=src%2Fhardware%2Fasix-sigma%2Fprotocol.h;h=2410b3b69e13d5b77dc6e70bb125e005be2c6e23;hp=388b44bc9f659e0b96838dce8f35fda368781357;hb=7c41c420aa51b07e7381df5132da27228e9a56bd;hpb=13262b48c181ae380e2029982197649cb6343b9f diff --git a/src/hardware/asix-sigma/protocol.h b/src/hardware/asix-sigma/protocol.h index 388b44bc..2410b3b6 100644 --- a/src/hardware/asix-sigma/protocol.h +++ b/src/hardware/asix-sigma/protocol.h @@ -30,6 +30,8 @@ #include #include "libsigrok-internal.h" +#define LOG_PREFIX "asix-sigma" + /* * Triggers are not working in this implementation. Stop claiming * support for the feature which effectively is not available, until @@ -38,24 +40,67 @@ */ #define ASIX_SIGMA_WITH_TRIGGER 0 -#define LOG_PREFIX "asix-sigma" +/* Experimental support for OMEGA (scan only, operation is ENOIMPL). */ +#define ASIX_WITH_OMEGA 0 + +#define USB_VENDOR_ASIX 0xa600 +#define USB_PRODUCT_SIGMA 0xa000 +#define USB_PRODUCT_OMEGA 0xa004 -#define USB_VENDOR 0xa600 -#define USB_PRODUCT 0xa000 -#define USB_DESCRIPTION "ASIX SIGMA" -#define USB_VENDOR_NAME "ASIX" -#define USB_MODEL_NAME "SIGMA" +enum asix_device_type { + ASIX_TYPE_NONE, + ASIX_TYPE_SIGMA, + ASIX_TYPE_OMEGA, +}; + +/* + * FPGA commands are 8bits wide. The upper nibble is a command opcode, + * the lower nibble can carry operand values. 8bit register addresses + * and 8bit data values get communicated in two steps. + */ + +/* Register access. */ +#define REG_ADDR_LOW (0x0 << 4) +#define REG_ADDR_HIGH (0x1 << 4) +#define REG_DATA_LOW (0x2 << 4) +#define REG_DATA_HIGH_WRITE (0x3 << 4) +#define REG_READ_ADDR (0x4 << 4) +#define REG_ADDR_ADJUST (1 << 0) /* Auto adjust register address. */ +#define REG_ADDR_DOWN (1 << 1) /* 1 decrement, 0 increment. */ +#define REG_ADDR_INC (REG_ADDR_ADJUST) +#define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN) + +/* Sample memory access. */ +#define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */ +#define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */ +#define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */ +#define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */ +#define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */ +#define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0) + +/* + * Registers at a specific address can have different meanings depending + * on whether data is read or written. This is why direction is part of + * the programming language identifiers. + * + * The vendor documentation suggests that in addition to the first 16 + * register addresses which implement the logic analyzer's feature set, + * there are 240 more registers in the 16 to 255 address range which + * are available to applications and plugin features. Can libsigrok's + * asix-sigma driver store configuration data there, to avoid expensive + * operations (think: firmware re-load). + */ enum sigma_write_register { WRITE_CLOCK_SELECT = 0, - WRITE_TRIGGER_SELECT0 = 1, - WRITE_TRIGGER_SELECT1 = 2, + WRITE_TRIGGER_SELECT = 1, + WRITE_TRIGGER_SELECT2 = 2, WRITE_MODE = 3, WRITE_MEMROW = 4, WRITE_POST_TRIGGER = 5, WRITE_TRIGGER_OPTION = 6, WRITE_PIN_VIEW = 7, - + /* Unassigned register locations. */ WRITE_TEST = 15, }; @@ -72,27 +117,15 @@ enum sigma_read_register { READ_PIN_CHANGE_HIGH = 9, READ_BLOCK_LAST_TS_LOW = 10, READ_BLOCK_LAST_TS_HIGH = 11, - READ_PIN_VIEW = 12, - + READ_BLOCK_TS_OVERRUN = 12, + READ_PIN_VIEW = 13, + /* Unassigned register location. */ READ_TEST = 15, }; -#define REG_ADDR_LOW (0x0 << 4) -#define REG_ADDR_HIGH (0x1 << 4) -#define REG_DATA_LOW (0x2 << 4) -#define REG_DATA_HIGH_WRITE (0x3 << 4) -#define REG_READ_ADDR (0x4 << 4) -#define REG_DRAM_WAIT_ACK (0x5 << 4) - -/* Bit (1 << 4) can be low or high (double buffer / cache) */ -#define REG_DRAM_BLOCK (0x6 << 4) -#define REG_DRAM_BLOCK_BEGIN (0x8 << 4) -#define REG_DRAM_BLOCK_DATA (0xa << 4) - #define LEDSEL0 6 #define LEDSEL1 7 -#define NEXT_REG 1 #define EVENTS_PER_CLUSTER 7 @@ -248,26 +281,31 @@ struct sigma_state { SIGMA_UNINITIALIZED = 0, SIGMA_IDLE, SIGMA_CAPTURE, + SIGMA_STOPPING, SIGMA_DOWNLOAD, } state; - uint16_t lastts; uint16_t lastsample; }; -/* Private, per-device-instance driver context. */ struct dev_context { + struct { + uint16_t vid, pid; + uint32_t serno; + uint16_t prefix; + enum asix_device_type type; + } id; struct ftdi_context ftdic; uint64_t cur_samplerate; uint64_t limit_msec; uint64_t limit_samples; uint64_t sent_samples; - struct timeval start_tv; + uint64_t start_time; int cur_firmware; int num_channels; int cur_channels; int samples_per_event; - int capture_ratio; + uint64_t capture_ratio; struct sigma_trigger trigger; int use_triggers; struct sigma_state state; @@ -276,11 +314,10 @@ struct dev_context { extern SR_PRIV const uint64_t samplerates[]; extern SR_PRIV const size_t samplerates_count; -SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, +SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, struct dev_context *devc); SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc); SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc); -SR_PRIV void sigma_clear_helper(void *priv); SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc, uint64_t limit_samples); SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate);