output/csv: use intermediate time_t var, silence compiler warning

[libsigrok.git] / src / hardware / saleae-logic16 / protocol.h

diff --git a/src/hardware/saleae-logic16/protocol.h b/src/hardware/saleae-logic16/protocol.h
index 9f834164c83d14bb3603a75f1815348b13f74e02..003358169871a1f144833f5c4641966413cfc3e3 100644 (file)
--- a/src/hardware/saleae-logic16/protocol.h
+++ b/src/hardware/saleae-logic16/protocol.h
@@ -41,7 +41,6 @@ enum fpga_variant {
        FPGA_VARIANT_MCUPRO    /* mcupro clone v4.6 with Actel FPGA */
 };
 
        FPGA_VARIANT_MCUPRO    /* mcupro clone v4.6 with Actel FPGA */
 };
 

-/** Private, per-device-instance driver context. */

 struct dev_context {
        /** Distinguishing between original Logic16 and clones */
        enum fpga_variant fpga_variant;
 struct dev_context {
        /** Distinguishing between original Logic16 and clones */
        enum fpga_variant fpga_variant;


@@ -87,7 +86,6 @@ struct dev_context {
        struct soft_trigger_logic *stl;
        gboolean trigger_fired;
 
        struct soft_trigger_logic *stl;
        gboolean trigger_fired;
 

-       void *cb_data;

        unsigned int num_transfers;
        struct libusb_transfer **transfers;
        struct sr_context *ctx;
        unsigned int num_transfers;
        struct libusb_transfer **transfers;
        struct sr_context *ctx;