output/csv: use intermediate time_t var, silence compiler warning

[libsigrok.git] / src / hardware / saleae-logic16 / protocol.h

diff --git a/src/hardware/saleae-logic16/protocol.h b/src/hardware/saleae-logic16/protocol.h
index 9eead9a9e772ffc80b728c12c058f1df36cbf758..003358169871a1f144833f5c4641966413cfc3e3 100644 (file)
--- a/src/hardware/saleae-logic16/protocol.h
+++ b/src/hardware/saleae-logic16/protocol.h
@@ -41,7 +41,6 @@ enum fpga_variant {
        FPGA_VARIANT_MCUPRO    /* mcupro clone v4.6 with Actel FPGA */
 };
 
-/** Private, per-device-instance driver context. */
 struct dev_context {
        /** Distinguishing between original Logic16 and clones */
        enum fpga_variant fpga_variant;