output/csv: use intermediate time_t var, silence compiler warning

[libsigrok.git] / src / hardware / saleae-logic16 / protocol.h

diff --git a/src/hardware/saleae-logic16/protocol.h b/src/hardware/saleae-logic16/protocol.h
index 00979a305cedd825bd29fcad3cba5beeb2030369..003358169871a1f144833f5c4641966413cfc3e3 100644 (file)
--- a/src/hardware/saleae-logic16/protocol.h
+++ b/src/hardware/saleae-logic16/protocol.h
@@ -24,7 +24,7 @@
 
 #include <stdint.h>
 #include <glib.h>
-#include "libsigrok.h"
+#include <libsigrok/libsigrok.h>
 #include "libsigrok-internal.h"
 
 #define LOG_PREFIX "saleae-logic16"
@@ -37,10 +37,10 @@ enum voltage_range {
 
 enum fpga_variant {
        FPGA_VARIANT_ORIGINAL,
+       FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM,
        FPGA_VARIANT_MCUPRO    /* mcupro clone v4.6 with Actel FPGA */
 };
 
-/** Private, per-device-instance driver context. */
 struct dev_context {
        /** Distinguishing between original Logic16 and clones */
        enum fpga_variant fpga_variant;
@@ -86,10 +86,13 @@ struct dev_context {
        struct soft_trigger_logic *stl;
        gboolean trigger_fired;
 
-       void *cb_data;
        unsigned int num_transfers;
        struct libusb_transfer **transfers;
        struct sr_context *ctx;
+
+       const uint8_t *fpga_register_map;
+       const uint8_t *fpga_status_control_bit_map;
+       const uint8_t *fpga_mode_bit_map;
 };
 
 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
@@ -97,6 +100,6 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
 SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi);
-SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer);
+SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer);
 
 #endif