src/hardware/saleae-logic16/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
   5  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   6  * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 3 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdint.h>
  23 #include <string.h>
  24 #include <glib.h>
  25 #include <glib/gstdio.h>
  26 #include <stdio.h>
  27 #include <errno.h>
  28 #include <math.h>
  29 #include <libsigrok/libsigrok.h>
  30 #include "libsigrok-internal.h"
  31 #include "protocol.h"
  32
  33 #define FPGA_FIRMWARE_18        FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
  34 #define FPGA_FIRMWARE_33        FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
  35
  36 #define MAX_SAMPLE_RATE         SR_MHZ(100)
  37 #define MAX_4CH_SAMPLE_RATE     SR_MHZ(50)
  38 #define MAX_7CH_SAMPLE_RATE     SR_MHZ(40)
  39 #define MAX_8CH_SAMPLE_RATE     SR_MHZ(32)
  40 #define MAX_10CH_SAMPLE_RATE    SR_MHZ(25)
  41 #define MAX_13CH_SAMPLE_RATE    SR_MHZ(16)
  42
  43 #define BASE_CLOCK_0_FREQ       SR_MHZ(100)
  44 #define BASE_CLOCK_1_FREQ       SR_MHZ(160)
  45
  46 #define COMMAND_START_ACQUISITION       1
  47 #define COMMAND_ABORT_ACQUISITION_ASYNC 2
  48 #define COMMAND_WRITE_EEPROM            6
  49 #define COMMAND_READ_EEPROM             7
  50 #define COMMAND_WRITE_LED_TABLE         0x7a
  51 #define COMMAND_SET_LED_MODE            0x7b
  52 #define COMMAND_RETURN_TO_BOOTLOADER    0x7c
  53 #define COMMAND_ABORT_ACQUISITION_SYNC  0x7d
  54 #define COMMAND_FPGA_UPLOAD_INIT        0x7e
  55 #define COMMAND_FPGA_UPLOAD_SEND_DATA   0x7f
  56 #define COMMAND_FPGA_WRITE_REGISTER     0x80
  57 #define COMMAND_FPGA_READ_REGISTER      0x81
  58 #define COMMAND_GET_REVID               0x82
  59
  60 #define WRITE_EEPROM_COOKIE1            0x42
  61 #define WRITE_EEPROM_COOKIE2            0x55
  62 #define READ_EEPROM_COOKIE1             0x33
  63 #define READ_EEPROM_COOKIE2             0x81
  64 #define ABORT_ACQUISITION_SYNC_PATTERN  0x55
  65
  66 #define MAX_EMPTY_TRANSFERS             64
  67
  68 /* Register mappings for old and new bitstream versions */
  69
  70 enum fpga_register_id {
  71         FPGA_REGISTER_VERSION,
  72         FPGA_REGISTER_STATUS_CONTROL,
  73         FPGA_REGISTER_CHANNEL_SELECT_LOW,
  74         FPGA_REGISTER_CHANNEL_SELECT_HIGH,
  75         FPGA_REGISTER_SAMPLE_RATE_DIVISOR,
  76         FPGA_REGISTER_LED_BRIGHTNESS,
  77         FPGA_REGISTER_PRIMER_DATA1,
  78         FPGA_REGISTER_PRIMER_CONTROL,
  79         FPGA_REGISTER_MODE,
  80         FPGA_REGISTER_PRIMER_DATA2,
  81         FPGA_REGISTER_MAX = FPGA_REGISTER_PRIMER_DATA2
  82 };
  83
  84 enum fpga_status_control_bit {
  85         FPGA_STATUS_CONTROL_BIT_RUNNING,
  86         FPGA_STATUS_CONTROL_BIT_UPDATE,
  87         FPGA_STATUS_CONTROL_BIT_UNKNOWN1,
  88         FPGA_STATUS_CONTROL_BIT_OVERFLOW,
  89         FPGA_STATUS_CONTROL_BIT_UNKNOWN2,
  90         FPGA_STATUS_CONTROL_BIT_MAX = FPGA_STATUS_CONTROL_BIT_UNKNOWN2
  91 };
  92
  93 enum fpga_mode_bit {
  94         FPGA_MODE_BIT_CLOCK,
  95         FPGA_MODE_BIT_UNKNOWN1,
  96         FPGA_MODE_BIT_UNKNOWN2,
  97         FPGA_MODE_BIT_MAX = FPGA_MODE_BIT_UNKNOWN2
  98 };
  99
 100 static const uint8_t fpga_register_map_old[FPGA_REGISTER_MAX + 1] = {
 101         [FPGA_REGISTER_VERSION]                 = 0,
 102         [FPGA_REGISTER_STATUS_CONTROL]          = 1,
 103         [FPGA_REGISTER_CHANNEL_SELECT_LOW]      = 2,
 104         [FPGA_REGISTER_CHANNEL_SELECT_HIGH]     = 3,
 105         [FPGA_REGISTER_SAMPLE_RATE_DIVISOR]     = 4,
 106         [FPGA_REGISTER_LED_BRIGHTNESS]          = 5,
 107         [FPGA_REGISTER_PRIMER_DATA1]            = 6,
 108         [FPGA_REGISTER_PRIMER_CONTROL]          = 7,
 109         [FPGA_REGISTER_MODE]                    = 10,
 110         [FPGA_REGISTER_PRIMER_DATA2]            = 12,
 111 };
 112
 113 static const uint8_t fpga_register_map_new[FPGA_REGISTER_MAX + 1] = {
 114         [FPGA_REGISTER_VERSION]                 = 7,
 115         [FPGA_REGISTER_STATUS_CONTROL]          = 15,
 116         [FPGA_REGISTER_CHANNEL_SELECT_LOW]      = 1,
 117         [FPGA_REGISTER_CHANNEL_SELECT_HIGH]     = 6,
 118         [FPGA_REGISTER_SAMPLE_RATE_DIVISOR]     = 11,
 119         [FPGA_REGISTER_LED_BRIGHTNESS]          = 5,
 120         [FPGA_REGISTER_PRIMER_DATA1]            = 14,
 121         [FPGA_REGISTER_PRIMER_CONTROL]          = 2,
 122         [FPGA_REGISTER_MODE]                    = 4,
 123         [FPGA_REGISTER_PRIMER_DATA2]            = 3,
 124 };
 125
 126 static const uint8_t fpga_status_control_bit_map_old[FPGA_STATUS_CONTROL_BIT_MAX + 1] = {
 127         [FPGA_STATUS_CONTROL_BIT_RUNNING]       = 0x01,
 128         [FPGA_STATUS_CONTROL_BIT_UPDATE]        = 0x02,
 129         [FPGA_STATUS_CONTROL_BIT_UNKNOWN1]      = 0x08,
 130         [FPGA_STATUS_CONTROL_BIT_OVERFLOW]      = 0x20,
 131         [FPGA_STATUS_CONTROL_BIT_UNKNOWN2]      = 0x40,
 132 };
 133
 134 static const uint8_t fpga_status_control_bit_map_new[FPGA_STATUS_CONTROL_BIT_MAX + 1] = {
 135         [FPGA_STATUS_CONTROL_BIT_RUNNING]       = 0x20,
 136         [FPGA_STATUS_CONTROL_BIT_UPDATE]        = 0x08,
 137         [FPGA_STATUS_CONTROL_BIT_UNKNOWN1]      = 0x10,
 138         [FPGA_STATUS_CONTROL_BIT_OVERFLOW]      = 0x01,
 139         [FPGA_STATUS_CONTROL_BIT_UNKNOWN2]      = 0x04,
 140 };
 141
 142 static const uint8_t fpga_mode_bit_map_old[FPGA_MODE_BIT_MAX + 1] = {
 143         [FPGA_MODE_BIT_CLOCK]           = 0x01,
 144         [FPGA_MODE_BIT_UNKNOWN1]        = 0x40,
 145         [FPGA_MODE_BIT_UNKNOWN2]        = 0x80,
 146 };
 147
 148 static const uint8_t fpga_mode_bit_map_new[FPGA_MODE_BIT_MAX + 1] = {
 149         [FPGA_MODE_BIT_CLOCK]           = 0x04,
 150         [FPGA_MODE_BIT_UNKNOWN1]        = 0x80,
 151         [FPGA_MODE_BIT_UNKNOWN2]        = 0x01,
 152 };
 153
 154 #define FPGA_REG(x) \
 155         (devc->fpga_register_map[FPGA_REGISTER_ ## x])
 156
 157 #define FPGA_STATUS_CONTROL(x) \
 158         (devc->fpga_status_control_bit_map[FPGA_STATUS_CONTROL_BIT_ ## x])
 159
 160 #define FPGA_MODE(x) \
 161         (devc->fpga_mode_bit_map[FPGA_MODE_BIT_ ## x])
 162
 163 static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
 164 {
 165         uint8_t state1 = 0x9b, state2 = 0x54;
 166         uint8_t t, v;
 167         int i;
 168
 169         for (i = 0; i < cnt; i++) {
 170                 v = src[i];
 171                 t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
 172                 t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
 173                 dest[i] = state2 = t;
 174                 state1 = v;
 175         }
 176 }
 177
 178 static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
 179 {
 180         uint8_t state1 = 0x9b, state2 = 0x54;
 181         uint8_t t, v;
 182         int i;
 183
 184         for (i = 0; i < cnt; i++) {
 185                 v = src[i];
 186                 t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
 187                 t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
 188                 dest[i] = state1 = t;
 189                 state2 = v;
 190         }
 191 }
 192
 193 static int do_ep1_command(const struct sr_dev_inst *sdi,
 194                           const uint8_t *command, uint8_t cmd_len,
 195                           uint8_t *reply, uint8_t reply_len)
 196 {
 197         uint8_t buf[64];
 198         struct sr_usb_dev_inst *usb;
 199         int ret, xfer;
 200
 201         usb = sdi->conn;
 202
 203         if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
 204             !command || (reply_len > 0 && !reply))
 205                 return SR_ERR_ARG;
 206
 207         encrypt(buf, command, cmd_len);
 208
 209         ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
 210         if (ret != 0) {
 211                 sr_dbg("Failed to send EP1 command 0x%02x: %s.",
 212                        command[0], libusb_error_name(ret));
 213                 return SR_ERR;
 214         }
 215         if (xfer != cmd_len) {
 216                 sr_dbg("Failed to send EP1 command 0x%02x: incorrect length "
 217                        "%d != %d.", xfer, cmd_len);
 218                 return SR_ERR;
 219         }
 220
 221         if (reply_len == 0)
 222                 return SR_OK;
 223
 224         ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len,
 225                                    &xfer, 1000);
 226         if (ret != 0) {
 227                 sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.",
 228                        command[0], libusb_error_name(ret));
 229                 return SR_ERR;
 230         }
 231         if (xfer != reply_len) {
 232                 sr_dbg("Failed to receive reply to EP1 command 0x%02x: "
 233                        "incorrect length %d != %d.", xfer, reply_len);
 234                 return SR_ERR;
 235         }
 236
 237         decrypt(reply, buf, reply_len);
 238
 239         return SR_OK;
 240 }
 241
 242 static int read_eeprom(const struct sr_dev_inst *sdi,
 243                        uint8_t address, uint8_t length, uint8_t *buf)
 244 {
 245         uint8_t command[5] = {
 246                 COMMAND_READ_EEPROM,
 247                 READ_EEPROM_COOKIE1,
 248                 READ_EEPROM_COOKIE2,
 249                 address,
 250                 length,
 251         };
 252
 253         return do_ep1_command(sdi, command, 5, buf, length);
 254 }
 255
 256 static int upload_led_table(const struct sr_dev_inst *sdi,
 257                             const uint8_t *table, uint8_t offset, uint8_t cnt)
 258 {
 259         uint8_t chunk, command[64];
 260         int ret;
 261
 262         if (cnt < 1 || cnt + offset > 64 || !table)
 263                 return SR_ERR_ARG;
 264
 265         while (cnt > 0) {
 266                 chunk = (cnt > 32 ? 32 : cnt);
 267
 268                 command[0] = COMMAND_WRITE_LED_TABLE;
 269                 command[1] = offset;
 270                 command[2] = chunk;
 271                 memcpy(command + 3, table, chunk);
 272
 273                 ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0);
 274                 if (ret != SR_OK)
 275                         return ret;
 276
 277                 table += chunk;
 278                 offset += chunk;
 279                 cnt -= chunk;
 280         }
 281
 282         return SR_OK;
 283 }
 284
 285 static int set_led_mode(const struct sr_dev_inst *sdi,
 286                         uint8_t animate, uint16_t t2reload, uint8_t div,
 287                         uint8_t repeat)
 288 {
 289         uint8_t command[6] = {
 290                 COMMAND_SET_LED_MODE,
 291                 animate,
 292                 t2reload & 0xff,
 293                 t2reload >> 8,
 294                 div,
 295                 repeat,
 296         };
 297
 298         return do_ep1_command(sdi, command, 6, NULL, 0);
 299 }
 300
 301 static int read_fpga_register(const struct sr_dev_inst *sdi,
 302                               uint8_t address, uint8_t *value)
 303 {
 304         uint8_t command[3] = {
 305                 COMMAND_FPGA_READ_REGISTER,
 306                 1,
 307                 address,
 308         };
 309
 310         return do_ep1_command(sdi, command, 3, value, 1);
 311 }
 312
 313 static int write_fpga_registers(const struct sr_dev_inst *sdi,
 314                                 uint8_t (*regs)[2], uint8_t cnt)
 315 {
 316         uint8_t command[64];
 317         int i;
 318
 319         if (cnt < 1 || cnt > 31)
 320                 return SR_ERR_ARG;
 321
 322         command[0] = COMMAND_FPGA_WRITE_REGISTER;
 323         command[1] = cnt;
 324         for (i = 0; i < cnt; i++) {
 325                 command[2 + 2 * i] = regs[i][0];
 326                 command[3 + 2 * i] = regs[i][1];
 327         }
 328
 329         return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0);
 330 }
 331
 332 static int write_fpga_register(const struct sr_dev_inst *sdi,
 333                                uint8_t address, uint8_t value)
 334 {
 335         uint8_t regs[2] = { address, value };
 336
 337         return write_fpga_registers(sdi, &regs, 1);
 338 }
 339
 340 static uint8_t map_eeprom_data(uint8_t v)
 341 {
 342         return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69;
 343 }
 344
 345 static int setup_register_mapping(const struct sr_dev_inst *sdi)
 346 {
 347         struct dev_context *devc;
 348         int ret;
 349
 350         devc = sdi->priv;
 351
 352         if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) {
 353                 uint8_t reg0, reg7;
 354
 355                 /*
 356                  * Check for newer bitstream version by polling the
 357                  * version register at the old and new location.
 358                  */
 359
 360                 if ((ret = read_fpga_register(sdi, 0 /* No mapping */, &reg0)) != SR_OK)
 361                         return ret;
 362
 363                 if ((ret = read_fpga_register(sdi, 7 /* No mapping */, &reg7)) != SR_OK)
 364                         return ret;
 365
 366                 if (reg0 == 0 && reg7 > 0x10) {
 367                         sr_info("Original Saleae Logic16 using new bitstream.");
 368                         devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM;
 369                 } else {
 370                         sr_info("Original Saleae Logic16 using old bitstream.");
 371                         devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
 372                 }
 373         }
 374
 375         if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) {
 376                 devc->fpga_register_map = fpga_register_map_new;
 377                 devc->fpga_status_control_bit_map = fpga_status_control_bit_map_new;
 378                 devc->fpga_mode_bit_map = fpga_mode_bit_map_new;
 379         } else {
 380                 devc->fpga_register_map = fpga_register_map_old;
 381                 devc->fpga_status_control_bit_map = fpga_status_control_bit_map_old;
 382                 devc->fpga_mode_bit_map = fpga_mode_bit_map_old;
 383         }
 384
 385         return SR_OK;
 386 }
 387
 388 static int prime_fpga(const struct sr_dev_inst *sdi)
 389 {
 390         struct dev_context *devc = sdi->priv;
 391         uint8_t eeprom_data[16];
 392         uint8_t old_mode_reg, version;
 393         uint8_t regs[8][2] = {
 394                 {FPGA_REG(MODE), 0x00},
 395                 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)},
 396                 {FPGA_REG(PRIMER_DATA2), 0},
 397                 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1) | FPGA_MODE(UNKNOWN2)},
 398                 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)},
 399                 {FPGA_REG(PRIMER_DATA1), 0},
 400                 {FPGA_REG(PRIMER_CONTROL), 1},
 401                 {FPGA_REG(PRIMER_CONTROL), 0}
 402         };
 403         int i, ret;
 404
 405         if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
 406                 return ret;
 407
 408         if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &old_mode_reg)) != SR_OK)
 409                 return ret;
 410
 411         regs[0][1] = (old_mode_reg &= ~FPGA_MODE(UNKNOWN2));
 412         regs[1][1] |= old_mode_reg;
 413         regs[3][1] |= old_mode_reg;
 414         regs[4][1] |= old_mode_reg;
 415
 416         for (i = 0; i < 16; i++) {
 417                 regs[2][1] = eeprom_data[i];
 418                 regs[5][1] = map_eeprom_data(eeprom_data[i]);
 419                 if (i)
 420                         ret = write_fpga_registers(sdi, &regs[2], 6);
 421                 else
 422                         ret = write_fpga_registers(sdi, &regs[0], 8);
 423                 if (ret != SR_OK)
 424                         return ret;
 425         }
 426
 427         if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), old_mode_reg)) != SR_OK)
 428                 return ret;
 429
 430         if ((ret = read_fpga_register(sdi, FPGA_REG(VERSION), &version)) != SR_OK)
 431                 return ret;
 432
 433         if (version != 0x10 && version != 0x13 && version != 0x40 && version != 0x41) {
 434                 sr_err("Unsupported FPGA version: 0x%02x.", version);
 435                 return SR_ERR;
 436         }
 437
 438         return SR_OK;
 439 }
 440
 441 static void make_heartbeat(uint8_t *table, int len)
 442 {
 443         int i, j;
 444
 445         memset(table, 0, len);
 446         len >>= 3;
 447         for (i = 0; i < 2; i++)
 448                 for (j = 0; j < len; j++)
 449                         *table++ = sin(j * G_PI / len) * 255;
 450 }
 451
 452 static int configure_led(const struct sr_dev_inst *sdi)
 453 {
 454         uint8_t table[64];
 455         int ret;
 456
 457         make_heartbeat(table, 64);
 458         if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
 459                 return ret;
 460
 461         return set_led_mode(sdi, 1, 6250, 0, 1);
 462 }
 463
 464 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
 465                                  enum voltage_range vrange)
 466 {
 467         struct dev_context *devc;
 468         int offset, chunksize, ret;
 469         const char *filename;
 470         uint8_t len, buf[256 * 62], command[64];
 471         FILE *fw;
 472
 473         devc = sdi->priv;
 474
 475         if (devc->cur_voltage_range == vrange)
 476                 return SR_OK;
 477
 478         if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) {
 479                 switch (vrange) {
 480                 case VOLTAGE_RANGE_18_33_V:
 481                         filename = FPGA_FIRMWARE_18;
 482                         break;
 483                 case VOLTAGE_RANGE_5_V:
 484                         filename = FPGA_FIRMWARE_33;
 485                         break;
 486                 default:
 487                         sr_err("Unsupported voltage range.");
 488                         return SR_ERR;
 489                 }
 490
 491                 sr_info("Uploading FPGA bitstream at %s.", filename);
 492                 if (!(fw = g_fopen(filename, "rb"))) {
 493                         sr_err("Unable to open bitstream file %s for reading: %s.",
 494                                filename, strerror(errno));
 495                         return SR_ERR;
 496                 }
 497
 498                 buf[0] = COMMAND_FPGA_UPLOAD_INIT;
 499                 if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
 500                         fclose(fw);
 501                         return ret;
 502                 }
 503
 504                 while (1) {
 505                         chunksize = fread(buf, 1, sizeof(buf), fw);
 506                         if (chunksize == 0)
 507                                 break;
 508
 509                         for (offset = 0; offset < chunksize; offset += 62) {
 510                                 len = (offset + 62 > chunksize ?
 511                                         chunksize - offset : 62);
 512                                 command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
 513                                 command[1] = len;
 514                                 memcpy(command + 2, buf + offset, len);
 515                                 ret = do_ep1_command(sdi, command, len + 2, NULL, 0);
 516                                 if (ret != SR_OK) {
 517                                         fclose(fw);
 518                                         return ret;
 519                                 }
 520                         }
 521
 522                         sr_info("Uploaded %d bytes.", chunksize);
 523                 }
 524                 fclose(fw);
 525                 sr_info("FPGA bitstream upload done.");
 526         }
 527
 528         /* This needs to be called before accessing any FPGA registers. */
 529         if ((ret = setup_register_mapping(sdi)) != SR_OK)
 530                 return ret;
 531
 532         if ((ret = prime_fpga(sdi)) != SR_OK)
 533                 return ret;
 534
 535         if ((ret = configure_led(sdi)) != SR_OK)
 536                 return ret;
 537
 538         devc->cur_voltage_range = vrange;
 539         return SR_OK;
 540 }
 541
 542 static int abort_acquisition_sync(const struct sr_dev_inst *sdi)
 543 {
 544         static const uint8_t command[2] = {
 545                 COMMAND_ABORT_ACQUISITION_SYNC,
 546                 ABORT_ACQUISITION_SYNC_PATTERN,
 547         };
 548         uint8_t reply, expected_reply;
 549         int ret;
 550
 551         if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
 552                 return ret;
 553
 554         expected_reply = ~command[1];
 555         if (reply != expected_reply) {
 556                 sr_err("Invalid response for abort acquisition command: "
 557                        "0x%02x != 0x%02x.", reply, expected_reply);
 558                 return SR_ERR;
 559         }
 560
 561         return SR_OK;
 562 }
 563
 564 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
 565                              uint64_t samplerate, uint16_t channels)
 566 {
 567         uint8_t clock_select, sta_con_reg, mode_reg;
 568         uint64_t div;
 569         int i, ret, nchan = 0;
 570         struct dev_context *devc;
 571
 572         devc = sdi->priv;
 573
 574         if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
 575                 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
 576                 return SR_ERR;
 577         }
 578
 579         if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
 580             (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
 581                 clock_select = 0;
 582         } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
 583                    (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
 584                 clock_select = 1;
 585         } else {
 586                 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
 587                 return SR_ERR;
 588         }
 589
 590         for (i = 0; i < 16; i++)
 591                 if (channels & (1U << i))
 592                         nchan++;
 593
 594         if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
 595             (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
 596             (nchan >= 8  && samplerate > MAX_8CH_SAMPLE_RATE) ||
 597             (nchan >= 7  && samplerate > MAX_7CH_SAMPLE_RATE) ||
 598             (nchan >= 4  && samplerate > MAX_4CH_SAMPLE_RATE)) {
 599                 sr_err("Unable to sample at %" PRIu64 "Hz "
 600                        "with this many channels.", samplerate);
 601                 return SR_ERR;
 602         }
 603
 604         ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
 605         if (ret != SR_OK)
 606                 return ret;
 607
 608         if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
 609                 return ret;
 610
 611         /* Ignore FIFO overflow on previous capture */
 612         sta_con_reg &= ~FPGA_STATUS_CONTROL(OVERFLOW);
 613
 614         if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != FPGA_STATUS_CONTROL(UNKNOWN1)) {
 615                 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. "
 616                        "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN1));
 617         }
 618
 619         if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK)
 620                 return ret;
 621
 622         if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), (clock_select? FPGA_MODE(CLOCK) : 0))) != SR_OK)
 623                 return ret;
 624
 625         if ((ret = write_fpga_register(sdi, FPGA_REG(SAMPLE_RATE_DIVISOR), (uint8_t)(div - 1))) != SR_OK)
 626                 return ret;
 627
 628         if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_LOW), (uint8_t)(channels & 0xff))) != SR_OK)
 629                 return ret;
 630
 631         if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_HIGH), (uint8_t)(channels >> 8))) != SR_OK)
 632                 return ret;
 633
 634         if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UPDATE))) != SR_OK)
 635                 return ret;
 636
 637         if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK)
 638                 return ret;
 639
 640         if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
 641                 return ret;
 642
 643         if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != (FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1))) {
 644                 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. "
 645                        "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1));
 646         }
 647
 648         if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &mode_reg)) != SR_OK)
 649                 return ret;
 650
 651         if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && mode_reg != (clock_select? FPGA_MODE(CLOCK) : 0)) {
 652                 sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. "
 653                        "Proceeding anyway.", mode_reg, (clock_select? FPGA_MODE(CLOCK) : 0));
 654         }
 655
 656         return SR_OK;
 657 }
 658
 659 SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi)
 660 {
 661         static const uint8_t command[1] = {
 662                 COMMAND_START_ACQUISITION,
 663         };
 664         int ret;
 665         struct dev_context *devc;
 666
 667         devc = sdi->priv;
 668
 669         if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
 670                 return ret;
 671
 672         return write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(RUNNING));
 673 }
 674
 675 SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi)
 676 {
 677         static const uint8_t command[1] = {
 678                 COMMAND_ABORT_ACQUISITION_ASYNC,
 679         };
 680         int ret;
 681         uint8_t sta_con_reg;
 682         struct dev_context *devc;
 683
 684         devc = sdi->priv;
 685
 686         if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
 687                 return ret;
 688
 689         if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), 0x00)) != SR_OK)
 690                 return ret;
 691
 692         if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
 693                 return ret;
 694
 695         if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && (sta_con_reg & ~FPGA_STATUS_CONTROL(OVERFLOW)) != FPGA_STATUS_CONTROL(UNKNOWN1)) {
 696                 sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x%02x.", sta_con_reg & ~0x20, FPGA_STATUS_CONTROL(UNKNOWN1));
 697                 return SR_ERR;
 698         }
 699
 700
 701         if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) {
 702                 uint8_t reg8, reg9;
 703
 704                 if ((ret = read_fpga_register(sdi, 8, &reg8)) != SR_OK)
 705                         return ret;
 706
 707                 if ((ret = read_fpga_register(sdi, 9, &reg9)) != SR_OK)
 708                         return ret;
 709         }
 710
 711         if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg & FPGA_STATUS_CONTROL(OVERFLOW)) {
 712                 sr_warn("FIFO overflow, capture data may be truncated.");
 713                 return SR_ERR;
 714         }
 715
 716         return SR_OK;
 717 }
 718
 719 SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi)
 720 {
 721         uint8_t version;
 722         struct dev_context *devc;
 723         int ret;
 724
 725         devc = sdi->priv;
 726
 727         devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
 728
 729         if ((ret = abort_acquisition_sync(sdi)) != SR_OK)
 730                 return ret;
 731
 732         if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
 733                 return ret;
 734
 735         /* mcupro Saleae16 has firmware pre-stored in FPGA.
 736            So, we can query it right away. */
 737         if (read_fpga_register(sdi, 0 /* No mapping */, &version) == SR_OK &&
 738             (version == 0x40 || version == 0x41)) {
 739                 sr_info("mcupro Saleae16 detected.");
 740                 devc->fpga_variant = FPGA_VARIANT_MCUPRO;
 741         } else {
 742                 sr_info("Original Saleae Logic16 detected.");
 743                 devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
 744         }
 745
 746         ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
 747         if (ret != SR_OK)
 748                 return ret;
 749
 750         return SR_OK;
 751 }
 752
 753 static void finish_acquisition(struct sr_dev_inst *sdi)
 754 {
 755         struct sr_datafeed_packet packet;
 756         struct dev_context *devc;
 757
 758         devc = sdi->priv;
 759
 760         /* Terminate session. */
 761         packet.type = SR_DF_END;
 762         sr_session_send(devc->cb_data, &packet);
 763
 764         /* Remove fds from polling. */
 765         usb_source_remove(sdi->session, devc->ctx);
 766
 767         devc->num_transfers = 0;
 768         g_free(devc->transfers);
 769         g_free(devc->convbuffer);
 770         if (devc->stl) {
 771                 soft_trigger_logic_free(devc->stl);
 772                 devc->stl = NULL;
 773         }
 774 }
 775
 776 static void free_transfer(struct libusb_transfer *transfer)
 777 {
 778         struct sr_dev_inst *sdi;
 779         struct dev_context *devc;
 780         unsigned int i;
 781
 782         sdi = transfer->user_data;
 783         devc = sdi->priv;
 784
 785         g_free(transfer->buffer);
 786         transfer->buffer = NULL;
 787         libusb_free_transfer(transfer);
 788
 789         for (i = 0; i < devc->num_transfers; i++) {
 790                 if (devc->transfers[i] == transfer) {
 791                         devc->transfers[i] = NULL;
 792                         break;
 793                 }
 794         }
 795
 796         devc->submitted_transfers--;
 797         if (devc->submitted_transfers == 0)
 798                 finish_acquisition(sdi);
 799 }
 800
 801 static void resubmit_transfer(struct libusb_transfer *transfer)
 802 {
 803         int ret;
 804
 805         if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
 806                 return;
 807
 808         free_transfer(transfer);
 809         /* TODO: Stop session? */
 810
 811         sr_err("%s: %s", __func__, libusb_error_name(ret));
 812 }
 813
 814 static size_t convert_sample_data(struct dev_context *devc,
 815                 uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt)
 816 {
 817         uint16_t *channel_data;
 818         int i, cur_channel;
 819         size_t ret = 0;
 820         uint16_t sample, channel_mask;
 821
 822         srccnt /= 2;
 823
 824         channel_data = devc->channel_data;
 825         cur_channel = devc->cur_channel;
 826
 827         while (srccnt--) {
 828                 sample = src[0] | (src[1] << 8);
 829                 src += 2;
 830
 831                 channel_mask = devc->channel_masks[cur_channel];
 832
 833                 for (i = 15; i >= 0; --i, sample >>= 1)
 834                         if (sample & 1)
 835                                 channel_data[i] |= channel_mask;
 836
 837                 if (++cur_channel == devc->num_channels) {
 838                         cur_channel = 0;
 839                         if (destcnt < 16 * 2) {
 840                                 sr_err("Conversion buffer too small!");
 841                                 break;
 842                         }
 843                         memcpy(dest, channel_data, 16 * 2);
 844                         memset(channel_data, 0, 16 * 2);
 845                         dest += 16 * 2;
 846                         ret += 16;
 847                         destcnt -= 16 * 2;
 848                 }
 849         }
 850
 851         devc->cur_channel = cur_channel;
 852
 853         return ret;
 854 }
 855
 856 SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer)
 857 {
 858         gboolean packet_has_error = FALSE;
 859         struct sr_datafeed_packet packet;
 860         struct sr_datafeed_logic logic;
 861         struct sr_dev_inst *sdi;
 862         struct dev_context *devc;
 863         size_t new_samples, num_samples;
 864         int trigger_offset;
 865         int pre_trigger_samples;
 866
 867         sdi = transfer->user_data;
 868         devc = sdi->priv;
 869
 870         /*
 871          * If acquisition has already ended, just free any queued up
 872          * transfer that come in.
 873          */
 874         if (devc->sent_samples < 0) {
 875                 free_transfer(transfer);
 876                 return;
 877         }
 878
 879         sr_info("receive_transfer(): status %s received %d bytes.",
 880                 libusb_error_name(transfer->status), transfer->actual_length);
 881
 882         switch (transfer->status) {
 883         case LIBUSB_TRANSFER_NO_DEVICE:
 884                 devc->sent_samples = -2;
 885                 free_transfer(transfer);
 886                 return;
 887         case LIBUSB_TRANSFER_COMPLETED:
 888         case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
 889                 break;
 890         default:
 891                 packet_has_error = TRUE;
 892                 break;
 893         }
 894
 895         if (transfer->actual_length & 1) {
 896                 sr_err("Got an odd number of bytes from the device. "
 897                        "This should not happen.");
 898                 /* Bail out right away. */
 899                 packet_has_error = TRUE;
 900                 devc->empty_transfer_count = MAX_EMPTY_TRANSFERS;
 901         }
 902
 903         if (transfer->actual_length == 0 || packet_has_error) {
 904                 devc->empty_transfer_count++;
 905                 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
 906                         /*
 907                          * The FX2 gave up. End the acquisition, the frontend
 908                          * will work out that the samplecount is short.
 909                          */
 910                         devc->sent_samples = -2;
 911                         free_transfer(transfer);
 912                 } else {
 913                         resubmit_transfer(transfer);
 914                 }
 915                 return;
 916         } else {
 917                 devc->empty_transfer_count = 0;
 918         }
 919
 920         new_samples = convert_sample_data(devc, devc->convbuffer,
 921                         devc->convbuffer_size, transfer->buffer, transfer->actual_length);
 922
 923         if (new_samples > 0) {
 924                 if (devc->trigger_fired) {
 925                         /* Send the incoming transfer to the session bus. */
 926                         packet.type = SR_DF_LOGIC;
 927                         packet.payload = &logic;
 928                         if (devc->limit_samples &&
 929                                         new_samples > devc->limit_samples - devc->sent_samples)
 930                                 new_samples = devc->limit_samples - devc->sent_samples;
 931                         logic.length = new_samples * 2;
 932                         logic.unitsize = 2;
 933                         logic.data = devc->convbuffer;
 934                         sr_session_send(devc->cb_data, &packet);
 935                         devc->sent_samples += new_samples;
 936                 } else {
 937                         trigger_offset = soft_trigger_logic_check(devc->stl,
 938                                         devc->convbuffer, new_samples * 2, &pre_trigger_samples);
 939                         if (trigger_offset > -1) {
 940                                 devc->sent_samples += pre_trigger_samples;
 941                                 packet.type = SR_DF_LOGIC;
 942                                 packet.payload = &logic;
 943                                 num_samples = new_samples - trigger_offset;
 944                                 if (devc->limit_samples &&
 945                                                 num_samples > devc->limit_samples - devc->sent_samples)
 946                                         num_samples = devc->limit_samples - devc->sent_samples;
 947                                 logic.length = num_samples * 2;
 948                                 logic.unitsize = 2;
 949                                 logic.data = devc->convbuffer + trigger_offset * 2;
 950                                 sr_session_send(devc->cb_data, &packet);
 951                                 devc->sent_samples += num_samples;
 952
 953                                 devc->trigger_fired = TRUE;
 954                         }
 955                 }
 956
 957                 if (devc->limit_samples &&
 958                                 (uint64_t)devc->sent_samples >= devc->limit_samples) {
 959                         devc->sent_samples = -2;
 960                         free_transfer(transfer);
 961                         return;
 962                 }
 963         }
 964
 965         resubmit_transfer(transfer);
 966 }