2 * This file is part of the libsigrok project.
4 * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
32 #include <libsigrok/libsigrok.h>
33 #include "libsigrok-internal.h"
38 * This is a unified protocol driver for the DS1000 and DS2000 series.
40 * DS1000 support tested with a Rigol DS1102D.
42 * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02.
44 * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think)
45 * standard. If you want to read it - it costs real money...
47 * Every response from the scope has a linefeed appended because the
48 * standard says so. In principle this could be ignored because sending the
49 * next command clears the output queue of the scope. This driver tries to
50 * avoid doing that because it may cause an error being generated inside the
51 * scope and who knows what bugs the firmware has WRT this.
53 * Waveform data is transferred in a format called "arbitrary block program
54 * data" specified in IEEE 488.2. See Agilents programming manuals for their
55 * 2000/3000 series scopes for a nice description.
57 * Each data block from the scope has a header, e.g. "#900000001400".
58 * The '#' marks the start of a block.
59 * Next is one ASCII decimal digit between 1 and 9, this gives the number of
60 * ASCII decimal digits following.
61 * Last are the ASCII decimal digits giving the number of bytes (not
62 * samples!) in the block.
64 * After this header as many data bytes as indicated follow.
66 * Each data block has a trailing linefeed too.
69 static int parse_int(const char *str, int *ret)
75 tmp = strtol(str, &e, 10);
76 if (e == str || *e != '\0') {
77 sr_dbg("Failed to parse integer: '%s'", str);
81 sr_dbg("Failed to parse integer: '%s', numerical overflow", str);
84 if (tmp > INT_MAX || tmp < INT_MIN) {
85 sr_dbg("Failed to parse integer: '%s', value to large/small", str);
93 /* Set the next event to wait for in rigol_ds_receive */
94 static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event)
96 if (event == WAIT_STOP)
97 devc->wait_status = 2;
99 devc->wait_status = 1;
100 devc->wait_event = event;
104 * Waiting for a event will return a timeout after 2 to 3 seconds in order
105 * to not block the application.
107 static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2)
110 struct dev_context *devc;
113 if (!(devc = sdi->priv))
119 * Trigger status may return:
120 * "TD" or "T'D" - triggered
121 * "AUTO" - autotriggered
123 * "WAIT" - waiting for trigger
127 if (devc->wait_status == 1) {
129 if (time(NULL) - start >= 3) {
130 sr_dbg("Timeout waiting for trigger");
131 return SR_ERR_TIMEOUT;
134 if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
136 } while (buf[0] == status1 || buf[0] == status2);
138 devc->wait_status = 2;
140 if (devc->wait_status == 2) {
142 if (time(NULL) - start >= 3) {
143 sr_dbg("Timeout waiting for trigger");
144 return SR_ERR_TIMEOUT;
147 if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
149 } while (buf[0] != status1 && buf[0] != status2);
151 rigol_ds_set_wait_event(devc, WAIT_NONE);
158 * For live capture we need to wait for a new trigger event to ensure that
159 * sample data is not returned twice.
161 * Unfortunately this will never really work because for sufficiently fast
162 * timebases and trigger rates it just can't catch the status changes.
164 * What would be needed is a trigger event register with autoreset like the
165 * Agilents have. The Rigols don't seem to have anything like this.
167 * The workaround is to only wait for the trigger when the timebase is slow
168 * enough. Of course this means that for faster timebases sample data can be
169 * returned multiple times, this effect is mitigated somewhat by sleeping
170 * for about one sweep time in that case.
172 static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi)
174 struct dev_context *devc;
177 if (!(devc = sdi->priv))
181 * If timebase < 50 msecs/DIV just sleep about one sweep time except
182 * for really fast sweeps.
184 if (devc->timebase < 0.0499) {
185 if (devc->timebase > 0.99e-6) {
187 * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100
188 * -> 85 percent of sweep time
190 s = (devc->timebase * devc->model->series->num_horizontal_divs
192 sr_spew("Sleeping for %ld usecs instead of trigger-wait", s);
195 rigol_ds_set_wait_event(devc, WAIT_NONE);
198 return rigol_ds_event_wait(sdi, 'T', 'A');
202 /* Wait for scope to got to "Stop" in single shot mode */
203 static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi)
205 return rigol_ds_event_wait(sdi, 'S', 'S');
208 /* Check that a single shot acquisition actually succeeded on the DS2000 */
209 static int rigol_ds_check_stop(const struct sr_dev_inst *sdi)
211 struct dev_context *devc;
212 struct sr_channel *ch;
215 if (!(devc = sdi->priv))
218 ch = devc->channel_entry->data;
220 if (devc->model->series->protocol != PROTOCOL_V3)
223 if (ch->type == SR_CHANNEL_LOGIC) {
224 if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK)
227 if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
228 ch->index + 1) != SR_OK)
231 /* Check that the number of samples will be accepted */
232 if (rigol_ds_config_set(sdi, ":WAV:POIN %d",
233 ch->type == SR_CHANNEL_LOGIC ?
234 devc->digital_frame_size :
235 devc->analog_frame_size) != SR_OK)
237 if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK)
240 * If we get an "Execution error" the scope went from "Single" to
241 * "Stop" without actually triggering. There is no waveform
242 * displayed and trying to download one will fail - the scope thinks
243 * it has 1400 samples (like display memory) and the driver thinks
244 * it has a different number of samples.
246 * In that case just try to capture something again. Might still
247 * fail in interesting ways.
249 * Ain't firmware fun?
252 sr_warn("Single shot acquisition failed, retrying...");
253 /* Sleep a bit, otherwise the single shot will often fail */
254 g_usleep(500 * 1000);
255 rigol_ds_config_set(sdi, ":SING");
256 rigol_ds_set_wait_event(devc, WAIT_STOP);
263 /* Wait for enough data becoming available in scope output buffer */
264 static int rigol_ds_block_wait(const struct sr_dev_inst *sdi)
267 struct dev_context *devc;
271 if (!(devc = sdi->priv))
274 if (devc->model->series->protocol == PROTOCOL_V3) {
279 if (time(NULL) - start >= 3) {
280 sr_dbg("Timeout waiting for data block");
281 return SR_ERR_TIMEOUT;
285 * The scope copies data really slowly from sample
286 * memory to its output buffer, so try not to bother
287 * it too much with SCPI requests but don't wait too
288 * long for short sample frame sizes.
290 g_usleep(devc->analog_frame_size < (15 * 1000) ? (100 * 1000) : (1000 * 1000));
292 /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */
293 if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK)
296 if (parse_int(buf + 5, &len) != SR_OK)
298 } while (buf[0] == 'R' && len < (1000 * 1000));
301 rigol_ds_set_wait_event(devc, WAIT_NONE);
306 /* Send a configuration setting. */
307 SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...)
309 struct dev_context *devc = sdi->priv;
313 va_start(args, format);
314 ret = sr_scpi_send_variadic(sdi->conn, format, args);
320 if (devc->model->series->protocol == PROTOCOL_V2) {
321 /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */
322 sr_spew("delay %dms", 100);
323 g_usleep(100 * 1000);
326 return sr_scpi_get_opc(sdi->conn);
330 /* Start capturing a new frameset */
331 SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
333 struct dev_context *devc;
335 unsigned int num_channels, i, j;
338 if (!(devc = sdi->priv))
341 uint64_t limit_frames = devc->limit_frames;
342 if (devc->num_frames_segmented != 0 && devc->num_frames_segmented < limit_frames)
343 limit_frames = devc->num_frames_segmented;
344 if (limit_frames == 0)
345 sr_dbg("Starting data capture for frameset %" PRIu64,
346 devc->num_frames + 1);
348 sr_dbg("Starting data capture for frameset %" PRIu64 " of %"
349 PRIu64, devc->num_frames + 1, limit_frames);
351 switch (devc->model->series->protocol) {
353 rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
356 if (devc->data_source == DATA_SOURCE_LIVE) {
357 if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK)
359 rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
361 if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
363 if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK)
365 if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK)
367 if (rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode) != SR_OK)
369 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
371 rigol_ds_set_wait_event(devc, WAIT_STOP);
377 if (rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK)
379 if (devc->data_source == DATA_SOURCE_LIVE) {
380 if (rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK)
382 devc->analog_frame_size = devc->model->series->live_samples;
383 devc->digital_frame_size = devc->model->series->live_samples;
384 rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
386 if (devc->model->series->protocol == PROTOCOL_V3) {
387 if (rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK)
389 } else if (devc->model->series->protocol >= PROTOCOL_V4) {
392 /* Channels 3 and 4 are multiplexed with D0-7 and D8-15 */
393 for (i = 0; i < devc->model->analog_channels; i++) {
394 if (devc->analog_channels[i]) {
396 } else if (i >= 2 && devc->model->has_digital) {
397 for (j = 0; j < 8; j++) {
398 if (devc->digital_channels[8 * (i - 2) + j]) {
406 buffer_samples = devc->model->series->buffer_samples;
407 if (buffer_samples == 0)
409 /* The DS4000 series does not have a fixed memory depth, it
410 * can be chosen from the menu and also varies with number
411 * of active channels. Retrieve the actual number with the
412 * ACQ:MDEP command. */
413 sr_scpi_get_int(sdi->conn, "ACQ:MDEP?", &buffer_samples);
414 devc->analog_frame_size = devc->digital_frame_size =
419 /* The DS1000Z series has a fixed memory depth which we
420 * need to divide correctly according to the number of
421 * active channels. */
422 devc->analog_frame_size = devc->digital_frame_size =
431 if (rigol_ds_config_set(sdi, ":SING") != SR_OK)
433 rigol_ds_set_wait_event(devc, WAIT_STOP);
434 if (devc->data_source == DATA_SOURCE_SEGMENTED)
435 if (rigol_ds_config_set(sdi, "FUNC:WREP:FCUR %d", devc->num_frames + 1) != SR_OK)
444 /* Start reading data from the current channel */
445 SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi)
447 struct dev_context *devc;
448 struct sr_channel *ch;
450 if (!(devc = sdi->priv))
453 ch = devc->channel_entry->data;
455 sr_dbg("Starting reading data from channel %d", ch->index + 1);
457 switch (devc->model->series->protocol) {
460 if (ch->type == SR_CHANNEL_LOGIC) {
461 if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK)
464 if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d",
465 ch->index + 1) != SR_OK)
468 rigol_ds_set_wait_event(devc, WAIT_NONE);
471 if (ch->type == SR_CHANNEL_LOGIC) {
472 if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK)
475 if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
476 ch->index + 1) != SR_OK)
479 if (devc->data_source != DATA_SOURCE_LIVE) {
480 if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
482 if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
488 if (ch->type == SR_CHANNEL_ANALOG) {
489 if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
490 ch->index + 1) != SR_OK)
493 if (rigol_ds_config_set(sdi, ":WAV:SOUR D%d",
498 if (rigol_ds_config_set(sdi,
499 devc->data_source == DATA_SOURCE_LIVE ?
500 ":WAV:MODE NORM" :":WAV:MODE RAW") != SR_OK)
503 if (devc->data_source != DATA_SOURCE_LIVE) {
504 if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
510 if (devc->model->series->protocol >= PROTOCOL_V3 &&
511 ch->type == SR_CHANNEL_ANALOG) {
512 /* Vertical increment. */
513 if (sr_scpi_get_float(sdi->conn, ":WAV:YINC?",
514 &devc->vert_inc[ch->index]) != SR_OK)
516 /* Vertical origin. */
517 if (sr_scpi_get_float(sdi->conn, ":WAV:YOR?",
518 &devc->vert_origin[ch->index]) != SR_OK)
520 /* Vertical reference. */
521 if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?",
522 &devc->vert_reference[ch->index]) != SR_OK)
524 } else if (ch->type == SR_CHANNEL_ANALOG) {
525 devc->vert_inc[ch->index] = devc->vdiv[ch->index] / 25.6;
528 rigol_ds_set_wait_event(devc, WAIT_BLOCK);
530 devc->num_channel_bytes = 0;
531 devc->num_header_bytes = 0;
532 devc->num_block_bytes = 0;
537 /* Read the header of a data block */
538 static int rigol_ds_read_header(struct sr_dev_inst *sdi)
540 struct sr_scpi_dev_inst *scpi = sdi->conn;
541 struct dev_context *devc = sdi->priv;
542 char *buf = (char *) devc->buffer;
543 size_t header_length;
546 /* Try to read the hashsign and length digit. */
547 if (devc->num_header_bytes < 2) {
548 ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes,
549 2 - devc->num_header_bytes);
551 sr_err("Read error while reading data header.");
554 devc->num_header_bytes += ret;
557 if (devc->num_header_bytes < 2)
560 if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') {
561 sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]);
565 header_length = 2 + buf[1] - '0';
567 /* Try to read the length. */
568 if (devc->num_header_bytes < header_length) {
569 ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes,
570 header_length - devc->num_header_bytes);
572 sr_err("Read error while reading data header.");
575 devc->num_header_bytes += ret;
578 if (devc->num_header_bytes < header_length)
581 /* Read the data length. */
582 buf[header_length] = '\0';
584 if (parse_int(buf + 2, &ret) != SR_OK) {
585 sr_err("Received invalid data block length '%s'.", buf + 2);
589 sr_dbg("Received data block header: '%s' -> block length %d", buf, ret);
594 SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data)
596 struct sr_dev_inst *sdi;
597 struct sr_scpi_dev_inst *scpi;
598 struct dev_context *devc;
599 struct sr_datafeed_packet packet;
600 struct sr_datafeed_analog analog;
601 struct sr_analog_encoding encoding;
602 struct sr_analog_meaning meaning;
603 struct sr_analog_spec spec;
604 struct sr_datafeed_logic logic;
605 double vdiv, offset, origin;
607 struct sr_channel *ch;
608 gsize expected_data_bytes;
612 if (!(sdi = cb_data))
615 if (!(devc = sdi->priv))
620 if (!(revents == G_IO_IN || revents == 0))
623 switch (devc->wait_event) {
627 if (rigol_ds_trigger_wait(sdi) != SR_OK)
629 if (rigol_ds_channel_start(sdi) != SR_OK)
633 if (rigol_ds_block_wait(sdi) != SR_OK)
637 if (rigol_ds_stop_wait(sdi) != SR_OK)
639 if (rigol_ds_check_stop(sdi) != SR_OK)
641 if (rigol_ds_channel_start(sdi) != SR_OK)
645 sr_err("BUG: Unknown event target encountered");
649 ch = devc->channel_entry->data;
651 expected_data_bytes = ch->type == SR_CHANNEL_ANALOG ?
652 devc->analog_frame_size : devc->digital_frame_size;
654 if (devc->num_block_bytes == 0) {
655 if (devc->model->series->protocol >= PROTOCOL_V4) {
656 if (rigol_ds_config_set(sdi, ":WAV:START %d",
657 devc->num_channel_bytes + 1) != SR_OK)
659 if (rigol_ds_config_set(sdi, ":WAV:STOP %d",
660 MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE,
661 devc->analog_frame_size)) != SR_OK)
665 if (devc->model->series->protocol >= PROTOCOL_V3) {
666 if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
668 if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK)
672 if (sr_scpi_read_begin(scpi) != SR_OK)
675 if (devc->format == FORMAT_IEEE488_2) {
676 sr_dbg("New block header expected");
677 len = rigol_ds_read_header(sdi);
679 /* Still reading the header. */
682 sr_err("Error while reading block header, aborting capture.");
683 std_session_send_df_frame_end(sdi);
684 sr_dev_acquisition_stop(sdi);
687 /* At slow timebases in live capture the DS2072
688 * sometimes returns "short" data blocks, with
689 * apparently no way to get the rest of the data.
690 * Discard these, the complete data block will
693 if (devc->data_source == DATA_SOURCE_LIVE
694 && (unsigned)len < expected_data_bytes) {
695 sr_dbg("Discarding short data block");
696 sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1);
699 devc->num_block_bytes = len;
701 devc->num_block_bytes = expected_data_bytes;
703 devc->num_block_read = 0;
706 len = devc->num_block_bytes - devc->num_block_read;
707 if (len > ACQ_BUFFER_SIZE)
708 len = ACQ_BUFFER_SIZE;
709 sr_dbg("Requesting read of %d bytes", len);
711 len = sr_scpi_read_data(scpi, (char *)devc->buffer, len);
714 sr_err("Error while reading block data, aborting capture.");
715 std_session_send_df_frame_end(sdi);
716 sr_dev_acquisition_stop(sdi);
720 sr_dbg("Received %d bytes.", len);
722 devc->num_block_read += len;
724 if (ch->type == SR_CHANNEL_ANALOG) {
725 vref = devc->vert_reference[ch->index];
726 vdiv = devc->vert_inc[ch->index];
727 origin = devc->vert_origin[ch->index];
728 offset = devc->vert_offset[ch->index];
729 if (devc->model->series->protocol >= PROTOCOL_V3)
730 for (i = 0; i < len; i++)
731 devc->data[i] = ((int)devc->buffer[i] - vref - origin) * vdiv;
733 for (i = 0; i < len; i++)
734 devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset;
735 float vdivlog = log10f(vdiv);
736 int digits = -(int)vdivlog + (vdivlog < 0.0);
737 sr_analog_init(&analog, &encoding, &meaning, &spec, digits);
738 analog.meaning->channels = g_slist_append(NULL, ch);
739 analog.num_samples = len;
740 analog.data = devc->data;
741 analog.meaning->mq = SR_MQ_VOLTAGE;
742 analog.meaning->unit = SR_UNIT_VOLT;
743 analog.meaning->mqflags = 0;
744 packet.type = SR_DF_ANALOG;
745 packet.payload = &analog;
746 sr_session_send(sdi, &packet);
747 g_slist_free(analog.meaning->channels);
750 // TODO: For the MSO1000Z series, we need a way to express that
751 // this data is in fact just for a single channel, with the valid
752 // data for that channel in the LSB of each byte.
753 logic.unitsize = devc->model->series->protocol >= PROTOCOL_V4 ? 1 : 2;
754 logic.data = devc->buffer;
755 packet.type = SR_DF_LOGIC;
756 packet.payload = &logic;
757 sr_session_send(sdi, &packet);
760 if (devc->num_block_read == devc->num_block_bytes) {
761 sr_dbg("Block has been completed");
762 if (devc->model->series->protocol >= PROTOCOL_V3) {
763 /* Discard the terminating linefeed */
764 sr_scpi_read_data(scpi, (char *)devc->buffer, 1);
766 if (devc->format == FORMAT_IEEE488_2) {
767 /* Prepare for possible next block */
768 devc->num_header_bytes = 0;
769 devc->num_block_bytes = 0;
770 if (devc->data_source != DATA_SOURCE_LIVE)
771 rigol_ds_set_wait_event(devc, WAIT_BLOCK);
773 if (!sr_scpi_read_complete(scpi) && !devc->channel_entry->next) {
774 sr_err("Read should have been completed");
776 devc->num_block_read = 0;
778 sr_dbg("%" PRIu64 " of %" PRIu64 " block bytes read",
779 devc->num_block_read, devc->num_block_bytes);
782 devc->num_channel_bytes += len;
784 if (devc->num_channel_bytes < expected_data_bytes)
785 /* Don't have the full data for this channel yet, re-run. */
788 /* End of data for this channel. */
789 if (devc->model->series->protocol == PROTOCOL_V3) {
790 /* Signal end of data download to scope */
791 if (devc->data_source != DATA_SOURCE_LIVE)
793 * This causes a query error, without it switching
794 * to the next channel causes an error. Fun with
797 rigol_ds_config_set(sdi, ":WAV:END");
800 if (devc->channel_entry->next) {
801 /* We got the frame for this channel, now get the next channel. */
802 devc->channel_entry = devc->channel_entry->next;
803 rigol_ds_channel_start(sdi);
805 /* Done with this frame. */
806 std_session_send_df_frame_end(sdi);
808 if (++devc->num_frames == devc->limit_frames ||
809 devc->num_frames == devc->num_frames_segmented ||
810 devc->data_source == DATA_SOURCE_MEMORY) {
811 /* Last frame, stop capture. */
812 sr_dev_acquisition_stop(sdi);
814 /* Get the next frame, starting with the first channel. */
815 devc->channel_entry = devc->enabled_channels;
817 rigol_ds_capture_start(sdi);
819 /* Start of next frame. */
820 std_session_send_df_frame_begin(sdi);
827 SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi)
829 struct dev_context *devc;
830 struct sr_channel *ch;
837 /* Analog channel state. */
838 for (i = 0; i < devc->model->analog_channels; i++) {
839 cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1);
840 res = sr_scpi_get_bool(sdi->conn, cmd, &devc->analog_channels[i]);
844 ch = g_slist_nth_data(sdi->channels, i);
845 ch->enabled = devc->analog_channels[i];
847 sr_dbg("Current analog channel state:");
848 for (i = 0; i < devc->model->analog_channels; i++)
849 sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off");
851 /* Digital channel state. */
852 if (devc->model->has_digital) {
853 if (sr_scpi_get_bool(sdi->conn,
854 devc->model->series->protocol >= PROTOCOL_V3 ?
855 ":LA:STAT?" : ":LA:DISP?",
856 &devc->la_enabled) != SR_OK)
858 sr_dbg("Logic analyzer %s, current digital channel state:",
859 devc->la_enabled ? "enabled" : "disabled");
860 for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
861 if (devc->model->series->protocol >= PROTOCOL_V5)
862 cmd = g_strdup_printf(":LA:DISP? D%d", i);
863 else if (devc->model->series->protocol >= PROTOCOL_V3)
864 cmd = g_strdup_printf(":LA:DIG%d:DISP?", i);
866 cmd = g_strdup_printf(":DIG%d:TURN?", i);
867 res = sr_scpi_get_bool(sdi->conn, cmd, &devc->digital_channels[i]);
871 ch = g_slist_nth_data(sdi->channels, i + devc->model->analog_channels);
872 ch->enabled = devc->digital_channels[i];
873 sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off");
878 if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK)
880 sr_dbg("Current timebase %g", devc->timebase);
882 /* Probe attenuation. */
883 for (i = 0; i < devc->model->analog_channels; i++) {
884 cmd = g_strdup_printf(":CHAN%d:PROB?", i + 1);
885 res = sr_scpi_get_float(sdi->conn, cmd, &devc->attenuation[i]);
890 sr_dbg("Current probe attenuation:");
891 for (i = 0; i < devc->model->analog_channels; i++)
892 sr_dbg("CH%d %g", i + 1, devc->attenuation[i]);
894 /* Vertical gain and offset. */
895 if (rigol_ds_get_dev_cfg_vertical(sdi) != SR_OK)
899 for (i = 0; i < devc->model->analog_channels; i++) {
900 cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1);
901 res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]);
906 sr_dbg("Current coupling:");
907 for (i = 0; i < devc->model->analog_channels; i++)
908 sr_dbg("CH%d %s", i + 1, devc->coupling[i]);
910 /* Trigger source. */
911 if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK)
913 sr_dbg("Current trigger source %s", devc->trigger_source);
915 /* Horizontal trigger position. */
916 if (sr_scpi_get_float(sdi->conn, devc->model->cmds[CMD_GET_HORIZ_TRIGGERPOS].str,
917 &devc->horiz_triggerpos) != SR_OK)
919 sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos);
922 if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK)
924 sr_dbg("Current trigger slope %s", devc->trigger_slope);
927 if (sr_scpi_get_float(sdi->conn, ":TRIG:EDGE:LEV?", &devc->trigger_level) != SR_OK)
929 sr_dbg("Current trigger level %g", devc->trigger_level);
934 SR_PRIV int rigol_ds_get_dev_cfg_vertical(const struct sr_dev_inst *sdi)
936 struct dev_context *devc;
944 for (i = 0; i < devc->model->analog_channels; i++) {
945 cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1);
946 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]);
951 sr_dbg("Current vertical gain:");
952 for (i = 0; i < devc->model->analog_channels; i++)
953 sr_dbg("CH%d %g", i + 1, devc->vdiv[i]);
955 /* Vertical offset. */
956 for (i = 0; i < devc->model->analog_channels; i++) {
957 cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1);
958 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]);
963 sr_dbg("Current vertical offset:");
964 for (i = 0; i < devc->model->analog_channels; i++)
965 sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]);