src/hardware/rigol-ds/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
   5  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   6  * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 3 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <config.h>
  23 #include <stdlib.h>
  24 #include <stdarg.h>
  25 #include <unistd.h>
  26 #include <errno.h>
  27 #include <string.h>
  28 #include <math.h>
  29 #include <ctype.h>
  30 #include <time.h>
  31 #include <glib.h>
  32 #include <libsigrok/libsigrok.h>
  33 #include "libsigrok-internal.h"
  34 #include "scpi.h"
  35 #include "protocol.h"
  36
  37 /*
  38  * This is a unified protocol driver for the DS1000 and DS2000 series.
  39  *
  40  * DS1000 support tested with a Rigol DS1102D.
  41  *
  42  * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02.
  43  *
  44  * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think)
  45  * standard. If you want to read it - it costs real money...
  46  *
  47  * Every response from the scope has a linefeed appended because the
  48  * standard says so. In principle this could be ignored because sending the
  49  * next command clears the output queue of the scope. This driver tries to
  50  * avoid doing that because it may cause an error being generated inside the
  51  * scope and who knows what bugs the firmware has WRT this.
  52  *
  53  * Waveform data is transferred in a format called "arbitrary block program
  54  * data" specified in IEEE 488.2. See Agilents programming manuals for their
  55  * 2000/3000 series scopes for a nice description.
  56  *
  57  * Each data block from the scope has a header, e.g. "#900000001400".
  58  * The '#' marks the start of a block.
  59  * Next is one ASCII decimal digit between 1 and 9, this gives the number of
  60  * ASCII decimal digits following.
  61  * Last are the ASCII decimal digits giving the number of bytes (not
  62  * samples!) in the block.
  63  *
  64  * After this header as many data bytes as indicated follow.
  65  *
  66  * Each data block has a trailing linefeed too.
  67  */
  68
  69 static int parse_int(const char *str, int *ret)
  70 {
  71         char *e;
  72         long tmp;
  73
  74         errno = 0;
  75         tmp = strtol(str, &e, 10);
  76         if (e == str || *e != '\0') {
  77                 sr_dbg("Failed to parse integer: '%s'", str);
  78                 return SR_ERR;
  79         }
  80         if (errno) {
  81                 sr_dbg("Failed to parse integer: '%s', numerical overflow", str);
  82                 return SR_ERR;
  83         }
  84         if (tmp > INT_MAX || tmp < INT_MIN) {
  85                 sr_dbg("Failed to parse integer: '%s', value to large/small", str);
  86                 return SR_ERR;
  87         }
  88
  89         *ret = (int)tmp;
  90         return SR_OK;
  91 }
  92
  93 /* Set the next event to wait for in rigol_ds_receive */
  94 static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event)
  95 {
  96         if (event == WAIT_STOP)
  97                 devc->wait_status = 2;
  98         else
  99                 devc->wait_status = 1;
 100         devc->wait_event = event;
 101 }
 102
 103 /*
 104  * Waiting for a event will return a timeout after 2 to 3 seconds in order
 105  * to not block the application.
 106  */
 107 static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2)
 108 {
 109         char *buf;
 110         struct dev_context *devc;
 111         time_t start;
 112
 113         if (!(devc = sdi->priv))
 114                 return SR_ERR;
 115
 116         start = time(NULL);
 117
 118         /*
 119          * Trigger status may return:
 120          * "TD" or "T'D" - triggered
 121          * "AUTO"        - autotriggered
 122          * "RUN"         - running
 123          * "WAIT"        - waiting for trigger
 124          * "STOP"        - stopped
 125          */
 126
 127         if (devc->wait_status == 1) {
 128                 do {
 129                         if (time(NULL) - start >= 3) {
 130                                 sr_dbg("Timeout waiting for trigger");
 131                                 return SR_ERR_TIMEOUT;
 132                         }
 133
 134                         if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
 135                                 return SR_ERR;
 136                 } while (buf[0] == status1 || buf[0] == status2);
 137
 138                 devc->wait_status = 2;
 139         }
 140         if (devc->wait_status == 2) {
 141                 do {
 142                         if (time(NULL) - start >= 3) {
 143                                 sr_dbg("Timeout waiting for trigger");
 144                                 return SR_ERR_TIMEOUT;
 145                         }
 146
 147                         if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
 148                                 return SR_ERR;
 149                 } while (buf[0] != status1 && buf[0] != status2);
 150
 151                 rigol_ds_set_wait_event(devc, WAIT_NONE);
 152         }
 153
 154         return SR_OK;
 155 }
 156
 157 /*
 158  * For live capture we need to wait for a new trigger event to ensure that
 159  * sample data is not returned twice.
 160  *
 161  * Unfortunately this will never really work because for sufficiently fast
 162  * timebases and trigger rates it just can't catch the status changes.
 163  *
 164  * What would be needed is a trigger event register with autoreset like the
 165  * Agilents have. The Rigols don't seem to have anything like this.
 166  *
 167  * The workaround is to only wait for the trigger when the timebase is slow
 168  * enough. Of course this means that for faster timebases sample data can be
 169  * returned multiple times, this effect is mitigated somewhat by sleeping
 170  * for about one sweep time in that case.
 171  */
 172 static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi)
 173 {
 174         struct dev_context *devc;
 175         long s;
 176
 177         if (!(devc = sdi->priv))
 178                 return SR_ERR;
 179
 180         /*
 181          * If timebase < 50 msecs/DIV just sleep about one sweep time except
 182          * for really fast sweeps.
 183          */
 184         if (devc->timebase < 0.0499) {
 185                 if (devc->timebase > 0.99e-6) {
 186                         /*
 187                          * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100
 188                          * -> 85 percent of sweep time
 189                          */
 190                         s = (devc->timebase * devc->model->series->num_horizontal_divs
 191                              * 85e6) / 100L;
 192                         sr_spew("Sleeping for %ld usecs instead of trigger-wait", s);
 193                         g_usleep(s);
 194                 }
 195                 rigol_ds_set_wait_event(devc, WAIT_NONE);
 196                 return SR_OK;
 197         } else {
 198                 return rigol_ds_event_wait(sdi, 'T', 'A');
 199         }
 200 }
 201
 202 /* Wait for scope to got to "Stop" in single shot mode */
 203 static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi)
 204 {
 205         return rigol_ds_event_wait(sdi, 'S', 'S');
 206 }
 207
 208 /* Check that a single shot acquisition actually succeeded on the DS2000 */
 209 static int rigol_ds_check_stop(const struct sr_dev_inst *sdi)
 210 {
 211         struct dev_context *devc;
 212         struct sr_channel *ch;
 213         int tmp;
 214
 215         if (!(devc = sdi->priv))
 216                 return SR_ERR;
 217
 218         ch = devc->channel_entry->data;
 219
 220         if (devc->model->series->protocol != PROTOCOL_V3)
 221                 return SR_OK;
 222
 223         if (ch->type == SR_CHANNEL_LOGIC) {
 224                 if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK)
 225                         return SR_ERR;
 226         } else {
 227                 if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
 228                                 ch->index + 1) != SR_OK)
 229                         return SR_ERR;
 230         }
 231         /* Check that the number of samples will be accepted */
 232         if (rigol_ds_config_set(sdi, ":WAV:POIN %d",
 233                         ch->type == SR_CHANNEL_LOGIC ?
 234                                 devc->digital_frame_size :
 235                                 devc->analog_frame_size) != SR_OK)
 236                 return SR_ERR;
 237         if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK)
 238                 return SR_ERR;
 239         /*
 240          * If we get an "Execution error" the scope went from "Single" to
 241          * "Stop" without actually triggering. There is no waveform
 242          * displayed and trying to download one will fail - the scope thinks
 243          * it has 1400 samples (like display memory) and the driver thinks
 244          * it has a different number of samples.
 245          *
 246          * In that case just try to capture something again. Might still
 247          * fail in interesting ways.
 248          *
 249          * Ain't firmware fun?
 250          */
 251         if (tmp & 0x10) {
 252                 sr_warn("Single shot acquisition failed, retrying...");
 253                 /* Sleep a bit, otherwise the single shot will often fail */
 254                 g_usleep(500 * 1000);
 255                 rigol_ds_config_set(sdi, ":SING");
 256                 rigol_ds_set_wait_event(devc, WAIT_STOP);
 257                 return SR_ERR;
 258         }
 259
 260         return SR_OK;
 261 }
 262
 263 /* Wait for enough data becoming available in scope output buffer */
 264 static int rigol_ds_block_wait(const struct sr_dev_inst *sdi)
 265 {
 266         char *buf;
 267         struct dev_context *devc;
 268         time_t start;
 269         int len;
 270
 271         if (!(devc = sdi->priv))
 272                 return SR_ERR;
 273
 274         if (devc->model->series->protocol == PROTOCOL_V3) {
 275
 276                 start = time(NULL);
 277
 278                 do {
 279                         if (time(NULL) - start >= 3) {
 280                                 sr_dbg("Timeout waiting for data block");
 281                                 return SR_ERR_TIMEOUT;
 282                         }
 283
 284                         /*
 285                          * The scope copies data really slowly from sample
 286                          * memory to its output buffer, so try not to bother
 287                          * it too much with SCPI requests but don't wait too
 288                          * long for short sample frame sizes.
 289                          */
 290                         g_usleep(devc->analog_frame_size < (15 * 1000) ? (100 * 1000) : (1000 * 1000));
 291
 292                         /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */
 293                         if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK)
 294                                 return SR_ERR;
 295
 296                         if (parse_int(buf + 5, &len) != SR_OK)
 297                                 return SR_ERR;
 298                 } while (buf[0] == 'R' && len < (1000 * 1000));
 299         }
 300
 301         rigol_ds_set_wait_event(devc, WAIT_NONE);
 302
 303         return SR_OK;
 304 }
 305
 306 /* Send a configuration setting. */
 307 SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...)
 308 {
 309         struct dev_context *devc = sdi->priv;
 310         va_list args;
 311         int ret;
 312
 313         va_start(args, format);
 314         ret = sr_scpi_send_variadic(sdi->conn, format, args);
 315         va_end(args);
 316
 317         if (ret != SR_OK)
 318                 return SR_ERR;
 319
 320         if (devc->model->series->protocol == PROTOCOL_V2) {
 321                 /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */
 322                 sr_spew("delay %dms", 100);
 323                 g_usleep(100 * 1000);
 324                 return SR_OK;
 325         } else {
 326                 return sr_scpi_get_opc(sdi->conn);
 327         }
 328 }
 329
 330 /* Start capturing a new frameset */
 331 SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
 332 {
 333         struct dev_context *devc;
 334         gchar *trig_mode;
 335         unsigned int num_channels, i, j;
 336         int buffer_samples;
 337
 338         if (!(devc = sdi->priv))
 339                 return SR_ERR;
 340
 341         if (devc->limit_frames == 0)
 342                 sr_dbg("Starting data capture for frameset %" PRIu64,
 343                        devc->num_frames + 1);
 344         else
 345                 sr_dbg("Starting data capture for frameset %" PRIu64 " of %"
 346                        PRIu64, devc->num_frames + 1, devc->limit_frames);
 347
 348         switch (devc->model->series->protocol) {
 349         case PROTOCOL_V1:
 350                 rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
 351                 break;
 352         case PROTOCOL_V2:
 353                 if (devc->data_source == DATA_SOURCE_LIVE) {
 354                         if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK)
 355                                 return SR_ERR;
 356                         rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
 357                 } else {
 358                         if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
 359                                 return SR_ERR;
 360                         if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK)
 361                                 return SR_ERR;
 362                         if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK)
 363                                 return SR_ERR;
 364                         if (rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode) != SR_OK)
 365                                 return SR_ERR;
 366                         if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
 367                                 return SR_ERR;
 368                         rigol_ds_set_wait_event(devc, WAIT_STOP);
 369                 }
 370                 break;
 371         case PROTOCOL_V3:
 372         case PROTOCOL_V4:
 373         case PROTOCOL_V5:
 374                 if (rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK)
 375                         return SR_ERR;
 376                 if (devc->data_source == DATA_SOURCE_LIVE) {
 377                         if (rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK)
 378                                 return SR_ERR;
 379                         devc->analog_frame_size = devc->model->series->live_samples;
 380                         devc->digital_frame_size = devc->model->series->live_samples;
 381                         rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
 382                 } else {
 383                         if (devc->model->series->protocol == PROTOCOL_V3) {
 384                                 if (rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK)
 385                                         return SR_ERR;
 386                         } else if (devc->model->series->protocol >= PROTOCOL_V4) {
 387                                 num_channels = 0;
 388
 389                                 /* Channels 3 and 4 are multiplexed with D0-7 and D8-15 */
 390                                 for (i = 0; i < devc->model->analog_channels; i++) {
 391                                         if (devc->analog_channels[i]) {
 392                                                 num_channels++;
 393                                         } else if (i >= 2 && devc->model->has_digital) {
 394                                                 for (j = 0; j < 8; j++) {
 395                                                         if (devc->digital_channels[8 * (i - 2) + j]) {
 396                                                                 num_channels++;
 397                                                                 break;
 398                                                         }
 399                                                 }
 400                                         }
 401                                 }
 402
 403                                 buffer_samples = devc->model->series->buffer_samples;
 404                                 if (buffer_samples == 0)
 405                                 {
 406                                         /* The DS4000 series does not have a fixed memory depth, it
 407                                          * can be chosen from the menu and also varies with number
 408                                          * of active channels. Retrieve the actual number with the
 409                                          * ACQ:MDEP command. */
 410                                         sr_scpi_get_int(sdi->conn, "ACQ:MDEP?", &buffer_samples);
 411                                         devc->analog_frame_size = devc->digital_frame_size =
 412                                                         buffer_samples;
 413                                 }
 414                                 else
 415                                 {
 416                                         /* The DS1000Z series has a fixed memory depth which we
 417                                          * need to divide correctly according to the number of
 418                                          * active channels. */
 419                                         devc->analog_frame_size = devc->digital_frame_size =
 420                                                 num_channels == 1 ?
 421                                                         buffer_samples :
 422                                                                 num_channels == 2 ?
 423                                                                         buffer_samples / 2 :
 424                                                                         buffer_samples / 4;
 425                                 }
 426                         }
 427
 428                         if (rigol_ds_config_set(sdi, ":SING") != SR_OK)
 429                                 return SR_ERR;
 430                         rigol_ds_set_wait_event(devc, WAIT_STOP);
 431                 }
 432                 break;
 433         }
 434
 435         return SR_OK;
 436 }
 437
 438 /* Start reading data from the current channel */
 439 SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi)
 440 {
 441         struct dev_context *devc;
 442         struct sr_channel *ch;
 443
 444         if (!(devc = sdi->priv))
 445                 return SR_ERR;
 446
 447         ch = devc->channel_entry->data;
 448
 449         sr_dbg("Starting reading data from channel %d", ch->index + 1);
 450
 451         switch (devc->model->series->protocol) {
 452         case PROTOCOL_V1:
 453         case PROTOCOL_V2:
 454                 if (ch->type == SR_CHANNEL_LOGIC) {
 455                         if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK)
 456                                 return SR_ERR;
 457                 } else {
 458                         if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d",
 459                                         ch->index + 1) != SR_OK)
 460                                 return SR_ERR;
 461                 }
 462                 rigol_ds_set_wait_event(devc, WAIT_NONE);
 463                 break;
 464         case PROTOCOL_V3:
 465                 if (ch->type == SR_CHANNEL_LOGIC) {
 466                         if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK)
 467                                 return SR_ERR;
 468                 } else {
 469                         if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
 470                                         ch->index + 1) != SR_OK)
 471                                 return SR_ERR;
 472                 }
 473                 if (devc->data_source != DATA_SOURCE_LIVE) {
 474                         if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
 475                                 return SR_ERR;
 476                         if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
 477                                 return SR_ERR;
 478                 }
 479                 break;
 480         case PROTOCOL_V4:
 481         case PROTOCOL_V5:
 482                 if (ch->type == SR_CHANNEL_ANALOG) {
 483                         if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
 484                                         ch->index + 1) != SR_OK)
 485                                 return SR_ERR;
 486                 } else {
 487                         if (rigol_ds_config_set(sdi, ":WAV:SOUR D%d",
 488                                         ch->index) != SR_OK)
 489                                 return SR_ERR;
 490                 }
 491
 492                 if (rigol_ds_config_set(sdi,
 493                                         devc->data_source == DATA_SOURCE_LIVE ?
 494                                                 ":WAV:MODE NORM" :":WAV:MODE RAW") != SR_OK)
 495                         return SR_ERR;
 496                 break;
 497         }
 498
 499         if (devc->model->series->protocol >= PROTOCOL_V3 &&
 500                         ch->type == SR_CHANNEL_ANALOG) {
 501                 /* Vertical increment. */
 502                 if (sr_scpi_get_float(sdi->conn, ":WAV:YINC?",
 503                                 &devc->vert_inc[ch->index]) != SR_OK)
 504                         return SR_ERR;
 505                 /* Vertical origin. */
 506                 if (sr_scpi_get_float(sdi->conn, ":WAV:YOR?",
 507                         &devc->vert_origin[ch->index]) != SR_OK)
 508                         return SR_ERR;
 509                 /* Vertical reference. */
 510                 if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?",
 511                                 &devc->vert_reference[ch->index]) != SR_OK)
 512                         return SR_ERR;
 513         } else if (ch->type == SR_CHANNEL_ANALOG) {
 514                 devc->vert_inc[ch->index] = devc->vdiv[ch->index] / 25.6;
 515         }
 516
 517         rigol_ds_set_wait_event(devc, WAIT_BLOCK);
 518
 519         devc->num_channel_bytes = 0;
 520         devc->num_header_bytes = 0;
 521         devc->num_block_bytes = 0;
 522
 523         return SR_OK;
 524 }
 525
 526 /* Read the header of a data block */
 527 static int rigol_ds_read_header(struct sr_dev_inst *sdi)
 528 {
 529         struct sr_scpi_dev_inst *scpi = sdi->conn;
 530         struct dev_context *devc = sdi->priv;
 531         char *buf = (char *) devc->buffer;
 532         size_t header_length;
 533         int ret;
 534
 535         /* Try to read the hashsign and length digit. */
 536         if (devc->num_header_bytes < 2) {
 537                 ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes,
 538                                 2 - devc->num_header_bytes);
 539                 if (ret < 0) {
 540                         sr_err("Read error while reading data header.");
 541                         return SR_ERR;
 542                 }
 543                 devc->num_header_bytes += ret;
 544         }
 545
 546         if (devc->num_header_bytes < 2)
 547                 return 0;
 548
 549         if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') {
 550                 sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]);
 551                 return SR_ERR;
 552         }
 553
 554         header_length = 2 + buf[1] - '0';
 555
 556         /* Try to read the length. */
 557         if (devc->num_header_bytes < header_length) {
 558                 ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes,
 559                                 header_length - devc->num_header_bytes);
 560                 if (ret < 0) {
 561                         sr_err("Read error while reading data header.");
 562                         return SR_ERR;
 563                 }
 564                 devc->num_header_bytes += ret;
 565         }
 566
 567         if (devc->num_header_bytes < header_length)
 568                 return 0;
 569
 570         /* Read the data length. */
 571         buf[header_length] = '\0';
 572
 573         if (parse_int(buf + 2, &ret) != SR_OK) {
 574                 sr_err("Received invalid data block length '%s'.", buf + 2);
 575                 return -1;
 576         }
 577
 578         sr_dbg("Received data block header: '%s' -> block length %d", buf, ret);
 579
 580         return ret;
 581 }
 582
 583 SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data)
 584 {
 585         struct sr_dev_inst *sdi;
 586         struct sr_scpi_dev_inst *scpi;
 587         struct dev_context *devc;
 588         struct sr_datafeed_packet packet;
 589         struct sr_datafeed_analog analog;
 590         struct sr_analog_encoding encoding;
 591         struct sr_analog_meaning meaning;
 592         struct sr_analog_spec spec;
 593         struct sr_datafeed_logic logic;
 594         double vdiv, offset, origin;
 595         int len, i, vref;
 596         struct sr_channel *ch;
 597         gsize expected_data_bytes;
 598
 599         (void)fd;
 600
 601         if (!(sdi = cb_data))
 602                 return TRUE;
 603
 604         if (!(devc = sdi->priv))
 605                 return TRUE;
 606
 607         scpi = sdi->conn;
 608
 609         if (!(revents == G_IO_IN || revents == 0))
 610                 return TRUE;
 611
 612         switch (devc->wait_event) {
 613         case WAIT_NONE:
 614                 break;
 615         case WAIT_TRIGGER:
 616                 if (rigol_ds_trigger_wait(sdi) != SR_OK)
 617                         return TRUE;
 618                 if (rigol_ds_channel_start(sdi) != SR_OK)
 619                         return TRUE;
 620                 return TRUE;
 621         case WAIT_BLOCK:
 622                 if (rigol_ds_block_wait(sdi) != SR_OK)
 623                         return TRUE;
 624                 break;
 625         case WAIT_STOP:
 626                 if (rigol_ds_stop_wait(sdi) != SR_OK)
 627                         return TRUE;
 628                 if (rigol_ds_check_stop(sdi) != SR_OK)
 629                         return TRUE;
 630                 if (rigol_ds_channel_start(sdi) != SR_OK)
 631                         return TRUE;
 632                 return TRUE;
 633         default:
 634                 sr_err("BUG: Unknown event target encountered");
 635                 break;
 636         }
 637
 638         ch = devc->channel_entry->data;
 639
 640         expected_data_bytes = ch->type == SR_CHANNEL_ANALOG ?
 641                         devc->analog_frame_size : devc->digital_frame_size;
 642
 643         if (devc->num_block_bytes == 0) {
 644                 if (devc->model->series->protocol >= PROTOCOL_V4) {
 645                         if (rigol_ds_config_set(sdi, ":WAV:START %d",
 646                                         devc->num_channel_bytes + 1) != SR_OK)
 647                                 return TRUE;
 648                         if (rigol_ds_config_set(sdi, ":WAV:STOP %d",
 649                                         MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE,
 650                                                 devc->analog_frame_size)) != SR_OK)
 651                                 return TRUE;
 652                 }
 653
 654                 if (devc->model->series->protocol >= PROTOCOL_V3)
 655                         if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK)
 656                                 return TRUE;
 657
 658                 if (sr_scpi_read_begin(scpi) != SR_OK)
 659                         return TRUE;
 660
 661                 if (devc->format == FORMAT_IEEE488_2) {
 662                         sr_dbg("New block header expected");
 663                         len = rigol_ds_read_header(sdi);
 664                         if (len == 0)
 665                                 /* Still reading the header. */
 666                                 return TRUE;
 667                         if (len == -1) {
 668                                 sr_err("Error while reading block header, aborting capture.");
 669                                 std_session_send_df_frame_end(sdi);
 670                                 sr_dev_acquisition_stop(sdi);
 671                                 return TRUE;
 672                         }
 673                         /* At slow timebases in live capture the DS2072
 674                          * sometimes returns "short" data blocks, with
 675                          * apparently no way to get the rest of the data.
 676                          * Discard these, the complete data block will
 677                          * appear eventually.
 678                          */
 679                         if (devc->data_source == DATA_SOURCE_LIVE
 680                                         && (unsigned)len < expected_data_bytes) {
 681                                 sr_dbg("Discarding short data block");
 682                                 sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1);
 683                                 return TRUE;
 684                         }
 685                         devc->num_block_bytes = len;
 686                 } else {
 687                         devc->num_block_bytes = expected_data_bytes;
 688                 }
 689                 devc->num_block_read = 0;
 690         }
 691
 692         len = devc->num_block_bytes - devc->num_block_read;
 693         if (len > ACQ_BUFFER_SIZE)
 694                 len = ACQ_BUFFER_SIZE;
 695         sr_dbg("Requesting read of %d bytes", len);
 696
 697         len = sr_scpi_read_data(scpi, (char *)devc->buffer, len);
 698
 699         if (len == -1) {
 700                 sr_err("Error while reading block data, aborting capture.");
 701                 std_session_send_df_frame_end(sdi);
 702                 sr_dev_acquisition_stop(sdi);
 703                 return TRUE;
 704         }
 705
 706         sr_dbg("Received %d bytes.", len);
 707
 708         devc->num_block_read += len;
 709
 710         if (ch->type == SR_CHANNEL_ANALOG) {
 711                 vref = devc->vert_reference[ch->index];
 712                 vdiv = devc->vert_inc[ch->index];
 713                 origin = devc->vert_origin[ch->index];
 714                 offset = devc->vert_offset[ch->index];
 715                 if (devc->model->series->protocol >= PROTOCOL_V3)
 716                         for (i = 0; i < len; i++)
 717                                 devc->data[i] = ((int)devc->buffer[i] - vref - origin) * vdiv;
 718                 else
 719                         for (i = 0; i < len; i++)
 720                                 devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset;
 721                 float vdivlog = log10f(vdiv);
 722                 int digits = -(int)vdivlog + (vdivlog < 0.0);
 723                 sr_analog_init(&analog, &encoding, &meaning, &spec, digits);
 724                 analog.meaning->channels = g_slist_append(NULL, ch);
 725                 analog.num_samples = len;
 726                 analog.data = devc->data;
 727                 analog.meaning->mq = SR_MQ_VOLTAGE;
 728                 analog.meaning->unit = SR_UNIT_VOLT;
 729                 analog.meaning->mqflags = 0;
 730                 packet.type = SR_DF_ANALOG;
 731                 packet.payload = &analog;
 732                 sr_session_send(sdi, &packet);
 733                 g_slist_free(analog.meaning->channels);
 734         } else {
 735                 logic.length = len;
 736                 // TODO: For the MSO1000Z series, we need a way to express that
 737                 // this data is in fact just for a single channel, with the valid
 738                 // data for that channel in the LSB of each byte.
 739                 logic.unitsize = devc->model->series->protocol >= PROTOCOL_V4 ? 1 : 2;
 740                 logic.data = devc->buffer;
 741                 packet.type = SR_DF_LOGIC;
 742                 packet.payload = &logic;
 743                 sr_session_send(sdi, &packet);
 744         }
 745
 746         if (devc->num_block_read == devc->num_block_bytes) {
 747                 sr_dbg("Block has been completed");
 748                 if (devc->model->series->protocol >= PROTOCOL_V3) {
 749                         /* Discard the terminating linefeed */
 750                         sr_scpi_read_data(scpi, (char *)devc->buffer, 1);
 751                 }
 752                 if (devc->format == FORMAT_IEEE488_2) {
 753                         /* Prepare for possible next block */
 754                         devc->num_header_bytes = 0;
 755                         devc->num_block_bytes = 0;
 756                         if (devc->data_source != DATA_SOURCE_LIVE)
 757                                 rigol_ds_set_wait_event(devc, WAIT_BLOCK);
 758                 }
 759                 /* End acquisition when data for all channels is acquired. */
 760                 if (!sr_scpi_read_complete(scpi) && !devc->channel_entry->next) {
 761                         sr_err("Read should have been completed");
 762                         std_session_send_df_frame_end(sdi);
 763                         sr_dev_acquisition_stop(sdi);
 764                         return TRUE;
 765                 }
 766                 devc->num_block_read = 0;
 767         } else {
 768                 sr_dbg("%" PRIu64 " of %" PRIu64 " block bytes read",
 769                         devc->num_block_read, devc->num_block_bytes);
 770         }
 771
 772         devc->num_channel_bytes += len;
 773
 774         if (devc->num_channel_bytes < expected_data_bytes)
 775                 /* Don't have the full data for this channel yet, re-run. */
 776                 return TRUE;
 777
 778         /* End of data for this channel. */
 779         if (devc->model->series->protocol == PROTOCOL_V3) {
 780                 /* Signal end of data download to scope */
 781                 if (devc->data_source != DATA_SOURCE_LIVE)
 782                         /*
 783                          * This causes a query error, without it switching
 784                          * to the next channel causes an error. Fun with
 785                          * firmware...
 786                          */
 787                         rigol_ds_config_set(sdi, ":WAV:END");
 788         }
 789
 790         if (devc->channel_entry->next) {
 791                 /* We got the frame for this channel, now get the next channel. */
 792                 devc->channel_entry = devc->channel_entry->next;
 793                 rigol_ds_channel_start(sdi);
 794         } else {
 795                 /* Done with this frame. */
 796                 std_session_send_df_frame_end(sdi);
 797
 798                 if (++devc->num_frames == devc->limit_frames) {
 799                         /* Last frame, stop capture. */
 800                         sr_dev_acquisition_stop(sdi);
 801                 } else {
 802                         /* Get the next frame, starting with the first channel. */
 803                         devc->channel_entry = devc->enabled_channels;
 804
 805                         rigol_ds_capture_start(sdi);
 806
 807                         /* Start of next frame. */
 808                         std_session_send_df_frame_begin(sdi);
 809                 }
 810         }
 811
 812         return TRUE;
 813 }
 814
 815 SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi)
 816 {
 817         struct dev_context *devc;
 818         struct sr_channel *ch;
 819         char *cmd;
 820         unsigned int i;
 821         int res;
 822
 823         devc = sdi->priv;
 824
 825         /* Analog channel state. */
 826         for (i = 0; i < devc->model->analog_channels; i++) {
 827                 cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1);
 828                 res = sr_scpi_get_bool(sdi->conn, cmd, &devc->analog_channels[i]);
 829                 g_free(cmd);
 830                 if (res != SR_OK)
 831                         return SR_ERR;
 832                 ch = g_slist_nth_data(sdi->channels, i);
 833                 ch->enabled = devc->analog_channels[i];
 834         }
 835         sr_dbg("Current analog channel state:");
 836         for (i = 0; i < devc->model->analog_channels; i++)
 837                 sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off");
 838
 839         /* Digital channel state. */
 840         if (devc->model->has_digital) {
 841                 if (sr_scpi_get_bool(sdi->conn,
 842                                 devc->model->series->protocol >= PROTOCOL_V3 ?
 843                                         ":LA:STAT?" : ":LA:DISP?",
 844                                 &devc->la_enabled) != SR_OK)
 845                         return SR_ERR;
 846                 sr_dbg("Logic analyzer %s, current digital channel state:",
 847                                 devc->la_enabled ? "enabled" : "disabled");
 848                 for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
 849                         if (devc->model->series->protocol >= PROTOCOL_V5)
 850                                 cmd = g_strdup_printf(":LA:DISP? D%d", i);
 851                         else if (devc->model->series->protocol >= PROTOCOL_V3)
 852                                 cmd = g_strdup_printf(":LA:DIG%d:DISP?", i);
 853                         else
 854                                 cmd = g_strdup_printf(":DIG%d:TURN?", i);
 855                         res = sr_scpi_get_bool(sdi->conn, cmd, &devc->digital_channels[i]);
 856                         g_free(cmd);
 857                         if (res != SR_OK)
 858                                 return SR_ERR;
 859                         ch = g_slist_nth_data(sdi->channels, i + devc->model->analog_channels);
 860                         ch->enabled = devc->digital_channels[i];
 861                         sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off");
 862                 }
 863         }
 864
 865         /* Timebase. */
 866         if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK)
 867                 return SR_ERR;
 868         sr_dbg("Current timebase %g", devc->timebase);
 869
 870         /* Probe attenuation. */
 871         for (i = 0; i < devc->model->analog_channels; i++) {
 872                 cmd = g_strdup_printf(":CHAN%d:PROB?", i + 1);
 873                 res = sr_scpi_get_float(sdi->conn, cmd, &devc->attenuation[i]);
 874                 g_free(cmd);
 875                 if (res != SR_OK)
 876                         return SR_ERR;
 877         }
 878         sr_dbg("Current probe attenuation:");
 879         for (i = 0; i < devc->model->analog_channels; i++)
 880                 sr_dbg("CH%d %g", i + 1, devc->attenuation[i]);
 881
 882         /* Vertical gain and offset. */
 883         if (rigol_ds_get_dev_cfg_vertical(sdi) != SR_OK)
 884                 return SR_ERR;
 885
 886         /* Coupling. */
 887         for (i = 0; i < devc->model->analog_channels; i++) {
 888                 cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1);
 889                 res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]);
 890                 g_free(cmd);
 891                 if (res != SR_OK)
 892                         return SR_ERR;
 893         }
 894         sr_dbg("Current coupling:");
 895         for (i = 0; i < devc->model->analog_channels; i++)
 896                 sr_dbg("CH%d %s", i + 1, devc->coupling[i]);
 897
 898         /* Trigger source. */
 899         if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK)
 900                 return SR_ERR;
 901         sr_dbg("Current trigger source %s", devc->trigger_source);
 902
 903         /* Horizontal trigger position. */
 904         if (sr_scpi_get_float(sdi->conn, devc->model->cmds[CMD_GET_HORIZ_TRIGGERPOS].str,
 905                         &devc->horiz_triggerpos) != SR_OK)
 906                 return SR_ERR;
 907         sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos);
 908
 909         /* Trigger slope. */
 910         if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK)
 911                 return SR_ERR;
 912         sr_dbg("Current trigger slope %s", devc->trigger_slope);
 913
 914         /* Trigger level. */
 915         if (sr_scpi_get_float(sdi->conn, ":TRIG:EDGE:LEV?", &devc->trigger_level) != SR_OK)
 916                 return SR_ERR;
 917         sr_dbg("Current trigger level %g", devc->trigger_level);
 918
 919         return SR_OK;
 920 }
 921
 922 SR_PRIV int rigol_ds_get_dev_cfg_vertical(const struct sr_dev_inst *sdi)
 923 {
 924         struct dev_context *devc;
 925         char *cmd;
 926         unsigned int i;
 927         int res;
 928
 929         devc = sdi->priv;
 930
 931         /* Vertical gain. */
 932         for (i = 0; i < devc->model->analog_channels; i++) {
 933                 cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1);
 934                 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]);
 935                 g_free(cmd);
 936                 if (res != SR_OK)
 937                         return SR_ERR;
 938         }
 939         sr_dbg("Current vertical gain:");
 940         for (i = 0; i < devc->model->analog_channels; i++)
 941                 sr_dbg("CH%d %g", i + 1, devc->vdiv[i]);
 942
 943         /* Vertical offset. */
 944         for (i = 0; i < devc->model->analog_channels; i++) {
 945                 cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1);
 946                 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]);
 947                 g_free(cmd);
 948                 if (res != SR_OK)
 949                         return SR_ERR;
 950         }
 951         sr_dbg("Current vertical offset:");
 952         for (i = 0; i < devc->model->analog_channels; i++)
 953                 sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]);
 954
 955         return SR_OK;
 956 }