src/hardware/rigol-ds/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
   5  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   6  * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 3 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <config.h>
  23 #include <stdlib.h>
  24 #include <stdarg.h>
  25 #include <unistd.h>
  26 #include <errno.h>
  27 #include <string.h>
  28 #include <math.h>
  29 #include <ctype.h>
  30 #include <time.h>
  31 #include <glib.h>
  32 #include <libsigrok/libsigrok.h>
  33 #include "libsigrok-internal.h"
  34 #include "scpi.h"
  35 #include "protocol.h"
  36
  37 /*
  38  * This is a unified protocol driver for the DS1000 and DS2000 series.
  39  *
  40  * DS1000 support tested with a Rigol DS1102D.
  41  *
  42  * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02.
  43  *
  44  * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think)
  45  * standard. If you want to read it - it costs real money...
  46  *
  47  * Every response from the scope has a linefeed appended because the
  48  * standard says so. In principle this could be ignored because sending the
  49  * next command clears the output queue of the scope. This driver tries to
  50  * avoid doing that because it may cause an error being generated inside the
  51  * scope and who knows what bugs the firmware has WRT this.
  52  *
  53  * Waveform data is transferred in a format called "arbitrary block program
  54  * data" specified in IEEE 488.2. See Agilents programming manuals for their
  55  * 2000/3000 series scopes for a nice description.
  56  *
  57  * Each data block from the scope has a header, e.g. "#900000001400".
  58  * The '#' marks the start of a block.
  59  * Next is one ASCII decimal digit between 1 and 9, this gives the number of
  60  * ASCII decimal digits following.
  61  * Last are the ASCII decimal digits giving the number of bytes (not
  62  * samples!) in the block.
  63  *
  64  * After this header as many data bytes as indicated follow.
  65  *
  66  * Each data block has a trailing linefeed too.
  67  */
  68
  69 static int parse_int(const char *str, int *ret)
  70 {
  71         char *e;
  72         long tmp;
  73
  74         errno = 0;
  75         tmp = strtol(str, &e, 10);
  76         if (e == str || *e != '\0') {
  77                 sr_dbg("Failed to parse integer: '%s'", str);
  78                 return SR_ERR;
  79         }
  80         if (errno) {
  81                 sr_dbg("Failed to parse integer: '%s', numerical overflow", str);
  82                 return SR_ERR;
  83         }
  84         if (tmp > INT_MAX || tmp < INT_MIN) {
  85                 sr_dbg("Failed to parse integer: '%s', value to large/small", str);
  86                 return SR_ERR;
  87         }
  88
  89         *ret = (int)tmp;
  90         return SR_OK;
  91 }
  92
  93 /* Set the next event to wait for in rigol_ds_receive */
  94 static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event)
  95 {
  96         if (event == WAIT_STOP)
  97                 devc->wait_status = 2;
  98         else
  99                 devc->wait_status = 1;
 100         devc->wait_event = event;
 101 }
 102
 103 /*
 104  * Waiting for a event will return a timeout after 2 to 3 seconds in order
 105  * to not block the application.
 106  */
 107 static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2)
 108 {
 109         char *buf, c;
 110         struct dev_context *devc;
 111         time_t start;
 112
 113         if (!(devc = sdi->priv))
 114                 return SR_ERR;
 115
 116         start = time(NULL);
 117
 118         /*
 119          * Trigger status may return:
 120          * "TD" or "T'D" - triggered
 121          * "AUTO"        - autotriggered
 122          * "RUN"         - running
 123          * "WAIT"        - waiting for trigger
 124          * "STOP"        - stopped
 125          */
 126
 127         if (devc->wait_status == 1) {
 128                 do {
 129                         if (time(NULL) - start >= 3) {
 130                                 sr_dbg("Timeout waiting for trigger");
 131                                 return SR_ERR_TIMEOUT;
 132                         }
 133
 134                         if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
 135                                 return SR_ERR;
 136                         c = buf[0];
 137                         g_free(buf);
 138                 } while (c == status1 || c == status2);
 139
 140                 devc->wait_status = 2;
 141         }
 142         if (devc->wait_status == 2) {
 143                 do {
 144                         if (time(NULL) - start >= 3) {
 145                                 sr_dbg("Timeout waiting for trigger");
 146                                 return SR_ERR_TIMEOUT;
 147                         }
 148
 149                         if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
 150                                 return SR_ERR;
 151                         c = buf[0];
 152                         g_free(buf);
 153                 } while (c != status1 && c != status2);
 154
 155                 rigol_ds_set_wait_event(devc, WAIT_NONE);
 156         }
 157
 158         return SR_OK;
 159 }
 160
 161 /*
 162  * For live capture we need to wait for a new trigger event to ensure that
 163  * sample data is not returned twice.
 164  *
 165  * Unfortunately this will never really work because for sufficiently fast
 166  * timebases and trigger rates it just can't catch the status changes.
 167  *
 168  * What would be needed is a trigger event register with autoreset like the
 169  * Agilents have. The Rigols don't seem to have anything like this.
 170  *
 171  * The workaround is to only wait for the trigger when the timebase is slow
 172  * enough. Of course this means that for faster timebases sample data can be
 173  * returned multiple times, this effect is mitigated somewhat by sleeping
 174  * for about one sweep time in that case.
 175  */
 176 static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi)
 177 {
 178         struct dev_context *devc;
 179         long s;
 180
 181         if (!(devc = sdi->priv))
 182                 return SR_ERR;
 183
 184         /*
 185          * If timebase < 50 msecs/DIV just sleep about one sweep time except
 186          * for really fast sweeps.
 187          */
 188         if (devc->timebase < 0.0499) {
 189                 if (devc->timebase > 0.99e-6) {
 190                         /*
 191                          * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100
 192                          * -> 85 percent of sweep time
 193                          */
 194                         s = (devc->timebase * devc->model->series->num_horizontal_divs
 195                              * 85e6) / 100L;
 196                         sr_spew("Sleeping for %ld usecs instead of trigger-wait", s);
 197                         g_usleep(s);
 198                 }
 199                 rigol_ds_set_wait_event(devc, WAIT_NONE);
 200                 return SR_OK;
 201         } else {
 202                 return rigol_ds_event_wait(sdi, 'T', 'A');
 203         }
 204 }
 205
 206 /* Wait for scope to got to "Stop" in single shot mode */
 207 static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi)
 208 {
 209         return rigol_ds_event_wait(sdi, 'S', 'S');
 210 }
 211
 212 /* Check that a single shot acquisition actually succeeded on the DS2000 */
 213 static int rigol_ds_check_stop(const struct sr_dev_inst *sdi)
 214 {
 215         struct dev_context *devc;
 216         struct sr_channel *ch;
 217         int tmp;
 218
 219         if (!(devc = sdi->priv))
 220                 return SR_ERR;
 221
 222         ch = devc->channel_entry->data;
 223
 224         if (devc->model->series->protocol != PROTOCOL_V3)
 225                 return SR_OK;
 226
 227         if (ch->type == SR_CHANNEL_LOGIC) {
 228                 if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK)
 229                         return SR_ERR;
 230         } else {
 231                 if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
 232                                 ch->index + 1) != SR_OK)
 233                         return SR_ERR;
 234         }
 235         /* Check that the number of samples will be accepted */
 236         if (rigol_ds_config_set(sdi, ":WAV:POIN %d",
 237                         ch->type == SR_CHANNEL_LOGIC ?
 238                                 devc->digital_frame_size :
 239                                 devc->analog_frame_size) != SR_OK)
 240                 return SR_ERR;
 241         if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK)
 242                 return SR_ERR;
 243         /*
 244          * If we get an "Execution error" the scope went from "Single" to
 245          * "Stop" without actually triggering. There is no waveform
 246          * displayed and trying to download one will fail - the scope thinks
 247          * it has 1400 samples (like display memory) and the driver thinks
 248          * it has a different number of samples.
 249          *
 250          * In that case just try to capture something again. Might still
 251          * fail in interesting ways.
 252          *
 253          * Ain't firmware fun?
 254          */
 255         if (tmp & 0x10) {
 256                 sr_warn("Single shot acquisition failed, retrying...");
 257                 /* Sleep a bit, otherwise the single shot will often fail */
 258                 g_usleep(500 * 1000);
 259                 rigol_ds_config_set(sdi, ":SING");
 260                 rigol_ds_set_wait_event(devc, WAIT_STOP);
 261                 return SR_ERR;
 262         }
 263
 264         return SR_OK;
 265 }
 266
 267 /* Wait for enough data becoming available in scope output buffer */
 268 static int rigol_ds_block_wait(const struct sr_dev_inst *sdi)
 269 {
 270         char *buf;
 271         struct dev_context *devc;
 272         time_t start;
 273         int len, ret;
 274
 275         if (!(devc = sdi->priv))
 276                 return SR_ERR;
 277
 278         if (devc->model->series->protocol == PROTOCOL_V3) {
 279
 280                 start = time(NULL);
 281
 282                 do {
 283                         if (time(NULL) - start >= 3) {
 284                                 sr_dbg("Timeout waiting for data block");
 285                                 return SR_ERR_TIMEOUT;
 286                         }
 287
 288                         /*
 289                          * The scope copies data really slowly from sample
 290                          * memory to its output buffer, so try not to bother
 291                          * it too much with SCPI requests but don't wait too
 292                          * long for short sample frame sizes.
 293                          */
 294                         g_usleep(devc->analog_frame_size < (15 * 1000) ? (100 * 1000) : (1000 * 1000));
 295
 296                         /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */
 297                         if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK)
 298                                 return SR_ERR;
 299                         ret = parse_int(buf + 5, &len);
 300                         g_free(buf);
 301                         if (ret != SR_OK)
 302                                 return SR_ERR;
 303                 } while (buf[0] == 'R' && len < (1000 * 1000));
 304         }
 305
 306         rigol_ds_set_wait_event(devc, WAIT_NONE);
 307
 308         return SR_OK;
 309 }
 310
 311 /* Send a configuration setting. */
 312 SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...)
 313 {
 314         struct dev_context *devc = sdi->priv;
 315         va_list args;
 316         int ret;
 317
 318         va_start(args, format);
 319         ret = sr_scpi_send_variadic(sdi->conn, format, args);
 320         va_end(args);
 321
 322         if (ret != SR_OK)
 323                 return SR_ERR;
 324
 325         if (devc->model->series->protocol == PROTOCOL_V2) {
 326                 /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */
 327                 sr_spew("delay %dms", 100);
 328                 g_usleep(100 * 1000);
 329                 return SR_OK;
 330         } else {
 331                 return sr_scpi_get_opc(sdi->conn);
 332         }
 333 }
 334
 335 /* Start capturing a new frameset */
 336 SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
 337 {
 338         struct dev_context *devc;
 339         gchar *trig_mode;
 340         unsigned int num_channels, i, j;
 341         int buffer_samples;
 342         int ret;
 343
 344         if (!(devc = sdi->priv))
 345                 return SR_ERR;
 346
 347         const gboolean first_frame = (devc->num_frames == 0);
 348
 349         uint64_t limit_frames = devc->limit_frames;
 350         if (devc->num_frames_segmented != 0 && devc->num_frames_segmented < limit_frames)
 351                 limit_frames = devc->num_frames_segmented;
 352         if (limit_frames == 0)
 353                 sr_dbg("Starting data capture for frameset %" PRIu64,
 354                        devc->num_frames + 1);
 355         else
 356                 sr_dbg("Starting data capture for frameset %" PRIu64 " of %"
 357                        PRIu64, devc->num_frames + 1, limit_frames);
 358
 359         switch (devc->model->series->protocol) {
 360         case PROTOCOL_V1:
 361                 rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
 362                 break;
 363         case PROTOCOL_V2:
 364                 if (devc->data_source == DATA_SOURCE_LIVE) {
 365                         if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK)
 366                                 return SR_ERR;
 367                         rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
 368                 } else {
 369                         if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
 370                                 return SR_ERR;
 371                         if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK)
 372                                 return SR_ERR;
 373                         if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK)
 374                                 return SR_ERR;
 375                         ret = rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode);
 376                         g_free(trig_mode);
 377                         if (ret != SR_OK)
 378                                 return SR_ERR;
 379                         if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
 380                                 return SR_ERR;
 381                         rigol_ds_set_wait_event(devc, WAIT_STOP);
 382                 }
 383                 break;
 384         case PROTOCOL_V3:
 385         case PROTOCOL_V4:
 386         case PROTOCOL_V5:
 387                 if (first_frame && rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK)
 388                         return SR_ERR;
 389                 if (devc->data_source == DATA_SOURCE_LIVE) {
 390                         if (first_frame && rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK)
 391                                 return SR_ERR;
 392                         devc->analog_frame_size = devc->model->series->live_samples;
 393                         devc->digital_frame_size = devc->model->series->live_samples;
 394                         rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
 395                 } else {
 396                         if (devc->model->series->protocol == PROTOCOL_V3) {
 397                                 if (first_frame && rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK)
 398                                         return SR_ERR;
 399                         } else if (devc->model->series->protocol >= PROTOCOL_V4) {
 400                                 num_channels = 0;
 401
 402                                 /* Channels 3 and 4 are multiplexed with D0-7 and D8-15 */
 403                                 for (i = 0; i < devc->model->analog_channels; i++) {
 404                                         if (devc->analog_channels[i]) {
 405                                                 num_channels++;
 406                                         } else if (i >= 2 && devc->model->has_digital) {
 407                                                 for (j = 0; j < 8; j++) {
 408                                                         if (devc->digital_channels[8 * (i - 2) + j]) {
 409                                                                 num_channels++;
 410                                                                 break;
 411                                                         }
 412                                                 }
 413                                         }
 414                                 }
 415
 416                                 buffer_samples = devc->model->series->buffer_samples;
 417                                 if (first_frame && buffer_samples == 0)
 418                                 {
 419                                         /* The DS4000 series does not have a fixed memory depth, it
 420                                          * can be chosen from the menu and also varies with number
 421                                          * of active channels. Retrieve the actual number with the
 422                                          * ACQ:MDEP command. */
 423                                         sr_scpi_get_int(sdi->conn, "ACQ:MDEP?", &buffer_samples);
 424                                         devc->analog_frame_size = devc->digital_frame_size =
 425                                                         buffer_samples;
 426                                 }
 427                                 else if (first_frame)
 428                                 {
 429                                         /* The DS1000Z series has a fixed memory depth which we
 430                                          * need to divide correctly according to the number of
 431                                          * active channels. */
 432                                         devc->analog_frame_size = devc->digital_frame_size =
 433                                                 num_channels == 1 ?
 434                                                         buffer_samples :
 435                                                                 num_channels == 2 ?
 436                                                                         buffer_samples / 2 :
 437                                                                         buffer_samples / 4;
 438                                 }
 439                         }
 440
 441                         if (devc->data_source == DATA_SOURCE_LIVE && rigol_ds_config_set(sdi, ":SINGL") != SR_OK)
 442                                 return SR_ERR;
 443                         rigol_ds_set_wait_event(devc, WAIT_STOP);
 444                         if (devc->data_source == DATA_SOURCE_SEGMENTED &&
 445                                         devc->model->series->protocol <= PROTOCOL_V4)
 446                                 if (rigol_ds_config_set(sdi, "FUNC:WREP:FCUR %d", devc->num_frames + 1) != SR_OK)
 447                                         return SR_ERR;
 448                 }
 449                 break;
 450         }
 451
 452         return SR_OK;
 453 }
 454
 455 /* Start reading data from the current channel */
 456 SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi)
 457 {
 458         struct dev_context *devc;
 459         struct sr_channel *ch;
 460
 461         if (!(devc = sdi->priv))
 462                 return SR_ERR;
 463
 464         ch = devc->channel_entry->data;
 465
 466         sr_dbg("Starting reading data from channel %d", ch->index + 1);
 467
 468         const gboolean first_frame = (devc->num_frames == 0);
 469
 470         switch (devc->model->series->protocol) {
 471         case PROTOCOL_V1:
 472         case PROTOCOL_V2:
 473                 if (ch->type == SR_CHANNEL_LOGIC) {
 474                         if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK)
 475                                 return SR_ERR;
 476                 } else {
 477                         if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d",
 478                                         ch->index + 1) != SR_OK)
 479                                 return SR_ERR;
 480                 }
 481                 rigol_ds_set_wait_event(devc, WAIT_NONE);
 482                 break;
 483         case PROTOCOL_V3:
 484                 if (ch->type == SR_CHANNEL_LOGIC) {
 485                         if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK)
 486                                 return SR_ERR;
 487                 } else {
 488                         if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
 489                                         ch->index + 1) != SR_OK)
 490                                 return SR_ERR;
 491                 }
 492                 if (devc->data_source != DATA_SOURCE_LIVE) {
 493                         if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
 494                                 return SR_ERR;
 495                         if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
 496                                 return SR_ERR;
 497                 }
 498                 break;
 499         case PROTOCOL_V4:
 500         case PROTOCOL_V5:
 501                 if (ch->type == SR_CHANNEL_ANALOG) {
 502                         if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
 503                                         ch->index + 1) != SR_OK)
 504                                 return SR_ERR;
 505                 } else {
 506                         if (rigol_ds_config_set(sdi, ":WAV:SOUR D%d",
 507                                         ch->index) != SR_OK)
 508                                 return SR_ERR;
 509                 }
 510
 511                 if (first_frame && rigol_ds_config_set(sdi,
 512                                         devc->data_source == DATA_SOURCE_LIVE ?
 513                                                 ":WAV:MODE NORM" :":WAV:MODE RAW") != SR_OK)
 514                         return SR_ERR;
 515
 516                 if (devc->data_source != DATA_SOURCE_LIVE) {
 517                         if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
 518                                 return SR_ERR;
 519                 }
 520                 break;
 521         }
 522
 523         if (devc->model->series->protocol >= PROTOCOL_V3 &&
 524                         ch->type == SR_CHANNEL_ANALOG) {
 525                 /* Vertical increment. */
 526                 if (first_frame && sr_scpi_get_float(sdi->conn, ":WAV:YINC?",
 527                                 &devc->vert_inc[ch->index]) != SR_OK)
 528                         return SR_ERR;
 529                 /* Vertical origin. */
 530                 if (first_frame && sr_scpi_get_float(sdi->conn, ":WAV:YOR?",
 531                         &devc->vert_origin[ch->index]) != SR_OK)
 532                         return SR_ERR;
 533                 /* Vertical reference. */
 534                 if (first_frame && sr_scpi_get_int(sdi->conn, ":WAV:YREF?",
 535                                 &devc->vert_reference[ch->index]) != SR_OK)
 536                         return SR_ERR;
 537         } else if (ch->type == SR_CHANNEL_ANALOG) {
 538                 devc->vert_inc[ch->index] = devc->vdiv[ch->index] / 25.6;
 539         }
 540
 541         rigol_ds_set_wait_event(devc, WAIT_BLOCK);
 542
 543         devc->num_channel_bytes = 0;
 544         devc->num_header_bytes = 0;
 545         devc->num_block_bytes = 0;
 546
 547         return SR_OK;
 548 }
 549
 550 /* Read the header of a data block */
 551 static int rigol_ds_read_header(struct sr_dev_inst *sdi)
 552 {
 553         struct sr_scpi_dev_inst *scpi = sdi->conn;
 554         struct dev_context *devc = sdi->priv;
 555         char *buf = (char *) devc->buffer;
 556         size_t header_length;
 557         int ret;
 558
 559         /* Try to read the hashsign and length digit. */
 560         if (devc->num_header_bytes < 2) {
 561                 ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes,
 562                                 2 - devc->num_header_bytes);
 563                 if (ret < 0) {
 564                         sr_err("Read error while reading data header.");
 565                         return SR_ERR;
 566                 }
 567                 devc->num_header_bytes += ret;
 568         }
 569
 570         if (devc->num_header_bytes < 2)
 571                 return 0;
 572
 573         if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') {
 574                 sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]);
 575                 return SR_ERR;
 576         }
 577
 578         header_length = 2 + buf[1] - '0';
 579
 580         /* Try to read the length. */
 581         if (devc->num_header_bytes < header_length) {
 582                 ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes,
 583                                 header_length - devc->num_header_bytes);
 584                 if (ret < 0) {
 585                         sr_err("Read error while reading data header.");
 586                         return SR_ERR;
 587                 }
 588                 devc->num_header_bytes += ret;
 589         }
 590
 591         if (devc->num_header_bytes < header_length)
 592                 return 0;
 593
 594         /* Read the data length. */
 595         buf[header_length] = '\0';
 596
 597         if (parse_int(buf + 2, &ret) != SR_OK) {
 598                 sr_err("Received invalid data block length '%s'.", buf + 2);
 599                 return -1;
 600         }
 601
 602         sr_dbg("Received data block header: '%s' -> block length %d", buf, ret);
 603
 604         return ret;
 605 }
 606
 607 SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data)
 608 {
 609         struct sr_dev_inst *sdi;
 610         struct sr_scpi_dev_inst *scpi;
 611         struct dev_context *devc;
 612         struct sr_datafeed_packet packet;
 613         struct sr_datafeed_analog analog;
 614         struct sr_analog_encoding encoding;
 615         struct sr_analog_meaning meaning;
 616         struct sr_analog_spec spec;
 617         struct sr_datafeed_logic logic;
 618         double vdiv, offset, origin;
 619         int len, i, vref;
 620         struct sr_channel *ch;
 621         gsize expected_data_bytes;
 622
 623         (void)fd;
 624
 625         if (!(sdi = cb_data))
 626                 return TRUE;
 627
 628         if (!(devc = sdi->priv))
 629                 return TRUE;
 630
 631         scpi = sdi->conn;
 632
 633         if (!(revents == G_IO_IN || revents == 0))
 634                 return TRUE;
 635
 636         const gboolean first_frame = (devc->num_frames == 0);
 637
 638         switch (devc->wait_event) {
 639         case WAIT_NONE:
 640                 break;
 641         case WAIT_TRIGGER:
 642                 if (rigol_ds_trigger_wait(sdi) != SR_OK)
 643                         return TRUE;
 644                 if (rigol_ds_channel_start(sdi) != SR_OK)
 645                         return TRUE;
 646                 return TRUE;
 647         case WAIT_BLOCK:
 648                 if (rigol_ds_block_wait(sdi) != SR_OK)
 649                         return TRUE;
 650                 break;
 651         case WAIT_STOP:
 652                 if (rigol_ds_stop_wait(sdi) != SR_OK)
 653                         return TRUE;
 654                 if (rigol_ds_check_stop(sdi) != SR_OK)
 655                         return TRUE;
 656                 if (rigol_ds_channel_start(sdi) != SR_OK)
 657                         return TRUE;
 658                 return TRUE;
 659         default:
 660                 sr_err("BUG: Unknown event target encountered");
 661                 break;
 662         }
 663
 664         ch = devc->channel_entry->data;
 665
 666         expected_data_bytes = ch->type == SR_CHANNEL_ANALOG ?
 667                         devc->analog_frame_size : devc->digital_frame_size;
 668
 669         if (devc->num_block_bytes == 0) {
 670                 if (devc->model->series->protocol >= PROTOCOL_V4) {
 671                         if (first_frame && rigol_ds_config_set(sdi, ":WAV:START %d",
 672                                         devc->num_channel_bytes + 1) != SR_OK)
 673                                 return TRUE;
 674                         if (first_frame && rigol_ds_config_set(sdi, ":WAV:STOP %d",
 675                                         MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE,
 676                                                 devc->analog_frame_size)) != SR_OK)
 677                                 return TRUE;
 678                 }
 679
 680                 if (devc->model->series->protocol >= PROTOCOL_V3) {
 681                         if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
 682                                 return TRUE;
 683                         if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK)
 684                                 return TRUE;
 685                 }
 686
 687                 if (sr_scpi_read_begin(scpi) != SR_OK)
 688                         return TRUE;
 689
 690                 if (devc->format == FORMAT_IEEE488_2) {
 691                         sr_dbg("New block header expected");
 692                         len = rigol_ds_read_header(sdi);
 693                         if (len == 0)
 694                                 /* Still reading the header. */
 695                                 return TRUE;
 696                         if (len == -1) {
 697                                 sr_err("Error while reading block header, aborting capture.");
 698                                 std_session_send_df_frame_end(sdi);
 699                                 sr_dev_acquisition_stop(sdi);
 700                                 return TRUE;
 701                         }
 702                         /* At slow timebases in live capture the DS2072 and
 703                          * DS1054Z sometimes return "short" data blocks, with
 704                          * apparently no way to get the rest of the data.
 705                          * Discard these, the complete data block will appear
 706                          * eventually.
 707                          */
 708                         if (devc->data_source == DATA_SOURCE_LIVE
 709                                         && (unsigned)len < expected_data_bytes) {
 710                                 sr_dbg("Discarding short data block: got %d/%d bytes\n", len, (int)expected_data_bytes);
 711                                 sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1);
 712                                 devc->num_header_bytes = 0;
 713                                 return TRUE;
 714                         }
 715                         devc->num_block_bytes = len;
 716                 } else {
 717                         devc->num_block_bytes = expected_data_bytes;
 718                 }
 719                 devc->num_block_read = 0;
 720         }
 721
 722         len = devc->num_block_bytes - devc->num_block_read;
 723         if (len > ACQ_BUFFER_SIZE)
 724                 len = ACQ_BUFFER_SIZE;
 725         sr_dbg("Requesting read of %d bytes", len);
 726
 727         len = sr_scpi_read_data(scpi, (char *)devc->buffer, len);
 728
 729         if (len == -1) {
 730                 sr_err("Error while reading block data, aborting capture.");
 731                 std_session_send_df_frame_end(sdi);
 732                 sr_dev_acquisition_stop(sdi);
 733                 return TRUE;
 734         }
 735
 736         sr_dbg("Received %d bytes.", len);
 737
 738         devc->num_block_read += len;
 739
 740         if (ch->type == SR_CHANNEL_ANALOG) {
 741                 vref = devc->vert_reference[ch->index];
 742                 vdiv = devc->vert_inc[ch->index];
 743                 origin = devc->vert_origin[ch->index];
 744                 offset = devc->vert_offset[ch->index];
 745                 if (devc->model->series->protocol >= PROTOCOL_V3)
 746                         for (i = 0; i < len; i++)
 747                                 devc->data[i] = ((int)devc->buffer[i] - vref - origin) * vdiv;
 748                 else
 749                         for (i = 0; i < len; i++)
 750                                 devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset;
 751                 float vdivlog = log10f(vdiv);
 752                 int digits = -(int)vdivlog + (vdivlog < 0.0);
 753                 sr_analog_init(&analog, &encoding, &meaning, &spec, digits);
 754                 analog.meaning->channels = g_slist_append(NULL, ch);
 755                 analog.num_samples = len;
 756                 analog.data = devc->data;
 757                 analog.meaning->mq = SR_MQ_VOLTAGE;
 758                 analog.meaning->unit = SR_UNIT_VOLT;
 759                 analog.meaning->mqflags = 0;
 760                 packet.type = SR_DF_ANALOG;
 761                 packet.payload = &analog;
 762                 sr_session_send(sdi, &packet);
 763                 g_slist_free(analog.meaning->channels);
 764         } else {
 765                 logic.length = len;
 766                 // TODO: For the MSO1000Z series, we need a way to express that
 767                 // this data is in fact just for a single channel, with the valid
 768                 // data for that channel in the LSB of each byte.
 769                 logic.unitsize = devc->model->series->protocol >= PROTOCOL_V4 ? 1 : 2;
 770                 logic.data = devc->buffer;
 771                 packet.type = SR_DF_LOGIC;
 772                 packet.payload = &logic;
 773                 sr_session_send(sdi, &packet);
 774         }
 775
 776         if (devc->num_block_read == devc->num_block_bytes) {
 777                 sr_dbg("Block has been completed");
 778                 if (devc->model->series->protocol >= PROTOCOL_V3) {
 779                         /* Discard the terminating linefeed */
 780                         sr_scpi_read_data(scpi, (char *)devc->buffer, 1);
 781                 }
 782                 if (devc->format == FORMAT_IEEE488_2) {
 783                         /* Prepare for possible next block */
 784                         devc->num_header_bytes = 0;
 785                         devc->num_block_bytes = 0;
 786                         if (devc->data_source != DATA_SOURCE_LIVE)
 787                                 rigol_ds_set_wait_event(devc, WAIT_BLOCK);
 788                 }
 789                 if (!sr_scpi_read_complete(scpi) && !devc->channel_entry->next) {
 790                         sr_err("Read should have been completed");
 791                 }
 792                 devc->num_block_read = 0;
 793         } else {
 794                 sr_dbg("%" PRIu64 " of %" PRIu64 " block bytes read",
 795                         devc->num_block_read, devc->num_block_bytes);
 796         }
 797
 798         devc->num_channel_bytes += len;
 799
 800         if (devc->num_channel_bytes < expected_data_bytes)
 801                 /* Don't have the full data for this channel yet, re-run. */
 802                 return TRUE;
 803
 804         /* End of data for this channel. */
 805         if (devc->model->series->protocol == PROTOCOL_V3) {
 806                 /* Signal end of data download to scope */
 807                 if (devc->data_source != DATA_SOURCE_LIVE)
 808                         /*
 809                          * This causes a query error, without it switching
 810                          * to the next channel causes an error. Fun with
 811                          * firmware...
 812                          */
 813                         rigol_ds_config_set(sdi, ":WAV:END");
 814         }
 815
 816         if (devc->channel_entry->next) {
 817                 /* We got the frame for this channel, now get the next channel. */
 818                 devc->channel_entry = devc->channel_entry->next;
 819                 rigol_ds_channel_start(sdi);
 820         } else {
 821                 /* Done with this frame. */
 822                 std_session_send_df_frame_end(sdi);
 823
 824                 devc->num_frames++;
 825
 826                 /* V5 has no way to read the number of recorded frames, so try to set the
 827                  * next frame and read it back instead.
 828                  */
 829                 if (devc->data_source == DATA_SOURCE_SEGMENTED &&
 830                                 devc->model->series->protocol == PROTOCOL_V5) {
 831                         int frames = 0;
 832                         if (rigol_ds_config_set(sdi, "REC:CURR %d", devc->num_frames + 1) != SR_OK)
 833                                 return SR_ERR;
 834                         if (sr_scpi_get_int(sdi->conn, "REC:CURR?", &frames) != SR_OK)
 835                                 return SR_ERR;
 836                         devc->num_frames_segmented = frames;
 837                 }
 838
 839                 if (devc->num_frames == devc->limit_frames ||
 840                                 devc->num_frames == devc->num_frames_segmented ||
 841                                 devc->data_source == DATA_SOURCE_MEMORY) {
 842                         /* Last frame, stop capture. */
 843                         sr_dev_acquisition_stop(sdi);
 844                 } else {
 845                         /* Get the next frame, starting with the first channel. */
 846                         devc->channel_entry = devc->enabled_channels;
 847
 848                         rigol_ds_capture_start(sdi);
 849
 850                         /* Start of next frame. */
 851                         std_session_send_df_frame_begin(sdi);
 852                 }
 853         }
 854
 855         return TRUE;
 856 }
 857
 858 SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi)
 859 {
 860         struct dev_context *devc;
 861         struct sr_channel *ch;
 862         char *cmd;
 863         unsigned int i;
 864         int res;
 865
 866         devc = sdi->priv;
 867
 868         /* Analog channel state. */
 869         for (i = 0; i < devc->model->analog_channels; i++) {
 870                 cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1);
 871                 res = sr_scpi_get_bool(sdi->conn, cmd, &devc->analog_channels[i]);
 872                 g_free(cmd);
 873                 if (res != SR_OK)
 874                         return SR_ERR;
 875                 ch = g_slist_nth_data(sdi->channels, i);
 876                 ch->enabled = devc->analog_channels[i];
 877         }
 878         sr_dbg("Current analog channel state:");
 879         for (i = 0; i < devc->model->analog_channels; i++)
 880                 sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off");
 881
 882         /* Digital channel state. */
 883         if (devc->model->has_digital) {
 884                 if (sr_scpi_get_bool(sdi->conn,
 885                                 devc->model->series->protocol >= PROTOCOL_V3 ?
 886                                         ":LA:STAT?" : ":LA:DISP?",
 887                                 &devc->la_enabled) != SR_OK)
 888                         return SR_ERR;
 889                 sr_dbg("Logic analyzer %s, current digital channel state:",
 890                                 devc->la_enabled ? "enabled" : "disabled");
 891                 for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
 892                         if (devc->model->series->protocol >= PROTOCOL_V5)
 893                                 cmd = g_strdup_printf(":LA:DISP? D%d", i);
 894                         else if (devc->model->series->protocol >= PROTOCOL_V3)
 895                                 cmd = g_strdup_printf(":LA:DIG%d:DISP?", i);
 896                         else
 897                                 cmd = g_strdup_printf(":DIG%d:TURN?", i);
 898                         res = sr_scpi_get_bool(sdi->conn, cmd, &devc->digital_channels[i]);
 899                         g_free(cmd);
 900                         if (res != SR_OK)
 901                                 return SR_ERR;
 902                         ch = g_slist_nth_data(sdi->channels, i + devc->model->analog_channels);
 903                         ch->enabled = devc->digital_channels[i];
 904                         sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off");
 905                 }
 906         }
 907
 908         /* Timebase. */
 909         if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK)
 910                 return SR_ERR;
 911         sr_dbg("Current timebase %g", devc->timebase);
 912
 913         /* Probe attenuation. */
 914         for (i = 0; i < devc->model->analog_channels; i++) {
 915                 cmd = g_strdup_printf(":CHAN%d:PROB?", i + 1);
 916
 917                 /* DSO1000B series prints an X after the probe factor, so
 918                  * we get a string and check for that instead of only handling
 919                  * floats. */
 920                 char *response;
 921                 res = sr_scpi_get_string(sdi->conn, cmd, &response);
 922                 if (res != SR_OK)
 923                         return SR_ERR;
 924
 925                 int len = strlen(response);
 926                 if (response[len-1] == 'X')
 927                         response[len-1] = 0;
 928
 929                 res = sr_atof_ascii(response, &devc->attenuation[i]);
 930                 g_free(response);
 931                 g_free(cmd);
 932                 if (res != SR_OK)
 933                         return SR_ERR;
 934         }
 935         sr_dbg("Current probe attenuation:");
 936         for (i = 0; i < devc->model->analog_channels; i++)
 937                 sr_dbg("CH%d %g", i + 1, devc->attenuation[i]);
 938
 939         /* Vertical gain and offset. */
 940         if (rigol_ds_get_dev_cfg_vertical(sdi) != SR_OK)
 941                 return SR_ERR;
 942
 943         /* Coupling. */
 944         for (i = 0; i < devc->model->analog_channels; i++) {
 945                 cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1);
 946                 g_free(devc->coupling[i]);
 947                 devc->coupling[i] = NULL;
 948                 res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]);
 949                 g_free(cmd);
 950                 if (res != SR_OK)
 951                         return SR_ERR;
 952         }
 953         sr_dbg("Current coupling:");
 954         for (i = 0; i < devc->model->analog_channels; i++)
 955                 sr_dbg("CH%d %s", i + 1, devc->coupling[i]);
 956
 957         /* Trigger source. */
 958         g_free(devc->trigger_source);
 959         devc->trigger_source = NULL;
 960         if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK)
 961                 return SR_ERR;
 962         sr_dbg("Current trigger source %s", devc->trigger_source);
 963
 964         /* Horizontal trigger position. */
 965         if (sr_scpi_get_float(sdi->conn, devc->model->cmds[CMD_GET_HORIZ_TRIGGERPOS].str,
 966                         &devc->horiz_triggerpos) != SR_OK)
 967                 return SR_ERR;
 968         sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos);
 969
 970         /* Trigger slope. */
 971         g_free(devc->trigger_slope);
 972         devc->trigger_slope = NULL;
 973         if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK)
 974                 return SR_ERR;
 975         sr_dbg("Current trigger slope %s", devc->trigger_slope);
 976
 977         /* Trigger level. */
 978         if (sr_scpi_get_float(sdi->conn, ":TRIG:EDGE:LEV?", &devc->trigger_level) != SR_OK)
 979                 return SR_ERR;
 980         sr_dbg("Current trigger level %g", devc->trigger_level);
 981
 982         return SR_OK;
 983 }
 984
 985 SR_PRIV int rigol_ds_get_dev_cfg_vertical(const struct sr_dev_inst *sdi)
 986 {
 987         struct dev_context *devc;
 988         char *cmd;
 989         unsigned int i;
 990         int res;
 991
 992         devc = sdi->priv;
 993
 994         /* Vertical gain. */
 995         for (i = 0; i < devc->model->analog_channels; i++) {
 996                 cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1);
 997                 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]);
 998                 g_free(cmd);
 999                 if (res != SR_OK)
1000                         return SR_ERR;
1001         }
1002         sr_dbg("Current vertical gain:");
1003         for (i = 0; i < devc->model->analog_channels; i++)
1004                 sr_dbg("CH%d %g", i + 1, devc->vdiv[i]);
1005
1006         /* Vertical offset. */
1007         for (i = 0; i < devc->model->analog_channels; i++) {
1008                 cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1);
1009                 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]);
1010                 g_free(cmd);
1011                 if (res != SR_OK)
1012                         return SR_ERR;
1013         }
1014         sr_dbg("Current vertical offset:");
1015         for (i = 0; i < devc->model->analog_channels; i++)
1016                 sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]);
1017
1018         return SR_OK;
1019 }