src/hardware/kingst-la2016/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
   5  * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
   6  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   7  * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation, either version 3 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <config.h>
  24 #include <stdint.h>
  25 #include <string.h>
  26 #include <glib.h>
  27 #include <glib/gstdio.h>
  28 #include <stdio.h>
  29 #include <errno.h>
  30 #include <math.h>
  31 #include <inttypes.h>
  32 #include <libsigrok/libsigrok.h>
  33 #include "libsigrok-internal.h"
  34 #include "protocol.h"
  35
  36 #define FPGA_FIRMWARE   "kingst-la2016a-fpga.bitstream"
  37 #define UC_FIRMWARE     "kingst-la-%04x.fw"
  38
  39 #define MAX_SAMPLE_RATE  SR_MHZ(200)
  40 #define MAX_SAMPLE_DEPTH 10e9
  41 #define MAX_PWM_FREQ     SR_MHZ(20)
  42 #define PWM_CLOCK        SR_MHZ(200)
  43
  44 /* usb vendor class control requests to the cypress FX2 microcontroller */
  45 #define CMD_EEPROM      0xa2    /* ctrl_in reads, ctrl_out writes */
  46 #define CMD_FPGA_INIT   0x50    /* used before and after FPGA bitstream loading */
  47 #define CMD_FPGA_SPI    0x20    /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */
  48 #define CMD_FPGA_ENABLE 0x10
  49 #define CMD_BULK_RESET  0x38    /* flush FX2 usb endpoint 6 IN fifos */
  50 #define CMD_BULK_START  0x30    /* begin transfer of capture data via usb endpoint 6 IN */
  51 #define CMD_KAUTH       0x60    /* communicate with authentication ic U10, not used */
  52
  53 /* registers for control request 32: */
  54 #define CTRL_RUN         0x00
  55 #define CTRL_PWM_EN      0x02
  56 #define CTRL_BULK        0x10 /* can be read to get 12 byte sampling_info (III) */
  57 #define CTRL_SAMPLING    0x20
  58 #define CTRL_TRIGGER     0x30
  59 #define CTRL_THRESHOLD   0x48
  60 #define CTRL_PWM1        0x70
  61 #define CTRL_PWM2        0x78
  62
  63 static int ctrl_in(const struct sr_dev_inst *sdi,
  64                    uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
  65                    void *data, uint16_t wLength)
  66 {
  67         struct sr_usb_dev_inst *usb;
  68         int ret;
  69
  70         usb = sdi->conn;
  71
  72         if ((ret = libusb_control_transfer(
  73                      usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
  74                      bRequest, wValue, wIndex, (unsigned char *)data, wLength,
  75                      DEFAULT_TIMEOUT_MS)) != wLength) {
  76                 sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.",
  77                        wLength, bRequest, wValue, wIndex,
  78                        libusb_error_name(ret));
  79                 return SR_ERR;
  80         }
  81
  82         return SR_OK;
  83 }
  84
  85 static int ctrl_out(const struct sr_dev_inst *sdi,
  86                     uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
  87                     void *data, uint16_t wLength)
  88 {
  89         struct sr_usb_dev_inst *usb;
  90         int ret;
  91
  92         usb = sdi->conn;
  93
  94         if ((ret = libusb_control_transfer(
  95                      usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
  96                      bRequest, wValue, wIndex, (unsigned char*)data, wLength,
  97                      DEFAULT_TIMEOUT_MS)) != wLength) {
  98                 sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.",
  99                        wLength, bRequest, wValue, wIndex,
 100                        libusb_error_name(ret));
 101                 return SR_ERR;
 102         }
 103
 104         return SR_OK;
 105 }
 106
 107 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi)
 108 {
 109         struct dev_context *devc;
 110         struct drv_context *drvc;
 111         struct sr_usb_dev_inst *usb;
 112         struct sr_resource bitstream;
 113         uint8_t buffer[sizeof(uint32_t)];
 114         uint8_t *wrptr;
 115         uint8_t cmd_resp;
 116         uint8_t block[4096];
 117         int len, act_len;
 118         unsigned int pos;
 119         int ret;
 120         unsigned int zero_pad_to = 0x2c000;
 121
 122         devc = sdi->priv;
 123         drvc = sdi->driver->context;
 124         usb = sdi->conn;
 125
 126         sr_info("Uploading FPGA bitstream '%s'.", FPGA_FIRMWARE);
 127
 128         ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, FPGA_FIRMWARE);
 129         if (ret != SR_OK) {
 130                 sr_err("could not find la2016 firmware %s!", FPGA_FIRMWARE);
 131                 return ret;
 132         }
 133
 134         devc->bitstream_size = (uint32_t)bitstream.size;
 135         wrptr = buffer;
 136         write_u32le_inc(&wrptr, devc->bitstream_size);
 137         if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
 138                 sr_err("failed to give upload init command");
 139                 sr_resource_close(drvc->sr_ctx, &bitstream);
 140                 return ret;
 141         }
 142
 143         pos = 0;
 144         while (1) {
 145                 if (pos < bitstream.size) {
 146                         len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block));
 147                         if (len < 0) {
 148                                 sr_err("failed to read from fpga bitstream!");
 149                                 sr_resource_close(drvc->sr_ctx, &bitstream);
 150                                 return SR_ERR;
 151                         }
 152                 } else {
 153                         // fill with zero's until zero_pad_to
 154                         len = zero_pad_to - pos;
 155                         if ((unsigned)len > sizeof(block))
 156                                 len = sizeof(block);
 157                         memset(&block, 0, len);
 158                 }
 159                 if (len == 0)
 160                         break;
 161
 162                 ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
 163                 if (ret != 0) {
 164                         sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret));
 165                         ret = SR_ERR;
 166                         break;
 167                 }
 168                 if (act_len != len) {
 169                         sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len);
 170                         ret = SR_ERR;
 171                         break;
 172                 }
 173                 pos += len;
 174         }
 175         sr_resource_close(drvc->sr_ctx, &bitstream);
 176         if (ret != 0)
 177                 return ret;
 178         sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size);
 179
 180         if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
 181                 sr_err("failed to read response after FPGA bitstream upload");
 182                 return ret;
 183         }
 184         if (cmd_resp != 0) {
 185                 sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp);
 186                 return SR_ERR;
 187         }
 188
 189         g_usleep(30000);
 190
 191         if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) {
 192                 sr_err("failed enable fpga");
 193                 return ret;
 194         }
 195
 196         g_usleep(40000);
 197         return SR_OK;
 198 }
 199
 200 static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
 201 {
 202         struct dev_context *devc;
 203         float o1, o2, v1, v2, f;
 204         uint32_t cfgval;
 205         uint8_t buffer[sizeof(uint32_t)];
 206         uint8_t *wrptr;
 207         int ret;
 208
 209         devc = sdi->priv;
 210         o1 = 15859969; v1 = 0.45;
 211         o2 = 15860333; v2 = 1.65;
 212         f = (o2 - o1) / (v2 - v1);
 213         cfgval = (uint32_t)(o1 + (voltage - v1) * f);
 214         sr_dbg("set threshold voltage %.2fV, raw value 0x%lx",
 215                 voltage, (unsigned long)cfgval);
 216
 217         wrptr = buffer;
 218         write_u32le_inc(&wrptr, cfgval);
 219         ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_THRESHOLD, 0, buffer, wrptr - buffer);
 220         if (ret != SR_OK) {
 221                 sr_err("Error setting %.2fV threshold voltage (%d)",
 222                         voltage, ret);
 223                 return ret;
 224         }
 225         devc->threshold_voltage = voltage;
 226
 227         return SR_OK;
 228 }
 229
 230 static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2)
 231 {
 232         struct dev_context *devc;
 233         uint8_t cfg;
 234         int ret;
 235
 236         devc = sdi->priv;
 237         cfg = 0;
 238
 239         if (p1) cfg |= 1 << 0;
 240         if (p2) cfg |= 1 << 1;
 241
 242         sr_dbg("set pwm enable %d %d", p1, p2);
 243         ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM_EN, 0, &cfg, sizeof(cfg));
 244         if (ret != SR_OK) {
 245                 sr_err("error setting new pwm enable 0x%02x", cfg);
 246                 return ret;
 247         }
 248         devc->pwm_setting[0].enabled = (p1) ? 1 : 0;
 249         devc->pwm_setting[1].enabled = (p2) ? 1 : 0;
 250
 251         return SR_OK;
 252 }
 253
 254 static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty)
 255 {
 256         int CTRL_PWM[] = { CTRL_PWM1, CTRL_PWM2 };
 257         struct dev_context *devc;
 258         pwm_setting_dev_t cfg;
 259         pwm_setting_t *setting;
 260         int ret;
 261         uint8_t buf[2 * sizeof(uint32_t)];
 262         uint8_t *wrptr;
 263
 264         devc = sdi->priv;
 265
 266         if (which < 1 || which > 2) {
 267                 sr_err("invalid pwm channel: %d", which);
 268                 return SR_ERR;
 269         }
 270         if (freq > MAX_PWM_FREQ) {
 271                 sr_err("pwm frequency too high: %.1f", freq);
 272                 return SR_ERR;
 273         }
 274         if (duty > 100 || duty < 0) {
 275                 sr_err("invalid pwm percentage: %f", duty);
 276                 return SR_ERR;
 277         }
 278
 279         cfg.period = (uint32_t)(PWM_CLOCK / freq);
 280         cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.));
 281         sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty);
 282
 283         wrptr = buf;
 284         write_u32le_inc(&wrptr, cfg.period);
 285         write_u32le_inc(&wrptr, cfg.duty);
 286         ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf);
 287         if (ret != SR_OK) {
 288                 sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty);
 289                 return ret;
 290         }
 291         setting = &devc->pwm_setting[which - 1];
 292         setting->freq = freq;
 293         setting->duty = duty;
 294
 295         return SR_OK;
 296 }
 297
 298 static int set_defaults(const struct sr_dev_inst *sdi)
 299 {
 300         struct dev_context *devc;
 301         int ret;
 302
 303         devc = sdi->priv;
 304
 305         devc->capture_ratio = 5; /* percent */
 306         devc->cur_channels = 0xffff;
 307         devc->limit_samples = 5000000;
 308         devc->cur_samplerate = 200000000;
 309
 310         ret = set_threshold_voltage(sdi, devc->threshold_voltage);
 311         if (ret)
 312                 return ret;
 313
 314         ret = enable_pwm(sdi, 0, 0);
 315         if (ret)
 316                 return ret;
 317
 318         ret = set_pwm(sdi, 1, 1e3, 50);
 319         if (ret)
 320                 return ret;
 321
 322         ret = set_pwm(sdi, 2, 100e3, 50);
 323         if (ret)
 324                 return ret;
 325
 326         ret = enable_pwm(sdi, 1, 1);
 327         if (ret)
 328                 return ret;
 329
 330         return SR_OK;
 331 }
 332
 333 static int set_trigger_config(const struct sr_dev_inst *sdi)
 334 {
 335         struct dev_context *devc;
 336         struct sr_trigger *trigger;
 337         trigger_cfg_t cfg;
 338         GSList *stages;
 339         GSList *channel;
 340         struct sr_trigger_stage *stage1;
 341         struct sr_trigger_match *match;
 342         uint16_t ch_mask;
 343         int ret;
 344         uint8_t buf[4 * sizeof(uint32_t)];
 345         uint8_t *wrptr;
 346
 347         devc = sdi->priv;
 348         trigger = sr_session_trigger_get(sdi->session);
 349
 350         memset(&cfg, 0, sizeof(cfg));
 351
 352         cfg.channels = devc->cur_channels;
 353
 354         if (trigger && trigger->stages) {
 355                 stages = trigger->stages;
 356                 stage1 = stages->data;
 357                 if (stages->next) {
 358                         sr_err("Only one trigger stage supported for now.");
 359                         return SR_ERR;
 360                 }
 361                 channel = stage1->matches;
 362                 while (channel) {
 363                         match = channel->data;
 364                         ch_mask = 1 << match->channel->index;
 365
 366                         switch (match->match) {
 367                         case SR_TRIGGER_ZERO:
 368                                 cfg.level |= ch_mask;
 369                                 cfg.high_or_falling &= ~ch_mask;
 370                                 break;
 371                         case SR_TRIGGER_ONE:
 372                                 cfg.level |= ch_mask;
 373                                 cfg.high_or_falling |= ch_mask;
 374                                 break;
 375                         case SR_TRIGGER_RISING:
 376                                 if ((cfg.enabled & ~cfg.level)) {
 377                                         sr_err("Only one trigger signal with falling-/rising-edge allowed.");
 378                                         return SR_ERR;
 379                                 }
 380                                 cfg.level &= ~ch_mask;
 381                                 cfg.high_or_falling &= ~ch_mask;
 382                                 break;
 383                         case SR_TRIGGER_FALLING:
 384                                 if ((cfg.enabled & ~cfg.level)) {
 385                                         sr_err("Only one trigger signal with falling-/rising-edge allowed.");
 386                                         return SR_ERR;
 387                                 }
 388                                 cfg.level &= ~ch_mask;
 389                                 cfg.high_or_falling |= ch_mask;
 390                                 break;
 391                         default:
 392                                 sr_err("Unknown trigger value.");
 393                                 return SR_ERR;
 394                         }
 395                         cfg.enabled |= ch_mask;
 396                         channel = channel->next;
 397                 }
 398         }
 399         sr_dbg("set trigger configuration channels: 0x%04x, "
 400                "trigger-enabled 0x%04x, level-triggered 0x%04x, "
 401                "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level,
 402                cfg.high_or_falling);
 403
 404         devc->had_triggers_configured = cfg.enabled != 0;
 405
 406         wrptr = buf;
 407         write_u32le_inc(&wrptr, cfg.channels);
 408         write_u32le_inc(&wrptr, cfg.enabled);
 409         write_u32le_inc(&wrptr, cfg.level);
 410         write_u32le_inc(&wrptr, cfg.high_or_falling);
 411         ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_TRIGGER, 16, buf, wrptr - buf);
 412         if (ret != SR_OK) {
 413                 sr_err("error setting trigger config!");
 414                 return ret;
 415         }
 416
 417         return SR_OK;
 418 }
 419
 420 static int set_sample_config(const struct sr_dev_inst *sdi)
 421 {
 422         struct dev_context *devc;
 423         double clock_divisor;
 424         uint64_t psa;
 425         uint64_t total;
 426         int ret;
 427         uint16_t divisor;
 428         uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)];
 429         uint8_t *wrptr;
 430
 431         devc = sdi->priv;
 432         total = 128 * 1024 * 1024;
 433
 434         if (devc->cur_samplerate > MAX_SAMPLE_RATE) {
 435                 sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate);
 436                 return SR_ERR;
 437         }
 438
 439         clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate;
 440         if (clock_divisor > 0xffff)
 441                 clock_divisor = 0xffff;
 442         divisor = (uint16_t)(clock_divisor + 0.5);
 443         devc->cur_samplerate = MAX_SAMPLE_RATE / divisor;
 444
 445         if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
 446                 sr_err("too high sample depth: %" PRIu64, devc->limit_samples);
 447                 return SR_ERR;
 448         }
 449
 450         devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100;
 451
 452         sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%",
 453                devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio);
 454
 455         psa = devc->pre_trigger_size * 256;
 456         wrptr = buf;
 457         write_u32le_inc(&wrptr, devc->limit_samples);
 458         write_u48le_inc(&wrptr, psa);
 459         write_u32le_inc(&wrptr, (total * devc->capture_ratio) / 100);
 460         write_u16le_inc(&wrptr, clock_divisor);
 461
 462         ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_SAMPLING, 0, buf, wrptr - buf);
 463         if (ret != SR_OK) {
 464                 sr_err("error setting sample config!");
 465                 return ret;
 466         }
 467
 468         return SR_OK;
 469 }
 470
 471 /**
 472  * lowest 2 bit are probably:
 473  * 2: recording
 474  * 1: finished
 475  * next 2 bit indicate whether we are still waiting for triggering
 476  * 0: waiting
 477  * 3: triggered
 478  */
 479 static uint16_t run_state(const struct sr_dev_inst *sdi)
 480 {
 481         uint16_t state;
 482         int ret;
 483
 484         if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, CTRL_RUN, 0, &state, sizeof(state))) != SR_OK) {
 485                 sr_err("failed to read run state!");
 486                 return ret;
 487         }
 488         sr_dbg("run_state: 0x%04x", state);
 489
 490         return state;
 491 }
 492
 493 static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking)
 494 {
 495         int ret;
 496
 497         if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) {
 498                 sr_err("failed to send set-run-mode command %d", fast_blinking);
 499                 return ret;
 500         }
 501
 502         return SR_OK;
 503 }
 504
 505 static int get_capture_info(const struct sr_dev_inst *sdi)
 506 {
 507         struct dev_context *devc;
 508         int ret;
 509         uint8_t buf[3 * sizeof(uint32_t)];
 510         const uint8_t *rdptr;
 511
 512         devc = sdi->priv;
 513
 514         if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, CTRL_BULK, 0, buf, sizeof(buf))) != SR_OK) {
 515                 sr_err("failed to read capture info!");
 516                 return ret;
 517         }
 518
 519         rdptr = buf;
 520         devc->info.n_rep_packets = read_u32le_inc(&rdptr);
 521         devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
 522         devc->info.write_pos = read_u32le_inc(&rdptr);
 523
 524         sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d",
 525                devc->info.n_rep_packets, devc->info.n_rep_packets,
 526                devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger,
 527                devc->info.write_pos, devc->info.write_pos);
 528
 529         if (devc->info.n_rep_packets % 5)
 530                 sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets);
 531
 532         return SR_OK;
 533 }
 534
 535 SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id)
 536 {
 537         char fw_file[1024];
 538         snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id);
 539         return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
 540 }
 541
 542 SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
 543 {
 544         struct dev_context *devc;
 545         int ret;
 546         uint8_t cmd;
 547
 548         devc = sdi->priv;
 549
 550         ret = set_threshold_voltage(sdi, devc->threshold_voltage);
 551         if (ret != SR_OK)
 552                 return ret;
 553
 554         cmd = 0;
 555         if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, 0x03, 0, &cmd, sizeof(cmd))) != SR_OK) {
 556                 sr_err("failed to send stop sampling command");
 557                 return ret;
 558         }
 559
 560         ret = set_trigger_config(sdi);
 561         if (ret != SR_OK)
 562                 return ret;
 563
 564         ret = set_sample_config(sdi);
 565         if (ret != SR_OK)
 566                 return ret;
 567
 568         return SR_OK;
 569 }
 570
 571 SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi)
 572 {
 573         return set_run_mode(sdi, 3);
 574 }
 575
 576 SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
 577 {
 578         return set_run_mode(sdi, 0);
 579 }
 580
 581 SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi)
 582 {
 583         return la2016_stop_acquisition(sdi);
 584 }
 585
 586 SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi)
 587 {
 588         uint16_t state;
 589
 590         state = run_state(sdi);
 591
 592         return (state & 0x3) == 1;
 593 }
 594
 595 SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb)
 596 {
 597         struct dev_context *devc;
 598         struct sr_usb_dev_inst *usb;
 599         int ret;
 600         uint8_t wrbuf[2 * sizeof(uint32_t)];
 601         uint8_t *wrptr;
 602         uint32_t to_read;
 603         uint8_t *buffer;
 604
 605         devc = sdi->priv;
 606         usb = sdi->conn;
 607
 608         if ((ret = get_capture_info(sdi)) != SR_OK)
 609                 return ret;
 610
 611         devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
 612         devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH;
 613         devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
 614         devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
 615
 616         sr_dbg("want to read %d tfer-packets starting from pos %d",
 617                devc->n_transfer_packets_to_read, devc->read_pos);
 618
 619         if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
 620                 sr_err("failed to reset bulk state");
 621                 return ret;
 622         }
 623         sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read);
 624         wrptr = wrbuf;
 625         write_u32le_inc(&wrptr, devc->read_pos);
 626         write_u32le_inc(&wrptr, devc->n_bytes_to_read);
 627         if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) {
 628                 sr_err("failed to send bulk config");
 629                 return ret;
 630         }
 631         if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) {
 632                 sr_err("failed to unblock bulk transfers");
 633                 return ret;
 634         }
 635
 636         to_read = devc->n_bytes_to_read;
 637         if (to_read > LA2016_BULK_MAX)
 638                 to_read = LA2016_BULK_MAX;
 639
 640         buffer = g_try_malloc(to_read);
 641         if (!buffer) {
 642                 sr_err("Failed to allocate %d bytes for bulk transfer", to_read);
 643                 return SR_ERR_MALLOC;
 644         }
 645
 646         devc->transfer = libusb_alloc_transfer(0);
 647         libusb_fill_bulk_transfer(
 648                 devc->transfer, usb->devhdl,
 649                 0x86, buffer, to_read,
 650                 cb, (void *)sdi, DEFAULT_TIMEOUT_MS);
 651
 652         if ((ret = libusb_submit_transfer(devc->transfer)) != 0) {
 653                 sr_err("Failed to submit transfer: %s.", libusb_error_name(ret));
 654                 libusb_free_transfer(devc->transfer);
 655                 devc->transfer = NULL;
 656                 g_free(buffer);
 657                 return SR_ERR;
 658         }
 659
 660         return SR_OK;
 661 }
 662
 663 SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi)
 664 {
 665         struct dev_context *devc;
 666         int ret;
 667         uint32_t i1;
 668         uint32_t i2[2];
 669         uint16_t state;
 670
 671         /* this unknown_cmd1 seems to depend on the FPGA bitstream */
 672         uint8_t unknown_cmd1_340[] = { 0xa3, 0x09, 0xc9, 0x8d, 0xe7, 0xad, 0x7a, 0x62, 0xb6, 0xd1, 0xbf };
 673         uint8_t unknown_cmd1_342[] = { 0xa3, 0x09, 0xc9, 0xf4, 0x32, 0x4c, 0x4d, 0xee, 0xab, 0xa0, 0xdd };
 674         uint8_t expected_unknown_resp1_340[] = { 0xa3, 0x10, 0xda, 0x66, 0x6b, 0x93, 0x5c, 0x55, 0x38, 0x50, 0x39, 0x51, 0x98, 0x86, 0x5d, 0x06, 0x7c, 0xea };
 675         uint8_t expected_unknown_resp1_342[] = { 0xa3, 0x10, 0xb3, 0x92, 0x7b, 0xd8, 0x6b, 0xca, 0xa5, 0xab, 0x42, 0x6e, 0xda, 0xcd, 0x9d, 0xf1, 0x31, 0x2f };
 676         uint8_t unknown_resp1[sizeof(expected_unknown_resp1_340)];
 677         uint8_t *expected_unknown_resp1;
 678         uint8_t *unknown_cmd1;
 679
 680         uint8_t unknown_cmd2[] = { 0xa3, 0x01, 0xca };
 681         uint8_t expected_unknown_resp2[] = { 0xa3, 0x08, 0x06, 0x83, 0x96, 0x29, 0x15, 0xe1, 0x92, 0x74, 0x00, 0x00 };
 682         uint8_t unknown_resp2[sizeof(expected_unknown_resp2)];
 683
 684         devc = sdi->priv;
 685
 686         if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, &i1, sizeof(i1))) != SR_OK) {
 687                 sr_err("failed to read i1");
 688                 return ret;
 689         }
 690         sr_dbg("i1: 0x%08x", i1);
 691
 692         if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &i2, sizeof(i2))) != SR_OK) {
 693                 sr_err("failed to read i2");
 694                 return ret;
 695         }
 696         sr_dbg("i2: 0x%08x, 0x%08x", i2[0], i2[1]);
 697
 698         if ((ret = upload_fpga_bitstream(sdi)) != SR_OK) {
 699                 sr_err("failed to upload fpga bitstream");
 700                 return ret;
 701         }
 702
 703         if (run_state(sdi) == 0xffff) {
 704                 sr_err("run_state after fpga bitstream upload is 0xffff!");
 705                 return SR_ERR;
 706         }
 707
 708         if (devc->bitstream_size == 0x2b602) {
 709                 // v3.4.0
 710                 unknown_cmd1 = unknown_cmd1_340;
 711                 expected_unknown_resp1 = expected_unknown_resp1_340;
 712         } else {
 713                 // v3.4.2
 714                 if (devc->bitstream_size != 0x2b839)
 715                         sr_warn("the FPGA bitstream size %d is unknown. tested bistreams from vendor's version 3.4.0 and 3.4.2\n", devc->bitstream_size);
 716                 unknown_cmd1 = unknown_cmd1_342;
 717                 expected_unknown_resp1 = expected_unknown_resp1_342;
 718         }
 719         if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1_340))) != SR_OK) {
 720                 sr_err("failed to send unknown_cmd1");
 721                 return ret;
 722         }
 723         g_usleep(80 * 1000);
 724         if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) {
 725                 sr_err("failed to read unknown_resp1");
 726                 return ret;
 727         }
 728         if (memcmp(unknown_resp1, expected_unknown_resp1, sizeof(unknown_resp1)))
 729                 sr_dbg("unknown_cmd1 response is not as expected, this is to be expected...");
 730
 731         state = run_state(sdi);
 732         if (state != 0x85e9)
 733                 sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state);
 734
 735         if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) {
 736                 sr_err("failed to send unknown_cmd2");
 737                 return ret;
 738         }
 739         g_usleep(80 * 1000);
 740         if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) {
 741                 sr_err("failed to read unknown_resp2");
 742                 return ret;
 743         }
 744         if (memcmp(unknown_resp2, expected_unknown_resp2, sizeof(unknown_resp2)))
 745                 sr_dbg("unknown_cmd2 response is not as expected!");
 746
 747         if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
 748                 sr_err("failed to send unknown_cmd3");
 749                 return ret;
 750         }
 751         sr_dbg("device should be initialized");
 752
 753         return set_defaults(sdi);
 754 }
 755
 756 SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi)
 757 {
 758         int ret;
 759
 760         if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) {
 761                 sr_err("failed to send deinit command");
 762                 return ret;
 763         }
 764
 765         return SR_OK;
 766 }