2 * This file is part of the libsigrok project.
4 * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
5 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
6 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
7 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
27 #include <glib/gstdio.h>
32 #include <libsigrok/libsigrok.h>
33 #include "libsigrok-internal.h"
36 #define FPGA_FIRMWARE "kingst-la2016a-fpga.bitstream"
37 #define UC_FIRMWARE "kingst-la-%04x.fw"
39 #define MAX_SAMPLE_RATE SR_MHZ(200)
40 #define MAX_SAMPLE_DEPTH 10e9
41 #define MAX_PWM_FREQ SR_MHZ(20)
42 #define PWM_CLOCK SR_MHZ(200)
44 /* usb vendor class control requests to the cypress FX2 microcontroller */
45 #define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */
46 #define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */
47 #define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */
48 #define CMD_FPGA_ENABLE 0x10
49 #define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */
50 #define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */
51 #define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */
54 * fpga spi register addresses for control request CMD_FPGA_SPI:
55 * There are around 60 byte-wide registers within the fpga and
56 * these are the base addresses used for accessing them.
57 * On the spi bus, the msb of the address byte is set for read
58 * and cleared for write, but that is handled by the fx2 mcu
59 * as appropriate. In this driver code just use IN transactions
60 * to read, OUT to write.
62 #define REG_RUN 0x00 /* read capture status, write capture start */
63 #define REG_PWM_EN 0x02 /* user pwm channels on/off */
64 #define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */
65 #define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */
66 #define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */
67 #define REG_TRIGGER 0x20 /* write level and edge trigger config */
68 #define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */
69 #define REG_PWM1 0x70 /* write config for user pwm1 */
70 #define REG_PWM2 0x78 /* write config for user pwm2 */
72 static int ctrl_in(const struct sr_dev_inst *sdi,
73 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
74 void *data, uint16_t wLength)
76 struct sr_usb_dev_inst *usb;
81 if ((ret = libusb_control_transfer(
82 usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
83 bRequest, wValue, wIndex, (unsigned char *)data, wLength,
84 DEFAULT_TIMEOUT_MS)) != wLength) {
85 sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.",
86 wLength, bRequest, wValue, wIndex,
87 libusb_error_name(ret));
94 static int ctrl_out(const struct sr_dev_inst *sdi,
95 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
96 void *data, uint16_t wLength)
98 struct sr_usb_dev_inst *usb;
103 if ((ret = libusb_control_transfer(
104 usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
105 bRequest, wValue, wIndex, (unsigned char*)data, wLength,
106 DEFAULT_TIMEOUT_MS)) != wLength) {
107 sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.",
108 wLength, bRequest, wValue, wIndex,
109 libusb_error_name(ret));
116 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi)
118 struct dev_context *devc;
119 struct drv_context *drvc;
120 struct sr_usb_dev_inst *usb;
121 struct sr_resource bitstream;
122 uint8_t buffer[sizeof(uint32_t)];
129 unsigned int zero_pad_to = 0x2c000;
132 drvc = sdi->driver->context;
135 sr_info("Uploading FPGA bitstream '%s'.", FPGA_FIRMWARE);
137 ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, FPGA_FIRMWARE);
139 sr_err("could not find la2016 firmware %s!", FPGA_FIRMWARE);
143 devc->bitstream_size = (uint32_t)bitstream.size;
145 write_u32le_inc(&wrptr, devc->bitstream_size);
146 if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
147 sr_err("failed to give upload init command");
148 sr_resource_close(drvc->sr_ctx, &bitstream);
154 if (pos < bitstream.size) {
155 len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block));
157 sr_err("failed to read from fpga bitstream!");
158 sr_resource_close(drvc->sr_ctx, &bitstream);
162 // fill with zero's until zero_pad_to
163 len = zero_pad_to - pos;
164 if ((unsigned)len > sizeof(block))
166 memset(&block, 0, len);
171 ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
173 sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret));
177 if (act_len != len) {
178 sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len);
184 sr_resource_close(drvc->sr_ctx, &bitstream);
187 sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size);
189 if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
190 sr_err("failed to read response after FPGA bitstream upload");
194 sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp);
200 if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) {
201 sr_err("failed enable fpga");
209 static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
211 struct dev_context *devc;
212 float o1, o2, v1, v2, f;
214 uint8_t buffer[sizeof(uint32_t)];
219 o1 = 15859969; v1 = 0.45;
220 o2 = 15860333; v2 = 1.65;
221 f = (o2 - o1) / (v2 - v1);
222 cfgval = (uint32_t)(o1 + (voltage - v1) * f);
223 sr_dbg("set threshold voltage %.2fV, raw value 0x%lx",
224 voltage, (unsigned long)cfgval);
227 write_u32le_inc(&wrptr, cfgval);
228 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buffer, wrptr - buffer);
230 sr_err("Error setting %.2fV threshold voltage (%d)",
234 devc->threshold_voltage = voltage;
239 static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2)
241 struct dev_context *devc;
248 if (p1) cfg |= 1 << 0;
249 if (p2) cfg |= 1 << 1;
251 sr_dbg("set pwm enable %d %d", p1, p2);
252 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg));
254 sr_err("error setting new pwm enable 0x%02x", cfg);
257 devc->pwm_setting[0].enabled = (p1) ? 1 : 0;
258 devc->pwm_setting[1].enabled = (p2) ? 1 : 0;
263 static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty)
265 int CTRL_PWM[] = { REG_PWM1, REG_PWM2 };
266 struct dev_context *devc;
267 pwm_setting_dev_t cfg;
268 pwm_setting_t *setting;
270 uint8_t buf[2 * sizeof(uint32_t)];
275 if (which < 1 || which > 2) {
276 sr_err("invalid pwm channel: %d", which);
279 if (freq > MAX_PWM_FREQ) {
280 sr_err("pwm frequency too high: %.1f", freq);
283 if (duty > 100 || duty < 0) {
284 sr_err("invalid pwm percentage: %f", duty);
288 cfg.period = (uint32_t)(PWM_CLOCK / freq);
289 cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.));
290 sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty);
293 write_u32le_inc(&wrptr, cfg.period);
294 write_u32le_inc(&wrptr, cfg.duty);
295 ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf);
297 sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty);
300 setting = &devc->pwm_setting[which - 1];
301 setting->freq = freq;
302 setting->duty = duty;
307 static int set_defaults(const struct sr_dev_inst *sdi)
309 struct dev_context *devc;
314 devc->capture_ratio = 5; /* percent */
315 devc->cur_channels = 0xffff;
316 devc->limit_samples = 5000000;
317 devc->cur_samplerate = 200000000;
319 ret = set_threshold_voltage(sdi, devc->threshold_voltage);
323 ret = enable_pwm(sdi, 0, 0);
327 ret = set_pwm(sdi, 1, 1e3, 50);
331 ret = set_pwm(sdi, 2, 100e3, 50);
335 ret = enable_pwm(sdi, 1, 1);
342 static int set_trigger_config(const struct sr_dev_inst *sdi)
344 struct dev_context *devc;
345 struct sr_trigger *trigger;
349 struct sr_trigger_stage *stage1;
350 struct sr_trigger_match *match;
353 uint8_t buf[4 * sizeof(uint32_t)];
357 trigger = sr_session_trigger_get(sdi->session);
359 memset(&cfg, 0, sizeof(cfg));
361 cfg.channels = devc->cur_channels;
363 if (trigger && trigger->stages) {
364 stages = trigger->stages;
365 stage1 = stages->data;
367 sr_err("Only one trigger stage supported for now.");
370 channel = stage1->matches;
372 match = channel->data;
373 ch_mask = 1 << match->channel->index;
375 switch (match->match) {
376 case SR_TRIGGER_ZERO:
377 cfg.level |= ch_mask;
378 cfg.high_or_falling &= ~ch_mask;
381 cfg.level |= ch_mask;
382 cfg.high_or_falling |= ch_mask;
384 case SR_TRIGGER_RISING:
385 if ((cfg.enabled & ~cfg.level)) {
386 sr_err("Only one trigger signal with falling-/rising-edge allowed.");
389 cfg.level &= ~ch_mask;
390 cfg.high_or_falling &= ~ch_mask;
392 case SR_TRIGGER_FALLING:
393 if ((cfg.enabled & ~cfg.level)) {
394 sr_err("Only one trigger signal with falling-/rising-edge allowed.");
397 cfg.level &= ~ch_mask;
398 cfg.high_or_falling |= ch_mask;
401 sr_err("Unknown trigger value.");
404 cfg.enabled |= ch_mask;
405 channel = channel->next;
408 sr_dbg("set trigger configuration channels: 0x%04x, "
409 "trigger-enabled 0x%04x, level-triggered 0x%04x, "
410 "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level,
411 cfg.high_or_falling);
413 devc->had_triggers_configured = cfg.enabled != 0;
416 write_u32le_inc(&wrptr, cfg.channels);
417 write_u32le_inc(&wrptr, cfg.enabled);
418 write_u32le_inc(&wrptr, cfg.level);
419 write_u32le_inc(&wrptr, cfg.high_or_falling);
420 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf);
422 sr_err("error setting trigger config!");
429 static int set_sample_config(const struct sr_dev_inst *sdi)
431 struct dev_context *devc;
432 double clock_divisor;
437 uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)];
441 total = 128 * 1024 * 1024;
443 if (devc->cur_samplerate > MAX_SAMPLE_RATE) {
444 sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate);
448 clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate;
449 if (clock_divisor > 0xffff)
450 clock_divisor = 0xffff;
451 divisor = (uint16_t)(clock_divisor + 0.5);
452 devc->cur_samplerate = MAX_SAMPLE_RATE / divisor;
454 if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
455 sr_err("too high sample depth: %" PRIu64, devc->limit_samples);
459 devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100;
461 sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%",
462 devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio);
464 psa = devc->pre_trigger_size * 256;
466 write_u32le_inc(&wrptr, devc->limit_samples);
467 write_u48le_inc(&wrptr, psa);
468 write_u32le_inc(&wrptr, (total * devc->capture_ratio) / 100);
469 write_u16le_inc(&wrptr, clock_divisor);
471 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf);
473 sr_err("error setting sample config!");
481 * lowest 2 bit are probably:
484 * next 2 bit indicate whether we are still waiting for triggering
488 static uint16_t run_state(const struct sr_dev_inst *sdi)
493 if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) {
494 sr_err("failed to read run state!");
497 sr_dbg("run_state: 0x%04x", state);
502 static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking)
506 if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) {
507 sr_err("failed to send set-run-mode command %d", fast_blinking);
514 static int get_capture_info(const struct sr_dev_inst *sdi)
516 struct dev_context *devc;
518 uint8_t buf[3 * sizeof(uint32_t)];
519 const uint8_t *rdptr;
523 if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) {
524 sr_err("failed to read capture info!");
529 devc->info.n_rep_packets = read_u32le_inc(&rdptr);
530 devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
531 devc->info.write_pos = read_u32le_inc(&rdptr);
533 sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d",
534 devc->info.n_rep_packets, devc->info.n_rep_packets,
535 devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger,
536 devc->info.write_pos, devc->info.write_pos);
538 if (devc->info.n_rep_packets % 5)
539 sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets);
544 SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id)
547 snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id);
548 return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
551 SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
553 struct dev_context *devc;
559 ret = set_threshold_voltage(sdi, devc->threshold_voltage);
564 if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) {
565 sr_err("failed to send stop sampling command");
569 ret = set_trigger_config(sdi);
573 ret = set_sample_config(sdi);
580 SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi)
582 return set_run_mode(sdi, 3);
585 SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
587 return set_run_mode(sdi, 0);
590 SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi)
592 return la2016_stop_acquisition(sdi);
595 SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi)
599 state = run_state(sdi);
601 return (state & 0x3) == 1;
604 SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb)
606 struct dev_context *devc;
607 struct sr_usb_dev_inst *usb;
609 uint8_t wrbuf[2 * sizeof(uint32_t)];
617 if ((ret = get_capture_info(sdi)) != SR_OK)
620 devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
621 devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH;
622 devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
623 devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
625 sr_dbg("want to read %d tfer-packets starting from pos %d",
626 devc->n_transfer_packets_to_read, devc->read_pos);
628 if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
629 sr_err("failed to reset bulk state");
632 sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read);
634 write_u32le_inc(&wrptr, devc->read_pos);
635 write_u32le_inc(&wrptr, devc->n_bytes_to_read);
636 if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) {
637 sr_err("failed to send bulk config");
640 if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) {
641 sr_err("failed to unblock bulk transfers");
645 to_read = devc->n_bytes_to_read;
646 if (to_read > LA2016_BULK_MAX)
647 to_read = LA2016_BULK_MAX;
649 buffer = g_try_malloc(to_read);
651 sr_err("Failed to allocate %d bytes for bulk transfer", to_read);
652 return SR_ERR_MALLOC;
655 devc->transfer = libusb_alloc_transfer(0);
656 libusb_fill_bulk_transfer(
657 devc->transfer, usb->devhdl,
658 0x86, buffer, to_read,
659 cb, (void *)sdi, DEFAULT_TIMEOUT_MS);
661 if ((ret = libusb_submit_transfer(devc->transfer)) != 0) {
662 sr_err("Failed to submit transfer: %s.", libusb_error_name(ret));
663 libusb_free_transfer(devc->transfer);
664 devc->transfer = NULL;
672 SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi)
674 struct dev_context *devc;
680 /* this unknown_cmd1 seems to depend on the FPGA bitstream */
681 uint8_t unknown_cmd1_340[] = { 0xa3, 0x09, 0xc9, 0x8d, 0xe7, 0xad, 0x7a, 0x62, 0xb6, 0xd1, 0xbf };
682 uint8_t unknown_cmd1_342[] = { 0xa3, 0x09, 0xc9, 0xf4, 0x32, 0x4c, 0x4d, 0xee, 0xab, 0xa0, 0xdd };
683 uint8_t expected_unknown_resp1_340[] = { 0xa3, 0x10, 0xda, 0x66, 0x6b, 0x93, 0x5c, 0x55, 0x38, 0x50, 0x39, 0x51, 0x98, 0x86, 0x5d, 0x06, 0x7c, 0xea };
684 uint8_t expected_unknown_resp1_342[] = { 0xa3, 0x10, 0xb3, 0x92, 0x7b, 0xd8, 0x6b, 0xca, 0xa5, 0xab, 0x42, 0x6e, 0xda, 0xcd, 0x9d, 0xf1, 0x31, 0x2f };
685 uint8_t unknown_resp1[sizeof(expected_unknown_resp1_340)];
686 uint8_t *expected_unknown_resp1;
687 uint8_t *unknown_cmd1;
689 uint8_t unknown_cmd2[] = { 0xa3, 0x01, 0xca };
690 uint8_t expected_unknown_resp2[] = { 0xa3, 0x08, 0x06, 0x83, 0x96, 0x29, 0x15, 0xe1, 0x92, 0x74, 0x00, 0x00 };
691 uint8_t unknown_resp2[sizeof(expected_unknown_resp2)];
695 if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, &i1, sizeof(i1))) != SR_OK) {
696 sr_err("failed to read i1");
699 sr_dbg("i1: 0x%08x", i1);
701 if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &i2, sizeof(i2))) != SR_OK) {
702 sr_err("failed to read i2");
705 sr_dbg("i2: 0x%08x, 0x%08x", i2[0], i2[1]);
707 if ((ret = upload_fpga_bitstream(sdi)) != SR_OK) {
708 sr_err("failed to upload fpga bitstream");
712 if (run_state(sdi) == 0xffff) {
713 sr_err("run_state after fpga bitstream upload is 0xffff!");
717 if (devc->bitstream_size == 0x2b602) {
719 unknown_cmd1 = unknown_cmd1_340;
720 expected_unknown_resp1 = expected_unknown_resp1_340;
723 if (devc->bitstream_size != 0x2b839)
724 sr_warn("the FPGA bitstream size %d is unknown. tested bistreams from vendor's version 3.4.0 and 3.4.2\n", devc->bitstream_size);
725 unknown_cmd1 = unknown_cmd1_342;
726 expected_unknown_resp1 = expected_unknown_resp1_342;
728 if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1_340))) != SR_OK) {
729 sr_err("failed to send unknown_cmd1");
733 if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) {
734 sr_err("failed to read unknown_resp1");
737 if (memcmp(unknown_resp1, expected_unknown_resp1, sizeof(unknown_resp1)))
738 sr_dbg("unknown_cmd1 response is not as expected, this is to be expected...");
740 state = run_state(sdi);
742 sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state);
744 if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) {
745 sr_err("failed to send unknown_cmd2");
749 if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) {
750 sr_err("failed to read unknown_resp2");
753 if (memcmp(unknown_resp2, expected_unknown_resp2, sizeof(unknown_resp2)))
754 sr_dbg("unknown_cmd2 response is not as expected!");
756 if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
757 sr_err("failed to send unknown_cmd3");
760 sr_dbg("device should be initialized");
762 return set_defaults(sdi);
765 SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi)
769 if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) {
770 sr_err("failed to send deinit command");