kingst-la2016: Eliminate non-portable packed structs for USB transfer layout
[libsigrok.git] / src / hardware / kingst-la2016 / protocol.c
1 /*
2  * This file is part of the libsigrok project.
3  *
4  * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
5  * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
6  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
7  * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation, either version 3 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22
23 #include <config.h>
24 #include <stdint.h>
25 #include <string.h>
26 #include <glib.h>
27 #include <glib/gstdio.h>
28 #include <stdio.h>
29 #include <errno.h>
30 #include <math.h>
31 #include <inttypes.h>
32 #include <libsigrok/libsigrok.h>
33 #include "libsigrok-internal.h"
34 #include "protocol.h"
35
36 #define FPGA_FIRMWARE   "kingst-la2016a-fpga.bitstream"
37 #define UC_FIRMWARE     "kingst-la-%04x.fw"
38
39 #define MAX_SAMPLE_RATE  SR_MHZ(200)
40 #define MAX_SAMPLE_DEPTH 10e9
41 #define MAX_PWM_FREQ     SR_MHZ(20)
42 #define PWM_CLOCK        SR_MHZ(200)
43
44 /* registers for control request 32: */
45 #define CTRL_RUN         0x00
46 #define CTRL_PWM_EN      0x02
47 #define CTRL_BULK        0x10 /* can be read to get 12 byte sampling_info (III) */
48 #define CTRL_SAMPLING    0x20
49 #define CTRL_TRIGGER     0x30
50 #define CTRL_THRESHOLD   0x48
51 #define CTRL_PWM1        0x70
52 #define CTRL_PWM2        0x78
53
54 static int ctrl_in(const struct sr_dev_inst *sdi,
55                    uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
56                    void *data, uint16_t wLength)
57 {
58         struct sr_usb_dev_inst *usb;
59         int ret;
60
61         usb = sdi->conn;
62
63         if ((ret = libusb_control_transfer(
64                      usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
65                      bRequest, wValue, wIndex, (unsigned char *)data, wLength,
66                      DEFAULT_TIMEOUT_MS)) != wLength) {
67                 sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.",
68                        wLength, bRequest, wValue, wIndex,
69                        libusb_error_name(ret));
70                 return SR_ERR;
71         }
72
73         return SR_OK;
74 }
75
76 static int ctrl_out(const struct sr_dev_inst *sdi,
77                     uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
78                     void *data, uint16_t wLength)
79 {
80         struct sr_usb_dev_inst *usb;
81         int ret;
82
83         usb = sdi->conn;
84
85         if ((ret = libusb_control_transfer(
86                      usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
87                      bRequest, wValue, wIndex, (unsigned char*)data, wLength,
88                      DEFAULT_TIMEOUT_MS)) != wLength) {
89                 sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.",
90                        wLength, bRequest, wValue, wIndex,
91                        libusb_error_name(ret));
92                 return SR_ERR;
93         }
94
95         return SR_OK;
96 }
97
98 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi)
99 {
100         struct dev_context *devc;
101         struct drv_context *drvc;
102         struct sr_usb_dev_inst *usb;
103         struct sr_resource bitstream;
104         uint8_t buffer[sizeof(uint32_t)];
105         uint8_t *wrptr;
106         uint8_t cmd_resp;
107         uint8_t block[4096];
108         int len, act_len;
109         unsigned int pos;
110         int ret;
111         unsigned int zero_pad_to = 0x2c000;
112
113         devc = sdi->priv;
114         drvc = sdi->driver->context;
115         usb = sdi->conn;
116
117         sr_info("Uploading FPGA bitstream '%s'.", FPGA_FIRMWARE);
118
119         ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, FPGA_FIRMWARE);
120         if (ret != SR_OK) {
121                 sr_err("could not find la2016 firmware %s!", FPGA_FIRMWARE);
122                 return ret;
123         }
124
125         devc->bitstream_size = (uint32_t)bitstream.size;
126         wrptr = buffer;
127         write_u32le_inc(&wrptr, devc->bitstream_size);
128         if ((ret = ctrl_out(sdi, 80, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
129                 sr_err("failed to give upload init command");
130                 sr_resource_close(drvc->sr_ctx, &bitstream);
131                 return ret;
132         }
133
134         pos = 0;
135         while (1) {
136                 if (pos < bitstream.size) {
137                         len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block));
138                         if (len < 0) {
139                                 sr_err("failed to read from fpga bitstream!");
140                                 sr_resource_close(drvc->sr_ctx, &bitstream);
141                                 return SR_ERR;
142                         }
143                 } else {
144                         // fill with zero's until zero_pad_to
145                         len = zero_pad_to - pos;
146                         if ((unsigned)len > sizeof(block))
147                                 len = sizeof(block);
148                         memset(&block, 0, len);
149                 }
150                 if (len == 0)
151                         break;
152
153                 ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
154                 if (ret != 0) {
155                         sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret));
156                         ret = SR_ERR;
157                         break;
158                 }
159                 if (act_len != len) {
160                         sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len);
161                         ret = SR_ERR;
162                         break;
163                 }
164                 pos += len;
165         }
166         sr_resource_close(drvc->sr_ctx, &bitstream);
167         if (ret != 0)
168                 return ret;
169         sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size);
170
171         if ((ret = ctrl_in(sdi, 80, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
172                 sr_err("failed to read response after FPGA bitstream upload");
173                 return ret;
174         }
175         if (cmd_resp != 0) {
176                 sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp);
177                 return SR_ERR;
178         }
179
180         g_usleep(30000);
181
182         if ((ret = ctrl_out(sdi, 16, 0x01, 0, NULL, 0)) != SR_OK) {
183                 sr_err("failed enable fpga");
184                 return ret;
185         }
186
187         g_usleep(40000);
188         return SR_OK;
189 }
190
191 static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
192 {
193         struct dev_context *devc;
194         float o1, o2, v1, v2, f;
195         uint32_t cfgval;
196         uint8_t buffer[sizeof(uint32_t)];
197         uint8_t *wrptr;
198         int ret;
199
200         devc = sdi->priv;
201         o1 = 15859969; v1 = 0.45;
202         o2 = 15860333; v2 = 1.65;
203         f = (o2 - o1) / (v2 - v1);
204         cfgval = (uint32_t)(o1 + (voltage - v1) * f);
205         sr_dbg("set threshold voltage %.2fV, raw value 0x%lx",
206                 voltage, (unsigned long)cfgval);
207
208         wrptr = buffer;
209         write_u32le_inc(&wrptr, cfgval);
210         ret = ctrl_out(sdi, 32, CTRL_THRESHOLD, 0, buffer, wrptr - buffer);
211         if (ret != SR_OK) {
212                 sr_err("Error setting %.2fV threshold voltage (%d)",
213                         voltage, ret);
214                 return ret;
215         }
216         devc->threshold_voltage = voltage;
217
218         return SR_OK;
219 }
220
221 static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2)
222 {
223         struct dev_context *devc;
224         uint8_t cfg;
225         int ret;
226
227         devc = sdi->priv;
228         cfg = 0;
229
230         if (p1) cfg |= 1 << 0;
231         if (p2) cfg |= 1 << 1;
232
233         sr_dbg("set pwm enable %d %d", p1, p2);
234         ret = ctrl_out(sdi, 32, CTRL_PWM_EN, 0, &cfg, sizeof(cfg));
235         if (ret != SR_OK) {
236                 sr_err("error setting new pwm enable 0x%02x", cfg);
237                 return ret;
238         }
239         devc->pwm_setting[0].enabled = (p1) ? 1 : 0;
240         devc->pwm_setting[1].enabled = (p2) ? 1 : 0;
241
242         return SR_OK;
243 }
244
245 static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty)
246 {
247         int CTRL_PWM[] = { CTRL_PWM1, CTRL_PWM2 };
248         struct dev_context *devc;
249         pwm_setting_dev_t cfg;
250         pwm_setting_t *setting;
251         int ret;
252         uint8_t buf[2 * sizeof(uint32_t)];
253         uint8_t *wrptr;
254
255         devc = sdi->priv;
256
257         if (which < 1 || which > 2) {
258                 sr_err("invalid pwm channel: %d", which);
259                 return SR_ERR;
260         }
261         if (freq > MAX_PWM_FREQ) {
262                 sr_err("pwm frequency too high: %.1f", freq);
263                 return SR_ERR;
264         }
265         if (duty > 100 || duty < 0) {
266                 sr_err("invalid pwm percentage: %f", duty);
267                 return SR_ERR;
268         }
269
270         cfg.period = (uint32_t)(PWM_CLOCK / freq);
271         cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.));
272         sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty);
273
274         wrptr = buf;
275         write_u32le_inc(&wrptr, cfg.period);
276         write_u32le_inc(&wrptr, cfg.duty);
277         ret = ctrl_out(sdi, 32, CTRL_PWM[which - 1], 0, buf, wrptr - buf);
278         if (ret != SR_OK) {
279                 sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty);
280                 return ret;
281         }
282         setting = &devc->pwm_setting[which - 1];
283         setting->freq = freq;
284         setting->duty = duty;
285
286         return SR_OK;
287 }
288
289 static int set_defaults(const struct sr_dev_inst *sdi)
290 {
291         struct dev_context *devc;
292         int ret;
293
294         devc = sdi->priv;
295
296         devc->capture_ratio = 5; /* percent */
297         devc->cur_channels = 0xffff;
298         devc->limit_samples = 5000000;
299         devc->cur_samplerate = 200000000;
300
301         ret = set_threshold_voltage(sdi, devc->threshold_voltage);
302         if (ret)
303                 return ret;
304
305         ret = enable_pwm(sdi, 0, 0);
306         if (ret)
307                 return ret;
308
309         ret = set_pwm(sdi, 1, 1e3, 50);
310         if (ret)
311                 return ret;
312
313         ret = set_pwm(sdi, 2, 100e3, 50);
314         if (ret)
315                 return ret;
316
317         ret = enable_pwm(sdi, 1, 1);
318         if (ret)
319                 return ret;
320
321         return SR_OK;
322 }
323
324 static int set_trigger_config(const struct sr_dev_inst *sdi)
325 {
326         struct dev_context *devc;
327         struct sr_trigger *trigger;
328         trigger_cfg_t cfg;
329         GSList *stages;
330         GSList *channel;
331         struct sr_trigger_stage *stage1;
332         struct sr_trigger_match *match;
333         uint16_t ch_mask;
334         int ret;
335         uint8_t buf[4 * sizeof(uint32_t)];
336         uint8_t *wrptr;
337
338         devc = sdi->priv;
339         trigger = sr_session_trigger_get(sdi->session);
340
341         memset(&cfg, 0, sizeof(cfg));
342
343         cfg.channels = devc->cur_channels;
344
345         if (trigger && trigger->stages) {
346                 stages = trigger->stages;
347                 stage1 = stages->data;
348                 if (stages->next) {
349                         sr_err("Only one trigger stage supported for now.");
350                         return SR_ERR;
351                 }
352                 channel = stage1->matches;
353                 while (channel) {
354                         match = channel->data;
355                         ch_mask = 1 << match->channel->index;
356
357                         switch (match->match) {
358                         case SR_TRIGGER_ZERO:
359                                 cfg.level |= ch_mask;
360                                 cfg.high_or_falling &= ~ch_mask;
361                                 break;
362                         case SR_TRIGGER_ONE:
363                                 cfg.level |= ch_mask;
364                                 cfg.high_or_falling |= ch_mask;
365                                 break;
366                         case SR_TRIGGER_RISING:
367                                 if ((cfg.enabled & ~cfg.level)) {
368                                         sr_err("Only one trigger signal with falling-/rising-edge allowed.");
369                                         return SR_ERR;
370                                 }
371                                 cfg.level &= ~ch_mask;
372                                 cfg.high_or_falling &= ~ch_mask;
373                                 break;
374                         case SR_TRIGGER_FALLING:
375                                 if ((cfg.enabled & ~cfg.level)) {
376                                         sr_err("Only one trigger signal with falling-/rising-edge allowed.");
377                                         return SR_ERR;
378                                 }
379                                 cfg.level &= ~ch_mask;
380                                 cfg.high_or_falling |= ch_mask;
381                                 break;
382                         default:
383                                 sr_err("Unknown trigger value.");
384                                 return SR_ERR;
385                         }
386                         cfg.enabled |= ch_mask;
387                         channel = channel->next;
388                 }
389         }
390         sr_dbg("set trigger configuration channels: 0x%04x, "
391                "trigger-enabled 0x%04x, level-triggered 0x%04x, "
392                "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level,
393                cfg.high_or_falling);
394
395         devc->had_triggers_configured = cfg.enabled != 0;
396
397         wrptr = buf;
398         write_u32le_inc(&wrptr, cfg.channels);
399         write_u32le_inc(&wrptr, cfg.enabled);
400         write_u32le_inc(&wrptr, cfg.level);
401         write_u32le_inc(&wrptr, cfg.high_or_falling);
402         ret = ctrl_out(sdi, 32, CTRL_TRIGGER, 16, buf, wrptr - buf);
403         if (ret != SR_OK) {
404                 sr_err("error setting trigger config!");
405                 return ret;
406         }
407
408         return SR_OK;
409 }
410
411 static int set_sample_config(const struct sr_dev_inst *sdi)
412 {
413         struct dev_context *devc;
414         double clock_divisor;
415         uint64_t psa;
416         uint64_t total;
417         int ret;
418         uint16_t divisor;
419         uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)];
420         uint8_t *wrptr;
421
422         devc = sdi->priv;
423         total = 128 * 1024 * 1024;
424
425         if (devc->cur_samplerate > MAX_SAMPLE_RATE) {
426                 sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate);
427                 return SR_ERR;
428         }
429
430         clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate;
431         if (clock_divisor > 0xffff)
432                 clock_divisor = 0xffff;
433         divisor = (uint16_t)(clock_divisor + 0.5);
434         devc->cur_samplerate = MAX_SAMPLE_RATE / divisor;
435
436         if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
437                 sr_err("too high sample depth: %" PRIu64, devc->limit_samples);
438                 return SR_ERR;
439         }
440
441         devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100;
442
443         sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%",
444                devc->cur_samplerate/1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio);
445
446         psa = devc->pre_trigger_size * 256;
447         wrptr = buf;
448         write_u32le_inc(&wrptr, devc->limit_samples);
449         write_u48le_inc(&wrptr, psa);
450         write_u32le_inc(&wrptr, (total * devc->capture_ratio) / 100);
451         write_u16le_inc(&wrptr, clock_divisor);
452
453         ret = ctrl_out(sdi, 32, CTRL_SAMPLING, 0, buf, wrptr - buf);
454         if (ret != SR_OK) {
455                 sr_err("error setting sample config!");
456                 return ret;
457         }
458
459         return SR_OK;
460 }
461
462 /**
463  * lowest 2 bit are probably:
464  * 2: recording
465  * 1: finished
466  * next 2 bit indicate whether we are still waiting for triggering
467  * 0: waiting
468  * 3: triggered
469  */
470 static uint16_t run_state(const struct sr_dev_inst *sdi)
471 {
472         uint16_t state;
473         int ret;
474
475         if ((ret = ctrl_in(sdi, 32, CTRL_RUN, 0, &state, sizeof(state))) != SR_OK) {
476                 sr_err("failed to read run state!");
477                 return ret;
478         }
479         sr_dbg("run_state: 0x%04x", state);
480
481         return state;
482 }
483
484 static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking)
485 {
486         int ret;
487
488         if ((ret = ctrl_out(sdi, 32, CTRL_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) {
489                 sr_err("failed to send set-run-mode command %d", fast_blinking);
490                 return ret;
491         }
492
493         return SR_OK;
494 }
495
496 static int get_capture_info(const struct sr_dev_inst *sdi)
497 {
498         struct dev_context *devc;
499         int ret;
500         uint8_t buf[3 * sizeof(uint32_t)];
501         const uint8_t *rdptr;
502
503         devc = sdi->priv;
504
505         if ((ret = ctrl_in(sdi, 32, CTRL_BULK, 0, buf, sizeof(buf))) != SR_OK) {
506                 sr_err("failed to read capture info!");
507                 return ret;
508         }
509
510         rdptr = buf;
511         devc->info.n_rep_packets = read_u32le_inc(&rdptr);
512         devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
513         devc->info.write_pos = read_u32le_inc(&rdptr);
514
515         sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d",
516                devc->info.n_rep_packets, devc->info.n_rep_packets,
517                devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger,
518                devc->info.write_pos, devc->info.write_pos);
519
520         if (devc->info.n_rep_packets % 5)
521                 sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets);
522
523         return SR_OK;
524 }
525
526 SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id)
527 {
528         char fw_file[1024];
529         snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id);
530         return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
531 }
532
533 SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
534 {
535         struct dev_context *devc;
536         int ret;
537         uint8_t cmd;
538
539         devc = sdi->priv;
540
541         ret = set_threshold_voltage(sdi, devc->threshold_voltage);
542         if (ret != SR_OK)
543                 return ret;
544
545         cmd = 0;
546         if ((ret = ctrl_out(sdi, 32, 0x03, 0, &cmd, sizeof(cmd))) != SR_OK) {
547                 sr_err("failed to send stop sampling command");
548                 return ret;
549         }
550
551         ret = set_trigger_config(sdi);
552         if (ret != SR_OK)
553                 return ret;
554
555         ret = set_sample_config(sdi);
556         if (ret != SR_OK)
557                 return ret;
558
559         return SR_OK;
560 }
561
562 SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi)
563 {
564         return set_run_mode(sdi, 3);
565 }
566
567 SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
568 {
569         return set_run_mode(sdi, 0);
570 }
571
572 SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi)
573 {
574         return la2016_stop_acquisition(sdi);
575 }
576
577 SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi)
578 {
579         uint16_t state;
580
581         state = run_state(sdi);
582
583         return (state & 0x3) == 1;
584 }
585
586 SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb)
587 {
588         struct dev_context *devc;
589         struct sr_usb_dev_inst *usb;
590         int ret;
591         uint8_t wrbuf[2 * sizeof(uint32_t)];
592         uint8_t *wrptr;
593         uint32_t to_read;
594         uint8_t *buffer;
595
596         devc = sdi->priv;
597         usb = sdi->conn;
598
599         if ((ret = get_capture_info(sdi)) != SR_OK)
600                 return ret;
601
602         devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
603         devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH;
604         devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
605         devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
606
607         sr_dbg("want to read %d tfer-packets starting from pos %d",
608                devc->n_transfer_packets_to_read, devc->read_pos);
609
610         if ((ret = ctrl_out(sdi, 56, 0x00, 0, NULL, 0)) != SR_OK) {
611                 sr_err("failed to reset bulk state");
612                 return ret;
613         }
614         sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read);
615         wrptr = wrbuf;
616         write_u32le_inc(&wrptr, devc->read_pos);
617         write_u32le_inc(&wrptr, devc->n_bytes_to_read);
618         if ((ret = ctrl_out(sdi, 32, CTRL_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) {
619                 sr_err("failed to send bulk config");
620                 return ret;
621         }
622         if ((ret = ctrl_out(sdi, 48, 0x00, 0, NULL, 0)) != SR_OK) {
623                 sr_err("failed to unblock bulk transfers");
624                 return ret;
625         }
626
627         to_read = devc->n_bytes_to_read;
628         if (to_read > LA2016_BULK_MAX)
629                 to_read = LA2016_BULK_MAX;
630
631         buffer = g_try_malloc(to_read);
632         if (!buffer) {
633                 sr_err("Failed to allocate %d bytes for bulk transfer", to_read);
634                 return SR_ERR_MALLOC;
635         }
636
637         devc->transfer = libusb_alloc_transfer(0);
638         libusb_fill_bulk_transfer(
639                 devc->transfer, usb->devhdl,
640                 0x86, buffer, to_read,
641                 cb, (void *)sdi, DEFAULT_TIMEOUT_MS);
642
643         if ((ret = libusb_submit_transfer(devc->transfer)) != 0) {
644                 sr_err("Failed to submit transfer: %s.", libusb_error_name(ret));
645                 libusb_free_transfer(devc->transfer);
646                 devc->transfer = NULL;
647                 g_free(buffer);
648                 return SR_ERR;
649         }
650
651         return SR_OK;
652 }
653
654 SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi)
655 {
656         struct dev_context *devc;
657         int ret;
658         uint32_t i1;
659         uint32_t i2[2];
660         uint16_t state;
661
662         /* this unknown_cmd1 seems to depend on the FPGA bitstream */
663         uint8_t unknown_cmd1_340[] = { 0xa3, 0x09, 0xc9, 0x8d, 0xe7, 0xad, 0x7a, 0x62, 0xb6, 0xd1, 0xbf };
664         uint8_t unknown_cmd1_342[] = { 0xa3, 0x09, 0xc9, 0xf4, 0x32, 0x4c, 0x4d, 0xee, 0xab, 0xa0, 0xdd };
665         uint8_t expected_unknown_resp1_340[] = { 0xa3, 0x10, 0xda, 0x66, 0x6b, 0x93, 0x5c, 0x55, 0x38, 0x50, 0x39, 0x51, 0x98, 0x86, 0x5d, 0x06, 0x7c, 0xea };
666         uint8_t expected_unknown_resp1_342[] = { 0xa3, 0x10, 0xb3, 0x92, 0x7b, 0xd8, 0x6b, 0xca, 0xa5, 0xab, 0x42, 0x6e, 0xda, 0xcd, 0x9d, 0xf1, 0x31, 0x2f };
667         uint8_t unknown_resp1[sizeof(expected_unknown_resp1_340)];
668         uint8_t *expected_unknown_resp1;
669         uint8_t *unknown_cmd1;
670
671         uint8_t unknown_cmd2[] = { 0xa3, 0x01, 0xca };
672         uint8_t expected_unknown_resp2[] = { 0xa3, 0x08, 0x06, 0x83, 0x96, 0x29, 0x15, 0xe1, 0x92, 0x74, 0x00, 0x00 };
673         uint8_t unknown_resp2[sizeof(expected_unknown_resp2)];
674
675         devc = sdi->priv;
676
677         if ((ret = ctrl_in(sdi, 162, 0x20, 0, &i1, sizeof(i1))) != SR_OK) {
678                 sr_err("failed to read i1");
679                 return ret;
680         }
681         sr_dbg("i1: 0x%08x", i1);
682
683         if ((ret = ctrl_in(sdi, 162, 0x08, 0, &i2, sizeof(i2))) != SR_OK) {
684                 sr_err("failed to read i2");
685                 return ret;
686         }
687         sr_dbg("i2: 0x%08x, 0x%08x", i2[0], i2[1]);
688
689         if ((ret = upload_fpga_bitstream(sdi)) != SR_OK) {
690                 sr_err("failed to upload fpga bitstream");
691                 return ret;
692         }
693
694         if (run_state(sdi) == 0xffff) {
695                 sr_err("run_state after fpga bitstream upload is 0xffff!");
696                 return SR_ERR;
697         }
698
699         if (devc->bitstream_size == 0x2b602) {
700                 // v3.4.0
701                 unknown_cmd1 = unknown_cmd1_340;
702                 expected_unknown_resp1 = expected_unknown_resp1_340;
703         } else {
704                 // v3.4.2
705                 if (devc->bitstream_size != 0x2b839)
706                         sr_warn("the FPGA bitstream size %d is unknown. tested bistreams from vendor's version 3.4.0 and 3.4.2\n", devc->bitstream_size);
707                 unknown_cmd1 = unknown_cmd1_342;
708                 expected_unknown_resp1 = expected_unknown_resp1_342;
709         }
710         if ((ret = ctrl_out(sdi, 96, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1_340))) != SR_OK) {
711                 sr_err("failed to send unknown_cmd1");
712                 return ret;
713         }
714         g_usleep(80 * 1000);
715         if ((ret = ctrl_in(sdi, 96, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) {
716                 sr_err("failed to read unknown_resp1");
717                 return ret;
718         }
719         if (memcmp(unknown_resp1, expected_unknown_resp1, sizeof(unknown_resp1)))
720                 sr_dbg("unknown_cmd1 response is not as expected, this is to be expected...");
721
722         state = run_state(sdi);
723         if (state != 0x85e9)
724                 sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state);
725
726         if ((ret = ctrl_out(sdi, 96, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) {
727                 sr_err("failed to send unknown_cmd2");
728                 return ret;
729         }
730         g_usleep(80 * 1000);
731         if ((ret = ctrl_in(sdi, 96, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) {
732                 sr_err("failed to read unknown_resp2");
733                 return ret;
734         }
735         if (memcmp(unknown_resp2, expected_unknown_resp2, sizeof(unknown_resp2)))
736                 sr_dbg("unknown_cmd2 response is not as expected!");
737
738         if ((ret = ctrl_out(sdi, 56, 0x00, 0, NULL, 0)) != SR_OK) {
739                 sr_err("failed to send unknown_cmd3");
740                 return ret;
741         }
742         sr_dbg("device should be initialized");
743
744         return set_defaults(sdi);
745 }
746
747 SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi)
748 {
749         int ret;
750
751         if ((ret = ctrl_out(sdi, 16, 0x00, 0, NULL, 0)) != SR_OK) {
752                 sr_err("failed to send deinit command");
753                 return ret;
754         }
755
756         return SR_OK;
757 }