hardware/sysclk-lwla/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 3 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "protocol.h"
  21 #include <string.h>
  22
  23 /* Bit mask for the RLE repeat-count-follows flag. */
  24 #define RLE_FLAG_LEN_FOLLOWS ((uint64_t)1 << 35)
  25
  26 /* Start address of capture status memory area to read. */
  27 #define CAP_STAT_ADDR 5
  28
  29 /* Number of 64-bit words read from the capture status memory. */
  30 #define CAP_STAT_LEN 5
  31
  32 /* The bitstream filenames are indexed by the clock_config enumeration.
  33  */
  34 static const char bitstream_map[][32] = {
  35         "sysclk-lwla1034-off.rbf",
  36         "sysclk-lwla1034-int.rbf",
  37         "sysclk-lwla1034-extpos.rbf",
  38         "sysclk-lwla1034-extneg.rbf",
  39 };
  40
  41 /* Submit an already filled-in USB transfer.
  42  */
  43 static int submit_transfer(struct dev_context *devc,
  44                            struct libusb_transfer *xfer)
  45 {
  46         int ret;
  47
  48         ret = libusb_submit_transfer(xfer);
  49
  50         if (ret != 0) {
  51                 sr_err("Submit transfer failed: %s.", libusb_error_name(ret));
  52                 devc->transfer_error = TRUE;
  53                 return SR_ERR;
  54         }
  55
  56         return SR_OK;
  57 }
  58
  59 /* Set up the LWLA in preparation for an acquisition session.
  60  */
  61 static int capture_setup(const struct sr_dev_inst *sdi)
  62 {
  63         struct dev_context *devc;
  64         struct acquisition_state *acq;
  65         uint64_t divider_count;
  66         uint64_t trigger_mask;
  67         uint64_t memory_limit;
  68         uint16_t command[3 + 10*4];
  69
  70         devc = sdi->priv;
  71         acq  = devc->acquisition;
  72
  73         command[0] = LWLA_WORD(CMD_CAP_SETUP);
  74         command[1] = LWLA_WORD(0); /* address */
  75         command[2] = LWLA_WORD(10); /* length */
  76
  77         command[3] = LWLA_WORD_0(devc->channel_mask);
  78         command[4] = LWLA_WORD_1(devc->channel_mask);
  79         command[5] = LWLA_WORD_2(devc->channel_mask);
  80         command[6] = LWLA_WORD_3(devc->channel_mask);
  81
  82         /* Set the clock divide counter maximum for samplerates of up to
  83          * 100 MHz. At the highest samplerate of 125 MHz the clock divider
  84          * is bypassed.
  85          */
  86         if (!acq->bypass_clockdiv && devc->samplerate > 0)
  87                 divider_count = SR_MHZ(100) / devc->samplerate - 1;
  88         else
  89                 divider_count = 0;
  90
  91         command[7]  = LWLA_WORD_0(divider_count);
  92         command[8]  = LWLA_WORD_1(divider_count);
  93         command[9]  = LWLA_WORD_2(divider_count);
  94         command[10] = LWLA_WORD_3(divider_count);
  95
  96         command[11] = LWLA_WORD_0(devc->trigger_values);
  97         command[12] = LWLA_WORD_1(devc->trigger_values);
  98         command[13] = LWLA_WORD_2(devc->trigger_values);
  99         command[14] = LWLA_WORD_3(devc->trigger_values);
 100
 101         command[15] = LWLA_WORD_0(devc->trigger_edge_mask);
 102         command[16] = LWLA_WORD_1(devc->trigger_edge_mask);
 103         command[17] = LWLA_WORD_2(devc->trigger_edge_mask);
 104         command[18] = LWLA_WORD_3(devc->trigger_edge_mask);
 105
 106         trigger_mask = devc->trigger_mask;
 107         /* Set bits to select external TRG input edge. */
 108         if (devc->cfg_trigger_source == TRIGGER_EXT_TRG)
 109                 switch (devc->cfg_trigger_slope) {
 110                 case EDGE_POSITIVE: trigger_mask |= (uint64_t)1 << 35; break;
 111                 case EDGE_NEGATIVE: trigger_mask |= (uint64_t)1 << 34; break;
 112                 }
 113
 114         command[19] = LWLA_WORD_0(trigger_mask);
 115         command[20] = LWLA_WORD_1(trigger_mask);
 116         command[21] = LWLA_WORD_2(trigger_mask);
 117         command[22] = LWLA_WORD_3(trigger_mask);
 118
 119         /* Set the capture memory full threshold. This is slightly less
 120          * than the actual maximum, most likely in order to compensate for
 121          * pipeline latency.
 122          */
 123         memory_limit = MEMORY_DEPTH - 16;
 124
 125         command[23] = LWLA_WORD_0(memory_limit);
 126         command[24] = LWLA_WORD_1(memory_limit);
 127         command[25] = LWLA_WORD_2(memory_limit);
 128         command[26] = LWLA_WORD_3(memory_limit);
 129
 130         /* Fill remaining 64-bit words with zeroes. */
 131         memset(&command[27], 0, 16 * sizeof(uint16_t));
 132
 133         return lwla_send_command(sdi->conn, command, G_N_ELEMENTS(command));
 134 }
 135
 136 /* Issue a register write command as an asynchronous USB transfer.
 137  */
 138 static int issue_write_reg(const struct sr_dev_inst *sdi,
 139                            unsigned int reg, unsigned int value)
 140 {
 141         struct dev_context *devc;
 142         struct acquisition_state *acq;
 143
 144         devc = sdi->priv;
 145         acq  = devc->acquisition;
 146
 147         acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_REG);
 148         acq->xfer_buf_out[1] = LWLA_WORD(reg);
 149         acq->xfer_buf_out[2] = LWLA_WORD_0(value);
 150         acq->xfer_buf_out[3] = LWLA_WORD_1(value);
 151
 152         acq->xfer_out->length = 4 * sizeof(uint16_t);
 153
 154         return submit_transfer(devc, acq->xfer_out);
 155 }
 156
 157 /* Issue a register write command as an asynchronous USB transfer for the
 158  * next register/value pair of the currently active register write sequence.
 159  */
 160 static int issue_next_write_reg(const struct sr_dev_inst *sdi)
 161 {
 162         struct dev_context *devc;
 163         struct regval_pair *regval;
 164         int ret;
 165
 166         devc = sdi->priv;
 167
 168         if (devc->reg_write_pos >= devc->reg_write_len) {
 169                 sr_err("Already written all registers in sequence.");
 170                 return SR_ERR_BUG;
 171         }
 172         regval = &devc->reg_write_seq[devc->reg_write_pos];
 173
 174         ret = issue_write_reg(sdi, regval->reg, regval->val);
 175         if (ret != SR_OK)
 176                 return ret;
 177
 178         ++devc->reg_write_pos;
 179         return SR_OK;
 180 }
 181
 182 /* Issue a capture status request as an asynchronous USB transfer.
 183  */
 184 static void request_capture_status(const struct sr_dev_inst *sdi)
 185 {
 186         struct dev_context *devc;
 187         struct acquisition_state *acq;
 188
 189         devc = sdi->priv;
 190         acq  = devc->acquisition;
 191
 192         acq->xfer_buf_out[0] = LWLA_WORD(CMD_CAP_STATUS);
 193         acq->xfer_buf_out[1] = LWLA_WORD(CAP_STAT_ADDR);
 194         acq->xfer_buf_out[2] = LWLA_WORD(CAP_STAT_LEN);
 195
 196         acq->xfer_out->length = 3 * sizeof(uint16_t);
 197
 198         if (submit_transfer(devc, acq->xfer_out) == SR_OK)
 199                 devc->state = STATE_STATUS_REQUEST;
 200 }
 201
 202 /* Issue a request for the capture buffer fill level as
 203  * an asynchronous USB transfer.
 204  */
 205 static void request_capture_length(const struct sr_dev_inst *sdi)
 206 {
 207         struct dev_context *devc;
 208         struct acquisition_state *acq;
 209
 210         devc = sdi->priv;
 211         acq  = devc->acquisition;
 212
 213         acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_REG);
 214         acq->xfer_buf_out[1] = LWLA_WORD(REG_MEM_FILL);
 215
 216         acq->xfer_out->length = 2 * sizeof(uint16_t);
 217
 218         if (submit_transfer(devc, acq->xfer_out) == SR_OK)
 219                 devc->state = STATE_LENGTH_REQUEST;
 220 }
 221
 222 /* Initiate the capture memory read operation:  Reset the acquisition state
 223  * and start a sequence of register writes in order to set up the device for
 224  * reading from the capture buffer.
 225  */
 226 static void issue_read_start(const struct sr_dev_inst *sdi)
 227 {
 228         struct dev_context *devc;
 229         struct acquisition_state *acq;
 230         struct regval_pair *regvals;
 231
 232         devc = sdi->priv;
 233         acq  = devc->acquisition;
 234
 235         /* Reset RLE state. */
 236         acq->rle = RLE_STATE_DATA;
 237         acq->sample  = 0;
 238         acq->run_len = 0;
 239
 240         acq->samples_done = 0;
 241
 242         /* For some reason, the start address is 4 rather than 0. */
 243         acq->mem_addr_done = 4;
 244         acq->mem_addr_next = 4;
 245         acq->mem_addr_stop = acq->mem_addr_fill;
 246
 247         /* Sample position in the packet output buffer. */
 248         acq->out_index = 0;
 249
 250         regvals = devc->reg_write_seq;
 251
 252         regvals[0].reg = REG_DIV_BYPASS;
 253         regvals[0].val = 1;
 254
 255         regvals[1].reg = REG_MEM_CTRL2;
 256         regvals[1].val = 2;
 257
 258         regvals[2].reg = REG_MEM_CTRL4;
 259         regvals[2].val = 4;
 260
 261         devc->reg_write_pos = 0;
 262         devc->reg_write_len = 3;
 263
 264         if (issue_next_write_reg(sdi) == SR_OK)
 265                 devc->state = STATE_READ_PREPARE;
 266 }
 267
 268 /* Issue a command as an asynchronous USB transfer which returns the device
 269  * to normal state after a read operation.  Sets a new device context state
 270  * on success.
 271  */
 272 static void issue_read_end(const struct sr_dev_inst *sdi)
 273 {
 274         struct dev_context *devc;
 275
 276         devc = sdi->priv;
 277
 278         if (issue_write_reg(sdi, REG_DIV_BYPASS, 0) == SR_OK)
 279                 devc->state = STATE_READ_END;
 280 }
 281
 282 /* Decode an incoming reponse to a buffer fill level request and act on it
 283  * as appropriate.  Note that this function changes the device context state.
 284  */
 285 static void process_capture_length(const struct sr_dev_inst *sdi)
 286 {
 287         struct dev_context *devc;
 288         struct acquisition_state *acq;
 289
 290         devc = sdi->priv;
 291         acq  = devc->acquisition;
 292
 293         if (acq->xfer_in->actual_length != 4) {
 294                 sr_err("Received size %d doesn't match expected size 4.",
 295                        acq->xfer_in->actual_length);
 296                 devc->transfer_error = TRUE;
 297                 return;
 298         }
 299         acq->mem_addr_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
 300
 301         sr_dbg("%zu words in capture buffer.", acq->mem_addr_fill);
 302
 303         if (acq->mem_addr_fill > 0 && sdi->status == SR_ST_ACTIVE)
 304                 issue_read_start(sdi);
 305         else
 306                 issue_read_end(sdi);
 307 }
 308
 309 /* Initiate a sequence of register write commands with the effect of
 310  * cancelling a running capture operation.  This sets a new device state
 311  * if issuing the first command succeeds.
 312  */
 313 static void issue_stop_capture(const struct sr_dev_inst *sdi)
 314 {
 315         struct dev_context *devc;
 316         struct regval_pair *regvals;
 317
 318         devc = sdi->priv;
 319
 320         if (devc->stopping_in_progress)
 321                 return;
 322
 323         regvals = devc->reg_write_seq;
 324
 325         regvals[0].reg = REG_CMD_CTRL2;
 326         regvals[0].val = 10;
 327
 328         regvals[1].reg = REG_CMD_CTRL3;
 329         regvals[1].val = 0;
 330
 331         regvals[2].reg = REG_CMD_CTRL4;
 332         regvals[2].val = 0;
 333
 334         regvals[3].reg = REG_CMD_CTRL1;
 335         regvals[3].val = 0;
 336
 337         regvals[4].reg = REG_DIV_BYPASS;
 338         regvals[4].val = 0;
 339
 340         devc->reg_write_pos = 0;
 341         devc->reg_write_len = 5;
 342
 343         if (issue_next_write_reg(sdi) == SR_OK) {
 344                 devc->stopping_in_progress = TRUE;
 345                 devc->state = STATE_STOP_CAPTURE;
 346         }
 347 }
 348
 349 /* Decode an incoming capture status reponse and act on it as appropriate.
 350  * Note that this function changes the device state.
 351  */
 352 static void process_capture_status(const struct sr_dev_inst *sdi)
 353 {
 354         uint64_t duration;
 355         struct dev_context *devc;
 356         struct acquisition_state *acq;
 357         unsigned int mem_fill;
 358         unsigned int flags;
 359
 360         devc = sdi->priv;
 361         acq  = devc->acquisition;
 362
 363         if (acq->xfer_in->actual_length != CAP_STAT_LEN * 8) {
 364                 sr_err("Received size %d doesn't match expected size %d.",
 365                        acq->xfer_in->actual_length, CAP_STAT_LEN * 8);
 366                 devc->transfer_error = TRUE;
 367                 return;
 368         }
 369
 370         /* TODO: Find out the actual bit width of these fields as stored
 371          * in the FPGA.  These fields are definitely less than 64 bit wide
 372          * internally, and the unused bits occasionally even contain garbage.
 373          */
 374         mem_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
 375         duration = LWLA_TO_UINT32(acq->xfer_buf_in[4]);
 376         flags    = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
 377
 378         /* The LWLA1034 runs at 125 MHz if the clock divider is bypassed.
 379          * However, the time base used for the duration is apparently not
 380          * adjusted for this "boost" mode.  Whereas normally the duration
 381          * unit is 1 ms, it is 0.8 ms when the clock divider is bypassed.
 382          * As 0.8 = 100 MHz / 125 MHz, it seems that the internal cycle
 383          * counter period is the same as at the 100 MHz setting.
 384          */
 385         if (acq->bypass_clockdiv)
 386                 acq->duration_now = duration * 4 / 5;
 387         else
 388                 acq->duration_now = duration;
 389
 390         sr_spew("Captured %u words, %" PRIu64 " ms, flags 0x%02X.",
 391                 mem_fill, acq->duration_now, flags);
 392
 393         if ((flags & STATUS_TRIGGERED) > (acq->capture_flags & STATUS_TRIGGERED))
 394                 sr_info("Capture triggered.");
 395
 396         acq->capture_flags = flags;
 397
 398         if (acq->duration_now >= acq->duration_max) {
 399                 sr_dbg("Time limit reached, stopping capture.");
 400                 issue_stop_capture(sdi);
 401                 return;
 402         }
 403         devc->state = STATE_STATUS_WAIT;
 404
 405         if ((acq->capture_flags & STATUS_TRIGGERED) == 0) {
 406                 sr_spew("Waiting for trigger.");
 407         } else if ((acq->capture_flags & STATUS_MEM_AVAIL) == 0) {
 408                 sr_dbg("Capture memory filled.");
 409                 request_capture_length(sdi);
 410         } else if ((acq->capture_flags & STATUS_CAPTURING) != 0) {
 411                 sr_spew("Sampling in progress.");
 412         }
 413 }
 414
 415 /* Issue a capture buffer read request as an asynchronous USB transfer.
 416  * The address and size of the memory area to read are derived from the
 417  * current acquisition state.
 418  */
 419 static void request_read_mem(const struct sr_dev_inst *sdi)
 420 {
 421         struct dev_context *devc;
 422         struct acquisition_state *acq;
 423         size_t count;
 424
 425         devc = sdi->priv;
 426         acq  = devc->acquisition;
 427
 428         if (acq->mem_addr_next >= acq->mem_addr_stop)
 429                 return;
 430
 431         /* Always read a multiple of 8 device words. */
 432         count = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8;
 433         count = MIN(count, READ_CHUNK_LEN);
 434
 435         acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM);
 436         acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
 437         acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
 438         acq->xfer_buf_out[3] = LWLA_WORD_0(count);
 439         acq->xfer_buf_out[4] = LWLA_WORD_1(count);
 440
 441         acq->xfer_out->length = 5 * sizeof(uint16_t);
 442
 443         if (submit_transfer(devc, acq->xfer_out) == SR_OK) {
 444                 acq->mem_addr_next += count;
 445                 devc->state = STATE_READ_REQUEST;
 446         }
 447 }
 448
 449 /* Demangle and decompress incoming sample data from the capture buffer.
 450  * The data chunk is taken from the acquisition state, and is expected to
 451  * contain a multiple of 8 device words.
 452  * All data currently in the acquisition buffer will be processed.  Packets
 453  * of decoded samples are sent off to the session bus whenever the output
 454  * buffer becomes full while decoding.
 455  */
 456 static int process_sample_data(const struct sr_dev_inst *sdi)
 457 {
 458         uint64_t sample;
 459         uint64_t high_nibbles;
 460         uint64_t word;
 461         struct dev_context *devc;
 462         struct acquisition_state *acq;
 463         uint8_t *out_p;
 464         uint32_t *slice;
 465         struct sr_datafeed_packet packet;
 466         struct sr_datafeed_logic logic;
 467         size_t expect_len;
 468         size_t actual_len;
 469         size_t out_max_samples;
 470         size_t out_run_samples;
 471         size_t ri;
 472         size_t in_words_left;
 473         size_t si;
 474
 475         devc = sdi->priv;
 476         acq  = devc->acquisition;
 477
 478         if (acq->mem_addr_done >= acq->mem_addr_stop
 479                         || acq->samples_done >= acq->samples_max)
 480                 return SR_OK;
 481
 482         in_words_left = MIN(acq->mem_addr_stop - acq->mem_addr_done,
 483                             READ_CHUNK_LEN);
 484         expect_len = LWLA1034_MEMBUF_LEN(in_words_left) * sizeof(uint32_t);
 485         actual_len = acq->xfer_in->actual_length;
 486
 487         if (actual_len != expect_len) {
 488                 sr_err("Received size %zu does not match expected size %zu.",
 489                        actual_len, expect_len);
 490                 devc->transfer_error = TRUE;
 491                 return SR_ERR;
 492         }
 493         acq->mem_addr_done += in_words_left;
 494
 495         /* Prepare session packet. */
 496         packet.type    = SR_DF_LOGIC;
 497         packet.payload = &logic;
 498         logic.unitsize = UNIT_SIZE;
 499         logic.data     = acq->out_packet;
 500
 501         slice = acq->xfer_buf_in;
 502         si = 0; /* word index within slice */
 503
 504         for (;;) {
 505                 /* Calculate number of samples to write into packet. */
 506                 out_max_samples = MIN(acq->samples_max - acq->samples_done,
 507                                       PACKET_LENGTH - acq->out_index);
 508                 out_run_samples = MIN(acq->run_len, out_max_samples);
 509
 510                 /* Expand run-length samples into session packet. */
 511                 sample = acq->sample;
 512                 out_p = &acq->out_packet[acq->out_index * UNIT_SIZE];
 513
 514                 for (ri = 0; ri < out_run_samples; ++ri) {
 515                         out_p[0] =  sample        & 0xFF;
 516                         out_p[1] = (sample >>  8) & 0xFF;
 517                         out_p[2] = (sample >> 16) & 0xFF;
 518                         out_p[3] = (sample >> 24) & 0xFF;
 519                         out_p[4] = (sample >> 32) & 0xFF;
 520                         out_p += UNIT_SIZE;
 521                 }
 522                 acq->run_len -= out_run_samples;
 523                 acq->out_index += out_run_samples;
 524                 acq->samples_done += out_run_samples;
 525
 526                 /* Packet full or sample count limit reached? */
 527                 if (out_run_samples == out_max_samples) {
 528                         logic.length = acq->out_index * UNIT_SIZE;
 529                         sr_session_send(sdi, &packet);
 530                         acq->out_index = 0;
 531
 532                         if (acq->samples_done >= acq->samples_max)
 533                                 return SR_OK; /* sample limit reached */
 534                         if (acq->run_len > 0)
 535                                 continue; /* need another packet */
 536                 }
 537
 538                 if (in_words_left == 0)
 539                         break; /* done with current chunk */
 540
 541                 /* Now work on the current slice. */
 542                 high_nibbles = LWLA_TO_UINT32(slice[8]);
 543                 word = LWLA_TO_UINT32(slice[si]);
 544                 word |= (high_nibbles << (4 * si + 4)) & ((uint64_t)0xF << 32);
 545
 546                 if (acq->rle == RLE_STATE_DATA) {
 547                         acq->sample = word & ALL_CHANNELS_MASK;
 548                         acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1;
 549                         if (word & RLE_FLAG_LEN_FOLLOWS)
 550                                 acq->rle = RLE_STATE_LEN;
 551                 } else {
 552                         acq->run_len += word << 1;
 553                         acq->rle = RLE_STATE_DATA;
 554                 }
 555
 556                 /* Move to next word. */
 557                 si = (si + 1) % 8;
 558                 if (si == 0)
 559                         slice += 9;
 560                 --in_words_left;
 561         }
 562
 563         /* Send out partially filled packet if this was the last chunk. */
 564         if (acq->mem_addr_done >= acq->mem_addr_stop && acq->out_index > 0) {
 565                 logic.length = acq->out_index * UNIT_SIZE;
 566                 sr_session_send(sdi, &packet);
 567                 acq->out_index = 0;
 568         }
 569         return SR_OK;
 570 }
 571
 572 /* Finish an acquisition session.  This sends the end packet to the session
 573  * bus and removes the listener for asynchronous USB transfers.
 574  */
 575 static void end_acquisition(struct sr_dev_inst *sdi)
 576 {
 577         struct drv_context *drvc;
 578         struct dev_context *devc;
 579         struct sr_datafeed_packet packet;
 580
 581         drvc = sdi->driver->priv;
 582         devc = sdi->priv;
 583
 584         if (devc->state == STATE_IDLE)
 585                 return;
 586
 587         devc->state = STATE_IDLE;
 588
 589         /* Remove USB file descriptors from polling. */
 590         usb_source_remove(sdi->session, drvc->sr_ctx);
 591
 592         packet.type = SR_DF_END;
 593         sr_session_send(sdi, &packet);
 594
 595         lwla_free_acquisition_state(devc->acquisition);
 596         devc->acquisition = NULL;
 597
 598         sdi->status = SR_ST_ACTIVE;
 599 }
 600
 601 /* USB output transfer completion callback.
 602  */
 603 static void receive_transfer_out(struct libusb_transfer *transfer)
 604 {
 605         struct sr_dev_inst *sdi;
 606         struct dev_context *devc;
 607
 608         sdi  = transfer->user_data;
 609         devc = sdi->priv;
 610
 611         if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
 612                 sr_err("Transfer to device failed: %d.", transfer->status);
 613                 devc->transfer_error = TRUE;
 614                 return;
 615         }
 616
 617         if (devc->reg_write_pos < devc->reg_write_len) {
 618                 issue_next_write_reg(sdi);
 619         } else {
 620                 switch (devc->state) {
 621                 case STATE_START_CAPTURE:
 622                         devc->state = STATE_STATUS_WAIT;
 623                         break;
 624                 case STATE_STATUS_REQUEST:
 625                         devc->state = STATE_STATUS_RESPONSE;
 626                         submit_transfer(devc, devc->acquisition->xfer_in);
 627                         break;
 628                 case STATE_STOP_CAPTURE:
 629                         if (sdi->status == SR_ST_ACTIVE)
 630                                 request_capture_length(sdi);
 631                         else
 632                                 end_acquisition(sdi);
 633                         break;
 634                 case STATE_LENGTH_REQUEST:
 635                         devc->state = STATE_LENGTH_RESPONSE;
 636                         submit_transfer(devc, devc->acquisition->xfer_in);
 637                         break;
 638                 case STATE_READ_PREPARE:
 639                         request_read_mem(sdi);
 640                         break;
 641                 case STATE_READ_REQUEST:
 642                         devc->state = STATE_READ_RESPONSE;
 643                         submit_transfer(devc, devc->acquisition->xfer_in);
 644                         break;
 645                 case STATE_READ_END:
 646                         end_acquisition(sdi);
 647                         break;
 648                 default:
 649                         sr_err("Unexpected device state %d.", devc->state);
 650                         break;
 651                 }
 652         }
 653 }
 654
 655 /* USB input transfer completion callback.
 656  */
 657 static void receive_transfer_in(struct libusb_transfer *transfer)
 658 {
 659         struct sr_dev_inst *sdi;
 660         struct dev_context *devc;
 661         struct acquisition_state *acq;
 662
 663         sdi  = transfer->user_data;
 664         devc = sdi->priv;
 665         acq  = devc->acquisition;
 666
 667         if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
 668                 sr_err("Transfer from device failed: %d.", transfer->status);
 669                 devc->transfer_error = TRUE;
 670                 return;
 671         }
 672
 673         switch (devc->state) {
 674         case STATE_STATUS_RESPONSE:
 675                 process_capture_status(sdi);
 676                 break;
 677         case STATE_LENGTH_RESPONSE:
 678                 process_capture_length(sdi);
 679                 break;
 680         case STATE_READ_RESPONSE:
 681                 if (process_sample_data(sdi) == SR_OK
 682                                 && acq->mem_addr_next < acq->mem_addr_stop
 683                                 && acq->samples_done < acq->samples_max)
 684                         request_read_mem(sdi);
 685                 else
 686                         issue_read_end(sdi);
 687                 break;
 688         default:
 689                 sr_err("Unexpected device state %d.", devc->state);
 690                 break;
 691         }
 692 }
 693
 694 /* Initialize the LWLA.  This downloads a bitstream into the FPGA
 695  * and executes a simple device test sequence.
 696  */
 697 SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
 698 {
 699         struct dev_context *devc;
 700         int ret;
 701         uint32_t value;
 702
 703         devc = sdi->priv;
 704
 705         /* Force reload of bitstream */
 706         devc->cur_clock_config = CONF_CLOCK_NONE;
 707
 708         ret = lwla_set_clock_config(sdi);
 709
 710         if (ret != SR_OK)
 711                 return ret;
 712
 713         ret = lwla_write_reg(sdi->conn, REG_CMD_CTRL2, 100);
 714         if (ret != SR_OK)
 715                 return ret;
 716
 717         ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL1, &value);
 718         if (ret != SR_OK)
 719                 return ret;
 720         sr_dbg("Received test word 0x%08X back.", value);
 721         if (value != 0x12345678)
 722                 return SR_ERR;
 723
 724         ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL4, &value);
 725         if (ret != SR_OK)
 726                 return ret;
 727         sr_dbg("Received test word 0x%08X back.", value);
 728         if (value != 0x12345678)
 729                 return SR_ERR;
 730
 731         ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL3, &value);
 732         if (ret != SR_OK)
 733                 return ret;
 734         sr_dbg("Received test word 0x%08X back.", value);
 735         if (value != 0x87654321)
 736                 return SR_ERR;
 737
 738         return ret;
 739 }
 740
 741 SR_PRIV int lwla_convert_trigger(const struct sr_dev_inst *sdi)
 742 {
 743         struct dev_context *devc;
 744         struct sr_trigger *trigger;
 745         struct sr_trigger_stage *stage;
 746         struct sr_trigger_match *match;
 747         const GSList *l, *m;
 748         uint64_t channel_index;
 749
 750         devc = sdi->priv;
 751
 752         devc->trigger_mask = 0;
 753         devc->trigger_values = 0;
 754         devc->trigger_edge_mask = 0;
 755
 756         if (!(trigger = sr_session_trigger_get(sdi->session)))
 757                 return SR_OK;
 758
 759         if (g_slist_length(trigger->stages) > 1) {
 760                 sr_err("This device only supports 1 trigger stage.");
 761                 return SR_ERR;
 762         }
 763
 764         for (l = trigger->stages; l; l = l->next) {
 765                 stage = l->data;
 766                 for (m = stage->matches; m; m = m->next) {
 767                         match = m->data;
 768                         if (!match->channel->enabled)
 769                                 /* Ignore disabled channels with a trigger. */
 770                                 continue;
 771                         channel_index = 1 << match->channel->index;
 772                         devc->trigger_mask |= channel_index;
 773                         switch (match->match) {
 774                         case SR_TRIGGER_ONE:
 775                                 devc->trigger_values |= channel_index;
 776                                 break;
 777                         case SR_TRIGGER_RISING:
 778                                 devc->trigger_values |= channel_index;
 779                                 /* Fall through for edge mask. */
 780                         case SR_TRIGGER_FALLING:
 781                                 devc->trigger_edge_mask |= channel_index;
 782                                 break;
 783                         }
 784                 }
 785         }
 786
 787         return SR_OK;
 788 }
 789
 790 /* Select the LWLA clock configuration.  If the clock source changed from
 791  * the previous setting, this will download a new bitstream to the FPGA.
 792  */
 793 SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi)
 794 {
 795         struct dev_context *devc;
 796         int ret;
 797         enum clock_config choice;
 798
 799         devc = sdi->priv;
 800
 801         if (sdi->status == SR_ST_INACTIVE)
 802                 choice = CONF_CLOCK_NONE;
 803         else if (devc->cfg_clock_source == CLOCK_INTERNAL)
 804                 choice = CONF_CLOCK_INT;
 805         else if (devc->cfg_clock_edge == EDGE_POSITIVE)
 806                 choice = CONF_CLOCK_EXT_RISE;
 807         else
 808                 choice = CONF_CLOCK_EXT_FALL;
 809
 810         if (choice != devc->cur_clock_config) {
 811                 devc->cur_clock_config = CONF_CLOCK_NONE;
 812                 ret = lwla_send_bitstream(sdi->conn, bitstream_map[choice]);
 813                 if (ret == SR_OK)
 814                         devc->cur_clock_config = choice;
 815                 return ret;
 816         }
 817         return SR_OK;
 818 }
 819
 820 /* Configure the LWLA in preparation for an acquisition session.
 821  */
 822 SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi)
 823 {
 824         struct dev_context *devc;
 825         struct sr_usb_dev_inst *usb;
 826         struct acquisition_state *acq;
 827         struct regval_pair regvals[7];
 828         int ret;
 829
 830         devc = sdi->priv;
 831         usb  = sdi->conn;
 832         acq  = devc->acquisition;
 833
 834         if (devc->limit_msec > 0) {
 835                 acq->duration_max = devc->limit_msec;
 836                 sr_info("Acquisition time limit %" PRIu64 " ms.",
 837                         devc->limit_msec);
 838         } else
 839                 acq->duration_max = MAX_LIMIT_MSEC;
 840
 841         if (devc->limit_samples > 0) {
 842                 acq->samples_max = devc->limit_samples;
 843                 sr_info("Acquisition sample count limit %" PRIu64 ".",
 844                         devc->limit_samples);
 845         } else
 846                 acq->samples_max = MAX_LIMIT_SAMPLES;
 847
 848         if (devc->cfg_clock_source == CLOCK_INTERNAL) {
 849                 sr_info("Internal clock, samplerate %" PRIu64 ".",
 850                         devc->samplerate);
 851                 if (devc->samplerate == 0)
 852                         return SR_ERR_BUG;
 853                 /* At 125 MHz, the clock divider is bypassed. */
 854                 acq->bypass_clockdiv = (devc->samplerate > SR_MHZ(100));
 855
 856                 /* If only one of the limits is set, derive the other one. */
 857                 if (devc->limit_msec == 0 && devc->limit_samples > 0)
 858                         acq->duration_max = devc->limit_samples
 859                                         * 1000 / devc->samplerate + 1;
 860                 else if (devc->limit_samples == 0 && devc->limit_msec > 0)
 861                         acq->samples_max = devc->limit_msec
 862                                         * devc->samplerate / 1000;
 863         } else {
 864                 acq->bypass_clockdiv = TRUE;
 865
 866                 if (devc->cfg_clock_edge == EDGE_NEGATIVE)
 867                         sr_info("External clock, falling edge.");
 868                 else
 869                         sr_info("External clock, rising edge.");
 870         }
 871
 872         regvals[0].reg = REG_MEM_CTRL2;
 873         regvals[0].val = 2;
 874
 875         regvals[1].reg = REG_MEM_CTRL2;
 876         regvals[1].val = 1;
 877
 878         regvals[2].reg = REG_CMD_CTRL2;
 879         regvals[2].val = 10;
 880
 881         regvals[3].reg = REG_CMD_CTRL3;
 882         regvals[3].val = 0x74;
 883
 884         regvals[4].reg = REG_CMD_CTRL4;
 885         regvals[4].val = 0;
 886
 887         regvals[5].reg = REG_CMD_CTRL1;
 888         regvals[5].val = 0;
 889
 890         regvals[6].reg = REG_DIV_BYPASS;
 891         regvals[6].val = acq->bypass_clockdiv;
 892
 893         ret = lwla_write_regs(usb, regvals, G_N_ELEMENTS(regvals));
 894         if (ret != SR_OK)
 895                 return ret;
 896
 897         return capture_setup(sdi);
 898 }
 899
 900 /* Start the capture operation on the LWLA device.  Beginning with this
 901  * function, all USB transfers will be asynchronous until the end of the
 902  * acquisition session.
 903  */
 904 SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi)
 905 {
 906         struct dev_context *devc;
 907         struct sr_usb_dev_inst *usb;
 908         struct acquisition_state *acq;
 909         struct regval_pair *regvals;
 910
 911         devc = sdi->priv;
 912         usb  = sdi->conn;
 913         acq  = devc->acquisition;
 914
 915         acq->duration_now  = 0;
 916         acq->mem_addr_fill = 0;
 917         acq->capture_flags = 0;
 918
 919         libusb_fill_bulk_transfer(acq->xfer_out, usb->devhdl, EP_COMMAND,
 920                                   (unsigned char *)acq->xfer_buf_out, 0,
 921                                   &receive_transfer_out,
 922                                   (struct sr_dev_inst *)sdi, USB_TIMEOUT);
 923
 924         libusb_fill_bulk_transfer(acq->xfer_in, usb->devhdl, EP_REPLY,
 925                                   (unsigned char *)acq->xfer_buf_in,
 926                                   sizeof acq->xfer_buf_in,
 927                                   &receive_transfer_in,
 928                                   (struct sr_dev_inst *)sdi, USB_TIMEOUT);
 929
 930         regvals = devc->reg_write_seq;
 931
 932         regvals[0].reg = REG_CMD_CTRL2;
 933         regvals[0].val = 10;
 934
 935         regvals[1].reg = REG_CMD_CTRL3;
 936         regvals[1].val = 1;
 937
 938         regvals[2].reg = REG_CMD_CTRL4;
 939         regvals[2].val = 0;
 940
 941         regvals[3].reg = REG_CMD_CTRL1;
 942         regvals[3].val = 0;
 943
 944         devc->reg_write_pos = 0;
 945         devc->reg_write_len = 4;
 946
 947         devc->state = STATE_START_CAPTURE;
 948
 949         return issue_next_write_reg(sdi);
 950 }
 951
 952 /* Allocate an acquisition state object.
 953  */
 954 SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void)
 955 {
 956         struct acquisition_state *acq;
 957
 958         acq = g_try_new0(struct acquisition_state, 1);
 959         if (!acq) {
 960                 sr_err("Acquisition state malloc failed.");
 961                 return NULL;
 962         }
 963
 964         acq->xfer_in = libusb_alloc_transfer(0);
 965         if (!acq->xfer_in) {
 966                 sr_err("Transfer malloc failed.");
 967                 g_free(acq);
 968                 return NULL;
 969         }
 970
 971         acq->xfer_out = libusb_alloc_transfer(0);
 972         if (!acq->xfer_out) {
 973                 sr_err("Transfer malloc failed.");
 974                 libusb_free_transfer(acq->xfer_in);
 975                 g_free(acq);
 976                 return NULL;
 977         }
 978
 979         return acq;
 980 }
 981
 982 /* Deallocate an acquisition state object.
 983  */
 984 SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq)
 985 {
 986         if (acq) {
 987                 libusb_free_transfer(acq->xfer_out);
 988                 libusb_free_transfer(acq->xfer_in);
 989                 g_free(acq);
 990         }
 991 }
 992
 993 /* USB I/O source callback.
 994  */
 995 SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data)
 996 {
 997         struct sr_dev_inst *sdi;
 998         struct dev_context *devc;
 999         struct drv_context *drvc;
1000         struct timeval tv;
1001         int ret;
1002
1003         (void)fd;
1004
1005         sdi  = cb_data;
1006         devc = sdi->priv;
1007         drvc = sdi->driver->priv;
1008
1009         if (!devc || !drvc)
1010                 return FALSE;
1011
1012         /* No timeout: return immediately. */
1013         tv.tv_sec  = 0;
1014         tv.tv_usec = 0;
1015
1016         ret = libusb_handle_events_timeout_completed(drvc->sr_ctx->libusb_ctx,
1017                                                      &tv, NULL);
1018         if (ret != 0)
1019                 sr_err("Event handling failed: %s.", libusb_error_name(ret));
1020
1021         /* If no event flags are set the timeout must have expired. */
1022         if (revents == 0 && devc->state == STATE_STATUS_WAIT) {
1023                 if (sdi->status == SR_ST_STOPPING)
1024                         issue_stop_capture(sdi);
1025                 else
1026                         request_capture_status(sdi);
1027         }
1028
1029         /* Check if an error occurred on a transfer. */
1030         if (devc->transfer_error)
1031                 end_acquisition(sdi);
1032
1033         return TRUE;
1034 }