From: Vesa-Pekka Palmu <redacted>
Date: Mon, 26 Dec 2022 17:18:36 +0000 (+0200)
Subject: adf435x: Move decoder logic to SPI transfers
X-Git-Url: https://sigrok.org/gitweb/?a=commitdiff_plain;ds=sidebyside;h=adb8233a0bf30b1d9ee9176e1caa5dc8ae1830dd;hp=f534ce442c271c13af5d216e16f56322dc586822;p=libsigrokdecode.git

adf435x: Move decoder logic to SPI transfers

The previous implementation of the ADF435x decoder assumed knowledge of
internal details which are the SPI transport layer's responsibility. And
encoded an inappropriate chip select polarity in the process (falling
CS edge). The datasheet specifies that previously clocked in data bits
get latched on rising LE edges.

Not all setups were affected, that's why the issue went unnoticed before.

Use the lower layer's TRANSFER annotation to process the completion of
an ADF435x register access, after BITS annotations made the location of
individual bits available. The LE (CS) signal's polarity remains a detail
of the SPI decoding layer, and must be configured there. The SPI decoder's
default matches the ADF435x chip's expectation.

This fixes bug #1814.

Reported-by:  Martin Homuth-Rosemann <redacted>
---

diff --git a/decoders/adf435x/pd.py b/decoders/adf435x/pd.py
index e3d51a9..9ba88ca 100644
--- a/decoders/adf435x/pd.py
+++ b/decoders/adf435x/pd.py
@@ -113,7 +113,6 @@ class Decoder(srd.Decoder):
 
     def reset(self):
         self.bits = []
-        self.packet_start = 0
 
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
@@ -129,28 +128,22 @@ class Decoder(srd.Decoder):
         return val
 
     def decode(self, ss, es, data):
-
         ptype, _, _ = data
 
-        if ptype == 'CS-CHANGE':
-            _, cs_before, cs_after = data
-            if cs_before == 1:
-                if len(self.bits) == 32:
-                    reg_value, reg_pos = self.decode_bits(0, 3)
-                    self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
-                        ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
-                         '[%d]' % reg_value]])
-                    if reg_value < len(regs):
-                        field_descs = regs[reg_value]
-                        for field_desc in field_descs:
-                            field = self.decode_field(*field_desc)
-                else:
-                    error = "Frame error: Wrong number of bits: got %d expected 32" % len(self.bits)
-                    self.put(self.packet_start, es, self.out_ann, [ANN_WARN, [error, 'Frame error']])
-                self.bits = []
+        if ptype == 'TRANSFER':
+            if len(self.bits) == 32:
+                reg_value, reg_pos = self.decode_bits(0, 3)
+                self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
+                    ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
+                     '[%d]' % reg_value]])
+                if reg_value < len(regs):
+                    field_descs = regs[reg_value]
+                    for field_desc in field_descs:
+                        field = self.decode_field(*field_desc)
             else:
-                # Start of a new register write packet
-                self.packet_start = ss
+                error = "Frame error: Wrong number of bits: got %d expected 32" % len(self.bits)
+                self.put(ss, es, self.out_ann, [ANN_WARN, [error, 'Frame error']])
+            self.bits = []
 
         if ptype == 'BITS':
             _, mosi_bits, miso_bits = data