From: Uwe Hermann <redacted>
Date: Tue, 14 Feb 2017 21:49:37 +0000 (+0100)
Subject: adf435x: Add an initial test-case.
X-Git-Url: https://sigrok.org/gitweb/?a=commitdiff_plain;ds=sidebyside;h=6edd0d21243cc9ebddcdac258d3f0e7665324e38;hp=dbe11510e398f750f0fe65ae87dcd6035f670125;p=sigrok-test.git

adf435x: Add an initial test-case.
---

diff --git a/decoder/test/adf435x/set-4000mhz.output b/decoder/test/adf435x/set-4000mhz.output
new file mode 100644
index 0000000..53e26a5
--- /dev/null
+++ b/decoder/test/adf435x/set-4000mhz.output
@@ -0,0 +1,42 @@
+399842-400012 adf435x: register: "Register: 5" "Reg: 5" "[5]"
+398669-398782 adf435x: register: "LD Pin Mode: High"
+511405-511572 adf435x: register: "Register: 4" "Reg: 4" "[4]"
+511291-511405 adf435x: register: "Output Power: +5dBm"
+511235-511291 adf435x: register: "Output Enable: Enabled"
+511121-511235 adf435x: register: "AUX Output Power: +5dBm"
+511065-511121 adf435x: register: "AUX Output Select: Divided Output"
+511009-511065 adf435x: register: "AUX Output Enable: Disabled"
+510953-511009 adf435x: register: "MTLD: Disabled"
+510898-510953 adf435x: register: "VCO Power-Down: VCO Powered Up"
+510450-510898 adf435x: register: "Band Select Clock Divider: 200"
+510282-510450 adf435x: register: "RF Divider Select: ÷1"
+510227-510282 adf435x: register: "Feedback Select: Fundamental"
+723589-723758 adf435x: register: "Register: 3" "Reg: 3" "[3]"
+722917-723589 adf435x: register: "Clock Divider: 150"
+722806-722917 adf435x: register: "Clock Divider Mode: Clock Divider Off"
+722694-722750 adf435x: register: "CSR Enable: Disabled"
+722527-722583 adf435x: register: "Charge Cancellation: Disabled"
+722471-722527 adf435x: register: "ABP: 6ns (FRAC-N)"
+722416-722471 adf435x: register: "Band Select Clock Mode: Low"
+1018442-1018609 adf435x: register: "Register: 2" "Reg: 2" "[2]"
+1018386-1018442 adf435x: register: "Counter Reset: Disabled"
+1018331-1018386 adf435x: register: "Charge Pump Three-State: Disabled"
+1018275-1018331 adf435x: register: "Power-Down: Disabled"
+1018219-1018275 adf435x: register: "PD Polarity: Positive"
+1018163-1018219 adf435x: register: "LDP: 10ns"
+1018107-1018163 adf435x: register: "LDF: FRAC-N"
+1017881-1018107 adf435x: register: "Charge Pump Current Setting: 2.50mA @ 5.1kΩ"
+1017826-1017881 adf435x: register: "Double Buffer: Disabled"
+1017268-1017826 adf435x: register: "R Counter: 1"
+1017212-1017267 adf435x: register: "RDIV2: Disabled"
+1017157-1017212 adf435x: register: "Reference Doubler: Disabled"
+1016990-1017157 adf435x: register: "MUXOUT: Three-State Output"
+1016878-1016990 adf435x: register: "Low Noise and Low Spur Modes: Low Noise Mode"
+1304000-1304170 adf435x: register: "Register: 1" "Reg: 1" "[1]"
+1303331-1304000 adf435x: register: "MOD: 2"
+1302662-1303331 adf435x: register: "Phase: 1"
+1302607-1302662 adf435x: register: "Prescalar: 8/9"
+1302550-1302607 adf435x: register: "Phase Adjust: Off"
+1507574-1507741 adf435x: register: "Register: 0" "Reg: 0" "[0]"
+1506905-1507574 adf435x: register: "FRAC: 0"
+1506013-1506905 adf435x: register: "INT: 160"
diff --git a/decoder/test/adf435x/test.conf b/decoder/test/adf435x/test.conf
new file mode 100644
index 0000000..707d925
--- /dev/null
+++ b/decoder/test/adf435x/test.conf
@@ -0,0 +1,6 @@
+test set-4000mhz
+	protocol-decoder spi channel cs=0 channel mosi=1 channel clk=2
+	protocol-decoder adf435x
+	stack spi adf435x
+	input spi/adf4351/set-4000mhz.sr
+	output adf435x annotation match set-4000mhz.output