X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=uart%2Fhello_world%2FREADME;h=57365d63825e30abfdc19362d0c8c1da03312535;hb=d53db98d513dc13dbc75c1d1ca416b2b33e66ae9;hp=5bd2f89ba2ab51e9d99b4a13e45c440b67bb23ac;hpb=f793c6d26e576d436b93b3414a00b9d2fcdcdaba;p=sigrok-dumps.git

diff --git a/uart/hello_world/README b/uart/hello_world/README
index 5bd2f89..57365d6 100644
--- a/uart/hello_world/README
+++ b/uart/hello_world/README
@@ -19,14 +19,11 @@ http://olimex.com/dev/stm32-h103.html
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing is a ChronoVu LA8 at a sample rate
-of 5MHz (for baud rates 921600 - 230400), 1MHz (for 115200 - 19200),
-and 625kHz (for baud rates 9600 - 1200).
-
-The ChronoVu LA8 probes were connected to the UART like this:
+The logic analyzer used was a ChronoVu LA8 at a sample rate of 5MHz (for baud
+rates 921600 - 230400), 1MHz (115200 - 19200), and 625kHz (9600 - 1200):
 
   Probe       UART
-  -------------------
+  ----------------
   0 (green)   TX