X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=test%2Fdata%2Flogicsnapshot.cpp;h=8be915f02544bc6a8f10ade5f770438150c95357;hb=819f4c25391a9c74d3d2f528d462142d5c4aad4d;hp=1c536791b7a3f746a9ae621cc39c62553b21fae7;hpb=1b1ec774978b65209ce2b454cbf81da499b797d2;p=pulseview.git diff --git a/test/data/logicsnapshot.cpp b/test/data/logicsnapshot.cpp index 1c536791..8be915f0 100644 --- a/test/data/logicsnapshot.cpp +++ b/test/data/logicsnapshot.cpp @@ -27,9 +27,8 @@ #include "../../pv/data/logicsnapshot.h" -using namespace std; - using pv::data::LogicSnapshot; +using std::vector; BOOST_AUTO_TEST_SUITE(LogicSnapshotTest) @@ -348,7 +347,7 @@ BOOST_AUTO_TEST_CASE(LongPulses) //----- Create a LogicSnapshot -----// sr_datafeed_logic logic; logic.unitsize = 8; - logic.length = Length; + logic.length = Length * 8; logic.data = (uint64_t*)new uint64_t[Length]; uint64_t *p = (uint64_t*)logic.data; @@ -471,5 +470,66 @@ BOOST_AUTO_TEST_CASE(LisaMUsbHid) BOOST_CHECK_EQUAL(edges[edges.size() - 2].second, false); } +/* + * This test checks the rendering of wide data (more than 8 probes) + * Probe signals are either all-high, or all-low, but are interleaved such that + * they would toggle during every sample if treated like 8 probes. + * The packet contains a large number of samples, so the mipmap generation kicks + * in. + * + * The signals should not toggle (have exactly two edges: the start and end) + */ +BOOST_AUTO_TEST_CASE(WideData) +{ + const int Length = 512<<10; + uint16_t *data = new uint16_t[Length]; + + sr_datafeed_logic logic; + logic.unitsize = sizeof(data[0]); + logic.length = Length * sizeof(data[0]); + logic.data = data; + + for (int i = 0; i < Length; i++) + data[i] = 0x0FF0; + + LogicSnapshot s(logic); + + vector edges; + + edges.clear(); + s.get_subsampled_edges(edges, 0, Length-1, 1, 0); + BOOST_CHECK_EQUAL(edges.size(), 2); + + edges.clear(); + s.get_subsampled_edges(edges, 0, Length-1, 1, 8); + BOOST_CHECK_EQUAL(edges.size(), 2); + + // Cleanup + delete [] data; +} + +/* + * This test is a replica of sixteen.sr attached to Bug #33. + */ +BOOST_AUTO_TEST_CASE(Sixteen) +{ + const int Length = 8; + uint16_t data[Length]; + + sr_datafeed_logic logic; + logic.unitsize = sizeof(data[0]); + logic.length = Length * sizeof(data[0]); + logic.data = data; + + for (int i = 0; i < Length; i++) + data[i] = 0xFFFE; + + LogicSnapshot s(logic); + + vector edges; + s.get_subsampled_edges(edges, 0, 2, 0.0004, 1); + + BOOST_CHECK_EQUAL(edges.size(), 2); +} BOOST_AUTO_TEST_SUITE_END()