X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fsysclk-lwla%2Flwla1016.c;h=b280b7a2790d26708abe1b8ffa17c976c1380431;hb=e3abd15d08bcd97b9e94e5775fb35d44a1d43397;hp=33fd7e28988fda27f3eff7cd22e48e23d45faa27;hpb=786485772ffd28dfb1ca7375ca64118ccd7af25c;p=libsigrok.git

diff --git a/src/hardware/sysclk-lwla/lwla1016.c b/src/hardware/sysclk-lwla/lwla1016.c
index 33fd7e28..b280b7a2 100644
--- a/src/hardware/sysclk-lwla/lwla1016.c
+++ b/src/hardware/sysclk-lwla/lwla1016.c
@@ -142,9 +142,7 @@ static void read_response_rle(struct acquisition_state *acq)
 {
 	uint32_t *in_p;
 	uint16_t *out_p;
-	unsigned int words_left;
-	unsigned int max_samples, run_samples;
-	unsigned int wi, ri;
+	unsigned int words_left, max_samples, run_samples, wi, ri;
 	uint32_t word;
 	uint16_t sample;
 
@@ -170,14 +168,15 @@ static void read_response_rle(struct acquisition_state *acq)
 		acq->samples_done += run_samples;
 
 		if (run_samples == max_samples)
-			break; /* packet full or sample limit reached */
+			break; /* Packet full or sample limit reached. */
 		if (wi >= words_left)
-			break; /* done with current transfer */
+			break; /* Done with current transfer. */
 
 		word = GUINT32_FROM_LE(in_p[wi]);
 		acq->sample = word >> 16;
 		acq->run_len = (word & 0xFFFF) + 1;
 	}
+
 	acq->in_index += wi;
 	acq->mem_addr_done += wi;
 }
@@ -197,8 +196,7 @@ static int test_read_memory(const struct sr_dev_inst *sdi,
 	struct dev_context *devc;
 	struct sr_usb_dev_inst *usb;
 	unsigned int i;
-	int xfer_len;
-	int ret;
+	int xfer_len, ret;
 	uint16_t command[5];
 	unsigned char reply[512];
 
@@ -231,6 +229,7 @@ static int test_read_memory(const struct sr_dev_inst *sdi,
 		       xfer_len);
 		return SR_ERR;
 	}
+
 	return SR_OK;
 }
 
@@ -240,19 +239,18 @@ static int apply_fpga_config(const struct sr_dev_inst *sdi)
 {
 	struct dev_context *devc;
 	struct drv_context *drvc;
-	int config;
-	int ret;
+	int config, ret;
 
 	devc = sdi->priv;
 	drvc = sdi->driver->context;
 
 	if (sdi->status == SR_ST_INACTIVE)
-		return SR_OK; /* the LWLA1016 has no off state */
+		return SR_OK; /* The LWLA1016 has no off state. */
 
 	config = (devc->cfg_rle) ? FPGA_100_TS : FPGA_100;
 
 	if (config == devc->active_fpga_config)
-		return SR_OK; /* no change */
+		return SR_OK; /* No change. */
 
 	ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
 				  bitstream_map[config]);
@@ -271,12 +269,9 @@ static int device_init_check(const struct sr_dev_inst *sdi)
 	};
 	uint32_t value;
 	int ret;
-
 	const unsigned int test_count = 24;
 
-	ret = lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
-	if (ret != SR_OK)
-		return ret;
+	lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
 
 	/* Ignore the value returned by the first read. */
 	ret = lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
@@ -295,6 +290,7 @@ static int device_init_check(const struct sr_dev_inst *sdi)
 	ret = test_read_memory(sdi, 0, test_count);
 	if (ret != SR_OK)
 		return ret;
+
 	/*
 	 * Issue another read request or the device will stall, for whatever
 	 * reason. This happens both with and without the short transfer quirk.
@@ -304,51 +300,46 @@ static int device_init_check(const struct sr_dev_inst *sdi)
 
 static int setup_acquisition(const struct sr_dev_inst *sdi)
 {
+	static const struct regval capture_init[] = {
+		{REG_CAP_CTRL,  0},
+		{REG_DURATION,  0},
+		{REG_MEM_CTRL,  MEM_CTRL_RESET},
+		{REG_MEM_CTRL,  0},
+		{REG_MEM_CTRL,  MEM_CTRL_WRITE},
+		{REG_CAP_CTRL,  CAP_CTRL_FIFO32_FULL | CAP_CTRL_FIFO64_FULL},
+		{REG_CAP_CTRL,  CAP_CTRL_FIFO_EMPTY},
+		{REG_CAP_CTRL,  0},
+		{REG_CAP_COUNT, MEMORY_DEPTH - 5},
+	};
 	struct dev_context *devc;
 	struct sr_usb_dev_inst *usb;
-	struct acquisition_state *acq;
-	uint32_t divider_count;
+	uint32_t divider_count, trigger_setup;
 	int ret;
 
 	devc = sdi->priv;
 	usb  = sdi->conn;
-	acq  = devc->acquisition;
 
-	acq->reg_seq_pos = 0;
-	acq->reg_seq_len = 0;
-
-	lwla_queue_regval(acq, REG_CHAN_MASK, devc->channel_mask);
+	ret = lwla_write_reg(usb, REG_CHAN_MASK, devc->channel_mask);
+	if (ret != SR_OK)
+		return ret;
 
 	if (devc->samplerate > 0 && devc->samplerate < SR_MHZ(100))
 		divider_count = SR_MHZ(100) / devc->samplerate - 1;
 	else
 		divider_count = 0;
 
-	lwla_queue_regval(acq, REG_DIV_COUNT, divider_count);
-
-	lwla_queue_regval(acq, REG_CAP_CTRL, 0);
-	lwla_queue_regval(acq, REG_DURATION, 0);
-
-	lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_RESET);
-	lwla_queue_regval(acq, REG_MEM_CTRL, 0);
-	lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_WRITE);
-
-	lwla_queue_regval(acq, REG_CAP_CTRL,
-		CAP_CTRL_FIFO32_FULL | CAP_CTRL_FIFO64_FULL);
-
-	lwla_queue_regval(acq, REG_CAP_CTRL, CAP_CTRL_FIFO_EMPTY);
-	lwla_queue_regval(acq, REG_CAP_CTRL, 0);
-
-	lwla_queue_regval(acq, REG_CAP_COUNT, MEMORY_DEPTH - 5);
+	ret = lwla_write_reg(usb, REG_DIV_COUNT, divider_count);
+	if (ret != SR_OK)
+		return ret;
 
-	lwla_queue_regval(acq, REG_TRG_SEL,
-		((devc->trigger_edge_mask & 0xFFFF) << 16)
-		| (devc->trigger_values & 0xFFFF));
+	ret = lwla_write_regs(usb, capture_init, ARRAY_SIZE(capture_init));
+	if (ret != SR_OK)
+		return ret;
 
-	ret = lwla_write_regs(usb, acq->reg_sequence, acq->reg_seq_len);
-	acq->reg_seq_len = 0;
+	trigger_setup = ((devc->trigger_edge_mask & 0xFFFF) << 16)
+			| (devc->trigger_values & 0xFFFF);
 
-	return ret;
+	return lwla_write_reg(usb, REG_TRG_SEL, trigger_setup);
 }
 
 static int prepare_request(const struct sr_dev_inst *sdi)