X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fsysclk-lwla%2Flwla1016.c;h=1c0391f574db34bfcb6fc838bbf37bbb5f2da46e;hb=deb7615262ac4f9cc0750a08351afa7cbf9c34d5;hp=59557efd860822eb5ac5787c1bdf55f188018f2c;hpb=7ed808179f5542c903a476266c4b175a6f2a18a7;p=libsigrok.git diff --git a/src/hardware/sysclk-lwla/lwla1016.c b/src/hardware/sysclk-lwla/lwla1016.c index 59557efd..1c0391f5 100644 --- a/src/hardware/sysclk-lwla/lwla1016.c +++ b/src/hardware/sysclk-lwla/lwla1016.c @@ -21,28 +21,22 @@ #include "lwla.h" #include "protocol.h" -/* Number of logic channels. - */ +/* Number of logic channels. */ #define NUM_CHANNELS 16 -/* Unit size for the sigrok logic datafeed. - */ +/* Unit size for the sigrok logic datafeed. */ #define UNIT_SIZE ((NUM_CHANNELS + 7) / 8) -/* Size of the acquisition buffer in device memory units. - */ +/* Size of the acquisition buffer in device memory units. */ #define MEMORY_DEPTH (256 * 1024) /* 256k x 32 bit */ -/* Capture memory read start address. - */ -#define READ_START_ADDR 2 +/* Capture memory read start address. */ +#define READ_START_ADDR 2 -/* Number of device memory units (32 bit) to read at a time. - */ -#define READ_CHUNK_LEN32 250 +/* Number of device memory units (32 bit) to read at a time. */ +#define READ_CHUNK_LEN 250 -/** LWLA1016 register addresses. - */ +/** LWLA1016 register addresses. */ enum reg_addr { REG_CHAN_MASK = 0x1000, /* bit mask of enabled channels */ @@ -64,15 +58,13 @@ enum reg_addr { REG_DIV_COUNT = 0x10BC, /* write */ }; -/** Flag bits for REG_MEM_CTRL. - */ +/** Flag bits for REG_MEM_CTRL. */ enum mem_ctrl_flag { MEM_CTRL_RESET = 1 << 0, MEM_CTRL_WRITE = 1 << 1, }; -/** Flag bits for REG_CAP_CTRL. - */ +/** Flag bits for REG_CAP_CTRL. */ enum cap_ctrl_flag { CAP_CTRL_FIFO32_FULL = 1 << 0, /* "fifo32_ful" bit */ CAP_CTRL_FIFO64_FULL = 1 << 1, /* "fifo64_ful" bit */ @@ -83,22 +75,19 @@ enum cap_ctrl_flag { CAP_CTRL_CNTR_NOT_ENDR = 1 << 6, /* "cntr_not_endr" bit */ }; -/* Available FPGA configurations. - */ +/* Available FPGA configurations. */ enum fpga_config { FPGA_100 = 0, /* 100 MS/s, no compression */ FPGA_100_TS, /* 100 MS/s, timing-state mode */ }; -/* FPGA bitstream resource filenames. - */ +/* FPGA bitstream resource filenames. */ static const char bitstream_map[][32] = { [FPGA_100] = "sysclk-lwla1016-100.rbf", [FPGA_100_TS] = "sysclk-lwla1016-100-ts.rbf", }; -/* Demangle incoming sample data from the transfer buffer. - */ +/* Demangle incoming sample data from the transfer buffer. */ static void read_response(struct acquisition_state *acq) { uint32_t *in_p, *out_p; @@ -121,7 +110,7 @@ static void read_response(struct acquisition_state *acq) * alignment is guaranteed. */ out_p = (uint32_t *)&acq->out_packet[acq->out_index * UNIT_SIZE]; - in_p = &acq->xfer_buf_in[acq->in_index]; + in_p = &acq->xfer_buf_in[acq->in_index]; /* * Transfer two samples at a time, taking care to swap the 16-bit * halves of each input word but keeping the samples themselves in @@ -136,15 +125,12 @@ static void read_response(struct acquisition_state *acq) acq->samples_done += run_samples; } -/* Demangle and decompress incoming sample data from the transfer buffer. - */ +/* Demangle and decompress incoming sample data from the transfer buffer. */ static void read_response_rle(struct acquisition_state *acq) { uint32_t *in_p; uint16_t *out_p; - unsigned int words_left; - unsigned int max_samples, run_samples; - unsigned int wi, ri; + unsigned int words_left, max_samples, run_samples, wi, ri; uint32_t word; uint16_t sample; @@ -170,37 +156,88 @@ static void read_response_rle(struct acquisition_state *acq) acq->samples_done += run_samples; if (run_samples == max_samples) - break; /* packet full or sample limit reached */ + break; /* Packet full or sample limit reached. */ if (wi >= words_left) - break; /* done with current transfer */ + break; /* Done with current transfer. */ word = GUINT32_FROM_LE(in_p[wi]); acq->sample = word >> 16; acq->run_len = (word & 0xFFFF) + 1; } + acq->in_index += wi; acq->mem_addr_done += wi; } -/* Select and transfer FPGA bitstream for the current configuration. +/* Check whether we can receive responses of more than 64 bytes. + * The FX2 firmware of the LWLA1016 has a bug in the reset logic which + * sometimes causes the response endpoint to be limited to transfers of + * 64 bytes at a time, instead of the expected 2*512 bytes. The problem + * can be worked around by never requesting more than 64 bytes. + * This quirk manifests itself only under certain conditions, and some + * users seem to see it more frequently than others. Detect it here in + * order to avoid paying the penalty unnecessarily. */ +static int test_read_memory(const struct sr_dev_inst *sdi, + unsigned int start, unsigned int count) +{ + struct dev_context *devc; + struct sr_usb_dev_inst *usb; + unsigned int i; + int xfer_len, ret; + uint16_t command[5]; + unsigned char reply[512]; + + devc = sdi->priv; + usb = sdi->conn; + + command[0] = LWLA_WORD(CMD_READ_MEM32); + command[1] = LWLA_WORD_0(start); + command[2] = LWLA_WORD_1(start); + command[3] = LWLA_WORD_0(count); + command[4] = LWLA_WORD_1(count); + + ret = lwla_send_command(usb, ARRAY_AND_SIZE(command)); + if (ret != SR_OK) + return ret; + + ret = lwla_receive_reply(usb, reply, sizeof(reply), &xfer_len); + if (ret != SR_OK) + return ret; + + devc->short_transfer_quirk = (xfer_len == 64); + + for (i = xfer_len; i < 4 * count && xfer_len == 64; i += xfer_len) { + ret = lwla_receive_reply(usb, reply, sizeof(reply), &xfer_len); + if (ret != SR_OK) + return ret; + } + if (i != 4 * count) { + sr_err("Invalid read response of unexpected length %d.", + xfer_len); + return SR_ERR; + } + + return SR_OK; +} + +/* Select and transfer FPGA bitstream for the current configuration. */ static int apply_fpga_config(const struct sr_dev_inst *sdi) { struct dev_context *devc; struct drv_context *drvc; - int config; - int ret; + int config, ret; devc = sdi->priv; drvc = sdi->driver->context; if (sdi->status == SR_ST_INACTIVE) - return SR_OK; /* the LWLA1016 has no off state */ + return SR_OK; /* The LWLA1016 has no off state. */ config = (devc->cfg_rle) ? FPGA_100_TS : FPGA_100; if (config == devc->active_fpga_config) - return SR_OK; /* no change */ + return SR_OK; /* No change. */ ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn, bitstream_map[config]); @@ -209,16 +246,18 @@ static int apply_fpga_config(const struct sr_dev_inst *sdi) return ret; } -/* Perform initialization self test. - */ +/* Perform initialization self test. */ static int device_init_check(const struct sr_dev_inst *sdi) { + static const struct regval mem_reset[] = { + {REG_MEM_CTRL, MEM_CTRL_RESET}, + {REG_MEM_CTRL, 0}, + }; uint32_t value; int ret; + const unsigned int test_count = 24; - ret = lwla_read_reg(sdi->conn, REG_TEST_ID, &value); - if (ret != SR_OK) - return ret; + lwla_read_reg(sdi->conn, REG_TEST_ID, &value); /* Ignore the value returned by the first read. */ ret = lwla_read_reg(sdi->conn, REG_TEST_ID, &value); @@ -229,66 +268,74 @@ static int device_init_check(const struct sr_dev_inst *sdi) sr_err("Received invalid test word 0x%08X.", value); return SR_ERR; } - return SR_OK; + + ret = lwla_write_regs(sdi->conn, ARRAY_AND_SIZE(mem_reset)); + if (ret != SR_OK) + return ret; + + ret = test_read_memory(sdi, 0, test_count); + if (ret != SR_OK) + return ret; + + /* + * Issue another read request or the device will stall, for whatever + * reason. This happens both with and without the short transfer quirk. + */ + return test_read_memory(sdi, test_count, test_count); } static int setup_acquisition(const struct sr_dev_inst *sdi) { + static const struct regval capture_init[] = { + {REG_CAP_CTRL, 0}, + {REG_DURATION, 0}, + {REG_MEM_CTRL, MEM_CTRL_RESET}, + {REG_MEM_CTRL, 0}, + {REG_MEM_CTRL, MEM_CTRL_WRITE}, + {REG_CAP_CTRL, CAP_CTRL_FIFO32_FULL | CAP_CTRL_FIFO64_FULL}, + {REG_CAP_CTRL, CAP_CTRL_FIFO_EMPTY}, + {REG_CAP_CTRL, 0}, + {REG_CAP_COUNT, MEMORY_DEPTH - 5}, + }; struct dev_context *devc; struct sr_usb_dev_inst *usb; - struct acquisition_state *acq; - uint32_t divider_count; + uint32_t divider_count, trigger_setup; int ret; devc = sdi->priv; - usb = sdi->conn; - acq = devc->acquisition; + usb = sdi->conn; - acq->reg_seq_pos = 0; - acq->reg_seq_len = 0; - - lwla_queue_regval(acq, REG_CHAN_MASK, devc->channel_mask); + ret = lwla_write_reg(usb, REG_CHAN_MASK, devc->channel_mask); + if (ret != SR_OK) + return ret; if (devc->samplerate > 0 && devc->samplerate < SR_MHZ(100)) divider_count = SR_MHZ(100) / devc->samplerate - 1; else divider_count = 0; - lwla_queue_regval(acq, REG_DIV_COUNT, divider_count); - - lwla_queue_regval(acq, REG_CAP_CTRL, 0); - lwla_queue_regval(acq, REG_DURATION, 0); - - lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_RESET); - lwla_queue_regval(acq, REG_MEM_CTRL, 0); - lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_WRITE); - - lwla_queue_regval(acq, REG_CAP_CTRL, - CAP_CTRL_FIFO32_FULL | CAP_CTRL_FIFO64_FULL); - - lwla_queue_regval(acq, REG_CAP_CTRL, CAP_CTRL_FIFO_EMPTY); - lwla_queue_regval(acq, REG_CAP_CTRL, 0); - - lwla_queue_regval(acq, REG_CAP_COUNT, MEMORY_DEPTH - 5); + ret = lwla_write_reg(usb, REG_DIV_COUNT, divider_count); + if (ret != SR_OK) + return ret; - lwla_queue_regval(acq, REG_TRG_SEL, - ((devc->trigger_edge_mask & 0xFFFF) << 16) - | (devc->trigger_values & 0xFFFF)); + ret = lwla_write_regs(usb, ARRAY_AND_SIZE(capture_init)); + if (ret != SR_OK) + return ret; - ret = lwla_write_regs(usb, acq->reg_sequence, acq->reg_seq_len); - acq->reg_seq_len = 0; + trigger_setup = ((devc->trigger_edge_mask & 0xFFFF) << 16) + | (devc->trigger_values & 0xFFFF); - return ret; + return lwla_write_reg(usb, REG_TRG_SEL, trigger_setup); } static int prepare_request(const struct sr_dev_inst *sdi) { struct dev_context *devc; struct acquisition_state *acq; - unsigned int count; + unsigned int chunk_len, count; devc = sdi->priv; - acq = devc->acquisition; + acq = devc->acquisition; acq->xfer_out->length = 0; acq->reg_seq_pos = 0; @@ -319,9 +366,10 @@ static int prepare_request(const struct sr_dev_inst *sdi) lwla_queue_regval(acq, REG_CAP_COUNT, 0); break; case STATE_READ_REQUEST: - /* Always read a multiple of 8 device words. */ - count = MIN(READ_CHUNK_LEN32, - acq->mem_addr_stop - acq->mem_addr_next); + /* Limit reads to 16 device words (64 bytes) at a time if the + * device firmware has the short transfer quirk. */ + chunk_len = (devc->short_transfer_quirk) ? 16 : READ_CHUNK_LEN; + count = MIN(chunk_len, acq->mem_addr_stop - acq->mem_addr_next); acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM32); acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next); @@ -347,7 +395,7 @@ static int handle_response(const struct sr_dev_inst *sdi) int expect_len; devc = sdi->priv; - acq = devc->acquisition; + acq = devc->acquisition; switch (devc->state) { case STATE_STATUS_REQUEST: @@ -381,8 +429,7 @@ static int handle_response(const struct sr_dev_inst *sdi) return SR_OK; } -/* Model descriptor for the LWLA1016. - */ +/* Model descriptor for the LWLA1016. */ SR_PRIV const struct model_info lwla1016_info = { .name = "LWLA1016", .num_channels = NUM_CHANNELS,