X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fscpi-pps%2Fprofiles.c;h=6d52b05bad13c8729f72781232ef846d13da8b28;hb=43ff1110fb317fba796f942bbc73c37a95973b8b;hp=6db7d57677739713aef4f40d2ec8a417ebc59ab2;hpb=7e381bfc3c4999d7c433131f2790c7c5b8665b21;p=libsigrok.git diff --git a/src/hardware/scpi-pps/profiles.c b/src/hardware/scpi-pps/profiles.c index 6db7d576..6d52b05b 100644 --- a/src/hardware/scpi-pps/profiles.c +++ b/src/hardware/scpi-pps/profiles.c @@ -27,10 +27,14 @@ #define CH_IDX(x) (1 << x) #define FREQ_DC_ONLY {0, 0, 0, 0, 0} +#define NO_OVP_LIMITS {0, 0, 0, 0, 0} +#define NO_OCP_LIMITS {0, 0, 0, 0, 0} /* Agilent/Keysight N5700A series */ static const uint32_t agilent_n5700a_devopts[] = { SR_CONF_CONTINUOUS, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, }; static const uint32_t agilent_n5700a_devopts_cg[] = { @@ -48,11 +52,11 @@ static const struct channel_group_spec agilent_n5700a_cg[] = { }; static const struct channel_spec agilent_n5767a_ch[] = { - { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY }, + { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, }; static const struct channel_spec agilent_n5763a_ch[] = { - { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY }, + { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, }; /* @@ -82,9 +86,58 @@ static const struct scpi_command agilent_n5700a_cmd[] = { ALL_ZERO }; +/* BK Precision 9130 series */ +static const uint32_t bk_9130_devopts[] = { + SR_CONF_CONTINUOUS, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, +}; + +static const uint32_t bk_9130_devopts_cg[] = { + SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, + SR_CONF_VOLTAGE | SR_CONF_GET, + SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, + SR_CONF_CURRENT | SR_CONF_GET, + SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, + SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, +}; + +static const struct channel_spec bk_9130_ch[] = { + { "1", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, + { "2", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, + { "3", { 0, 5, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 15, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, +}; + +static const struct channel_group_spec bk_9130_cg[] = { + { "1", CH_IDX(0), PPS_OVP }, + { "2", CH_IDX(1), PPS_OVP }, + { "3", CH_IDX(2), PPS_OVP }, +}; + +static const struct scpi_command bk_9130_cmd[] = { + { SCPI_CMD_REMOTE, "SYST:REMOTE" }, + { SCPI_CMD_LOCAL, "SYST:LOCAL" }, + { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, + { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, + { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, + { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" }, + { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, + { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, + { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, + { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, + { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, + { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP 1" }, + { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP 0" }, + { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" }, + { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT %.6f" }, + ALL_ZERO +}; + /* Chroma 61600 series AC source */ static const uint32_t chroma_61604_devopts[] = { SR_CONF_CONTINUOUS, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, }; static const uint32_t chroma_61604_devopts_cg[] = { @@ -99,7 +152,7 @@ static const uint32_t chroma_61604_devopts_cg[] = { }; static const struct channel_spec chroma_61604_ch[] = { - { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 } }, + { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 }, NO_OVP_LIMITS, NO_OCP_LIMITS }, }; static const struct channel_group_spec chroma_61604_cg[] = { @@ -131,6 +184,8 @@ static const struct scpi_command chroma_61604_cmd[] = { /* Chroma 62000 series DC source */ static const uint32_t chroma_62000_devopts[] = { SR_CONF_CONTINUOUS, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, }; static const uint32_t chroma_62000_devopts_cg[] = { @@ -222,16 +277,18 @@ static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi, /* Rigol DP700 series */ static const uint32_t rigol_dp700_devopts[] = { SR_CONF_CONTINUOUS, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, }; static const uint32_t rigol_dp700_devopts_cg[] = { SR_CONF_REGULATION | SR_CONF_GET, SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, - SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, + SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, - SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, + SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, SR_CONF_VOLTAGE | SR_CONF_GET, SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, SR_CONF_CURRENT | SR_CONF_GET, @@ -240,11 +297,11 @@ static const uint32_t rigol_dp700_devopts_cg[] = { }; static const struct channel_spec rigol_dp711_ch[] = { - { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY }, + { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 33, 0.01}, { 0.01, 5.5, 0.01 } }, }; static const struct channel_spec rigol_dp712_ch[] = { - { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY }, + { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 55, 0.01}, { 0.01, 3.3, 0.01 } }, }; static const struct channel_group_spec rigol_dp700_cg[] = { @@ -289,6 +346,8 @@ static const struct scpi_command rigol_dp700_cmd[] = { static const uint32_t rigol_dp800_devopts[] = { SR_CONF_CONTINUOUS, SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, }; static const uint32_t rigol_dp800_devopts_cg[] = { @@ -307,20 +366,20 @@ static const uint32_t rigol_dp800_devopts_cg[] = { }; static const struct channel_spec rigol_dp821a_ch[] = { - { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY }, - { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY }, + { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, + { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, }; static const struct channel_spec rigol_dp831_ch[] = { - { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY }, - { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY }, - { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY }, + { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, + { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, + { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, }; static const struct channel_spec rigol_dp832_ch[] = { - { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY }, - { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY }, - { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY }, + { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, + { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, + { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, }; static const struct channel_group_spec rigol_dp820_cg[] = { @@ -373,6 +432,8 @@ static const struct scpi_command rigol_dp800_cmd[] = { /* HP 663xx series */ static const uint32_t hp_6630a_devopts[] = { SR_CONF_CONTINUOUS, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, }; static const uint32_t hp_6630a_devopts_cg[] = { @@ -381,30 +442,49 @@ static const uint32_t hp_6630a_devopts_cg[] = { SR_CONF_CURRENT | SR_CONF_GET, SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST, SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST, - SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET, + SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET | SR_CONF_LIST, SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET, }; -static const uint32_t hp_6632b_devopts[] = { +static const uint32_t hp_6630b_devopts[] = { SR_CONF_CONTINUOUS, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, }; -static const uint32_t hp_6632b_devopts_cg[] = { +static const uint32_t hp_6630b_devopts_cg[] = { SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, SR_CONF_VOLTAGE | SR_CONF_GET, SR_CONF_CURRENT | SR_CONF_GET, SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, - SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, + SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, + SR_CONF_REGULATION | SR_CONF_GET, }; static const struct channel_spec hp_6633a_ch[] = { - { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY }, + { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS }, +}; + +static const struct channel_spec hp_6631b_ch[] = { + { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 10.237, 0.00263, 4, 5 }, { 0, 83.84103 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS }, }; static const struct channel_spec hp_6632b_ch[] = { - { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY }, + { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS }, +}; + +static const struct channel_spec hp_66332a_ch[] = { + { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS }, +}; + +static const struct channel_spec hp_6633b_ch[] = { + { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.000526, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS }, +}; + +static const struct channel_spec hp_6634b_ch[] = { + { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.000263, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS }, }; static const struct channel_group_spec hp_663xx_cg[] = { @@ -424,7 +504,7 @@ static const struct scpi_command hp_6630a_cmd[] = { ALL_ZERO }; -static const struct scpi_command hp_6632b_cmd[] = { +static const struct scpi_command hp_6630b_cmd[] = { { SCPI_CMD_REMOTE, "SYST:REM" }, { SCPI_CMD_LOCAL, "SYST:LOC" }, { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" }, @@ -441,12 +521,15 @@ static const struct scpi_command hp_6632b_cmd[] = { { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" }, { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" }, { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" }, + { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" }, ALL_ZERO }; /* Philips/Fluke PM2800 series */ static const uint32_t philips_pm2800_devopts[] = { SR_CONF_CONTINUOUS, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, }; static const uint32_t philips_pm2800_devopts_cg[] = { @@ -595,6 +678,8 @@ static const struct scpi_command philips_pm2800_cmd[] = { static const uint32_t rs_hmc8043_devopts[] = { SR_CONF_CONTINUOUS, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, }; static const uint32_t rs_hmc8043_devopts_cg[] = { @@ -609,9 +694,9 @@ static const uint32_t rs_hmc8043_devopts_cg[] = { }; static const struct channel_spec rs_hmc8043_ch[] = { - { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY }, - { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY }, - { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY }, + { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, + { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, + { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, }; static const struct channel_group_spec rs_hmc8043_cg[] = { @@ -642,7 +727,7 @@ static const struct scpi_command rs_hmc8043_cmd[] = { SR_PRIV const struct scpi_pps pps_profiles[] = { /* Agilent N5763A */ - { "Agilent", "N5763A", 0, + { "Agilent", "N5763A", SCPI_DIALECT_UNKNOWN, 0, ARRAY_AND_SIZE(agilent_n5700a_devopts), ARRAY_AND_SIZE(agilent_n5700a_devopts_cg), ARRAY_AND_SIZE(agilent_n5763a_ch), @@ -652,7 +737,7 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { }, /* Agilent N5767A */ - { "Agilent", "N5767A", 0, + { "Agilent", "N5767A", SCPI_DIALECT_UNKNOWN, 0, ARRAY_AND_SIZE(agilent_n5700a_devopts), ARRAY_AND_SIZE(agilent_n5700a_devopts_cg), ARRAY_AND_SIZE(agilent_n5767a_ch), @@ -661,8 +746,18 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { .probe_channels = NULL, }, + /* BK Precision 9310 */ + { "BK", "^9130$", SCPI_DIALECT_UNKNOWN, 0, + ARRAY_AND_SIZE(bk_9130_devopts), + ARRAY_AND_SIZE(bk_9130_devopts_cg), + ARRAY_AND_SIZE(bk_9130_ch), + ARRAY_AND_SIZE(bk_9130_cg), + bk_9130_cmd, + .probe_channels = NULL, + }, + /* Chroma 61604 */ - { "Chroma", "61604", 0, + { "Chroma", "61604", SCPI_DIALECT_UNKNOWN, 0, ARRAY_AND_SIZE(chroma_61604_devopts), ARRAY_AND_SIZE(chroma_61604_devopts_cg), ARRAY_AND_SIZE(chroma_61604_ch), @@ -672,7 +767,7 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { }, /* Chroma 62000 series */ - { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", 0, + { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", SCPI_DIALECT_UNKNOWN, 0, ARRAY_AND_SIZE(chroma_62000_devopts), ARRAY_AND_SIZE(chroma_62000_devopts_cg), NULL, 0, @@ -682,7 +777,7 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { }, /* HP 6633A */ - { "HP", "6633A", 0, + { "HP", "6633A", SCPI_DIALECT_HP_COMP, 0, ARRAY_AND_SIZE(hp_6630a_devopts), ARRAY_AND_SIZE(hp_6630a_devopts_cg), ARRAY_AND_SIZE(hp_6633a_ch), @@ -691,18 +786,58 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { .probe_channels = NULL, }, + /* HP 6631B */ + { "HP", "6631B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP, + ARRAY_AND_SIZE(hp_6630b_devopts), + ARRAY_AND_SIZE(hp_6630b_devopts_cg), + ARRAY_AND_SIZE(hp_6631b_ch), + ARRAY_AND_SIZE(hp_663xx_cg), + hp_6630b_cmd, + .probe_channels = NULL, + }, + /* HP 6632B */ - { "HP", "6632B", PPS_OVP | PPS_OCP | PPS_OTP, - ARRAY_AND_SIZE(hp_6632b_devopts), - ARRAY_AND_SIZE(hp_6632b_devopts_cg), + { "HP", "6632B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP, + ARRAY_AND_SIZE(hp_6630b_devopts), + ARRAY_AND_SIZE(hp_6630b_devopts_cg), ARRAY_AND_SIZE(hp_6632b_ch), ARRAY_AND_SIZE(hp_663xx_cg), - hp_6632b_cmd, + hp_6630b_cmd, + .probe_channels = NULL, + }, + + /* HP 66332A */ + { "HP", "66332A", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP, + ARRAY_AND_SIZE(hp_6630b_devopts), + ARRAY_AND_SIZE(hp_6630b_devopts_cg), + ARRAY_AND_SIZE(hp_66332a_ch), + ARRAY_AND_SIZE(hp_663xx_cg), + hp_6630b_cmd, + .probe_channels = NULL, + }, + + /* HP 6633B */ + { "HP", "6633B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP, + ARRAY_AND_SIZE(hp_6630b_devopts), + ARRAY_AND_SIZE(hp_6630b_devopts_cg), + ARRAY_AND_SIZE(hp_6633b_ch), + ARRAY_AND_SIZE(hp_663xx_cg), + hp_6630b_cmd, + .probe_channels = NULL, + }, + + /* HP 6634B */ + { "HP", "6634B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP, + ARRAY_AND_SIZE(hp_6630b_devopts), + ARRAY_AND_SIZE(hp_6630b_devopts_cg), + ARRAY_AND_SIZE(hp_6634b_ch), + ARRAY_AND_SIZE(hp_663xx_cg), + hp_6630b_cmd, .probe_channels = NULL, }, /* Rigol DP700 series */ - { "Rigol", "^DP711$", 0, + { "Rigol", "^DP711$", SCPI_DIALECT_UNKNOWN, 0, ARRAY_AND_SIZE(rigol_dp700_devopts), ARRAY_AND_SIZE(rigol_dp700_devopts_cg), ARRAY_AND_SIZE(rigol_dp711_ch), @@ -710,7 +845,7 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { rigol_dp700_cmd, .probe_channels = NULL, }, - { "Rigol", "^DP712$", 0, + { "Rigol", "^DP712$", SCPI_DIALECT_UNKNOWN, 0, ARRAY_AND_SIZE(rigol_dp700_devopts), ARRAY_AND_SIZE(rigol_dp700_devopts_cg), ARRAY_AND_SIZE(rigol_dp712_ch), @@ -720,7 +855,7 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { }, /* Rigol DP800 series */ - { "Rigol", "^DP821A$", PPS_OTP, + { "Rigol", "^DP821A$", SCPI_DIALECT_UNKNOWN, PPS_OTP, ARRAY_AND_SIZE(rigol_dp800_devopts), ARRAY_AND_SIZE(rigol_dp800_devopts_cg), ARRAY_AND_SIZE(rigol_dp821a_ch), @@ -728,7 +863,7 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { rigol_dp800_cmd, .probe_channels = NULL, }, - { "Rigol", "^DP831A$", PPS_OTP, + { "Rigol", "^DP831A$", SCPI_DIALECT_UNKNOWN, PPS_OTP, ARRAY_AND_SIZE(rigol_dp800_devopts), ARRAY_AND_SIZE(rigol_dp800_devopts_cg), ARRAY_AND_SIZE(rigol_dp831_ch), @@ -736,7 +871,7 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { rigol_dp800_cmd, .probe_channels = NULL, }, - { "Rigol", "^(DP832|DP832A)$", PPS_OTP, + { "Rigol", "^(DP832|DP832A)$", SCPI_DIALECT_UNKNOWN, PPS_OTP, ARRAY_AND_SIZE(rigol_dp800_devopts), ARRAY_AND_SIZE(rigol_dp800_devopts_cg), ARRAY_AND_SIZE(rigol_dp832_ch), @@ -746,7 +881,7 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { }, /* Philips/Fluke PM2800 series */ - { "Philips", "^PM28[13][123]/[01234]{1,2}$", 0, + { "Philips", "^PM28[13][123]/[01234]{1,2}$", SCPI_DIALECT_PHILIPS, 0, ARRAY_AND_SIZE(philips_pm2800_devopts), ARRAY_AND_SIZE(philips_pm2800_devopts_cg), NULL, 0, @@ -756,7 +891,7 @@ SR_PRIV const struct scpi_pps pps_profiles[] = { }, /* Rohde & Schwarz HMC8043 */ - { "Rohde&Schwarz", "HMC8043", 0, + { "Rohde&Schwarz", "HMC8043", SCPI_DIALECT_UNKNOWN, 0, ARRAY_AND_SIZE(rs_hmc8043_devopts), ARRAY_AND_SIZE(rs_hmc8043_devopts_cg), ARRAY_AND_SIZE(rs_hmc8043_ch),