X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fsaleae-logic16%2Fprotocol.h;h=9f834164c83d14bb3603a75f1815348b13f74e02;hb=e2626373b73e7583a8a02454a6e0771a4f18be44;hp=cdfc3681c031aa8937a64c331425ad667c44414e;hpb=6f479a0a72492b2a28344de04776733b19fdbaa9;p=libsigrok.git diff --git a/src/hardware/saleae-logic16/protocol.h b/src/hardware/saleae-logic16/protocol.h index cdfc3681..9f834164 100644 --- a/src/hardware/saleae-logic16/protocol.h +++ b/src/hardware/saleae-logic16/protocol.h @@ -24,7 +24,7 @@ #include #include -#include "libsigrok.h" +#include #include "libsigrok-internal.h" #define LOG_PREFIX "saleae-logic16" @@ -37,6 +37,7 @@ enum voltage_range { enum fpga_variant { FPGA_VARIANT_ORIGINAL, + FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM, FPGA_VARIANT_MCUPRO /* mcupro clone v4.6 with Actel FPGA */ }; @@ -59,6 +60,9 @@ struct dev_context { /** Maximum number of samples to capture, if nonzero. */ uint64_t limit_samples; + /** Percent of the samples that should be captured before the trigger. */ + uint64_t capture_ratio; + /** The currently configured input voltage of the device. */ enum voltage_range cur_voltage_range; @@ -87,6 +91,10 @@ struct dev_context { unsigned int num_transfers; struct libusb_transfer **transfers; struct sr_context *ctx; + + const uint8_t *fpga_register_map; + const uint8_t *fpga_status_control_bit_map; + const uint8_t *fpga_mode_bit_map; }; SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, @@ -94,6 +102,6 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi); SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi); SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi); -SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer); +SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer); #endif