X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fsaleae-logic16%2Fprotocol.h;h=9f834164c83d14bb3603a75f1815348b13f74e02;hb=0a1f7b09b3fa4cc4da29c7acf53717e14b004b63;hp=75a2089939968d4fab23c5fa094ad67b14fa91b2;hpb=55462b8ba9f48931de9b9a7bfbc182a1d113b3b5;p=libsigrok.git

diff --git a/src/hardware/saleae-logic16/protocol.h b/src/hardware/saleae-logic16/protocol.h
index 75a20899..9f834164 100644
--- a/src/hardware/saleae-logic16/protocol.h
+++ b/src/hardware/saleae-logic16/protocol.h
@@ -24,7 +24,7 @@
 
 #include <stdint.h>
 #include <glib.h>
-#include "libsigrok.h"
+#include <libsigrok/libsigrok.h>
 #include "libsigrok-internal.h"
 
 #define LOG_PREFIX "saleae-logic16"
@@ -37,6 +37,7 @@ enum voltage_range {
 
 enum fpga_variant {
 	FPGA_VARIANT_ORIGINAL,
+	FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM,
 	FPGA_VARIANT_MCUPRO    /* mcupro clone v4.6 with Actel FPGA */
 };
 
@@ -90,6 +91,10 @@ struct dev_context {
 	unsigned int num_transfers;
 	struct libusb_transfer **transfers;
 	struct sr_context *ctx;
+
+	const uint8_t *fpga_register_map;
+	const uint8_t *fpga_status_control_bit_map;
+	const uint8_t *fpga_mode_bit_map;
 };
 
 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,