X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fsaleae-logic16%2Fprotocol.c;h=5566b85972f64d890543e7764e20f5442970af21;hb=1f706c21a2977c768692f72d09b35633628d2b0d;hp=7e4cb919c496f5ad16ee51ae5c8bf765a1e04c83;hpb=c86813962979777f53432e7e3392b1d2f2b661b4;p=libsigrok.git

diff --git a/src/hardware/saleae-logic16/protocol.c b/src/hardware/saleae-logic16/protocol.c
index 7e4cb919..5566b859 100644
--- a/src/hardware/saleae-logic16/protocol.c
+++ b/src/hardware/saleae-logic16/protocol.c
@@ -19,6 +19,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <config.h>
 #include <stdint.h>
 #include <string.h>
 #include <glib.h>
@@ -26,12 +27,12 @@
 #include <stdio.h>
 #include <errno.h>
 #include <math.h>
-#include "libsigrok.h"
+#include <libsigrok/libsigrok.h>
 #include "libsigrok-internal.h"
 #include "protocol.h"
 
-#define FPGA_FIRMWARE_18	FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
-#define FPGA_FIRMWARE_33	FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
+#define FPGA_FIRMWARE_18	"saleae-logic16-fpga-18.bitstream"
+#define FPGA_FIRMWARE_33	"saleae-logic16-fpga-33.bitstream"
 
 #define MAX_SAMPLE_RATE		SR_MHZ(100)
 #define MAX_4CH_SAMPLE_RATE	SR_MHZ(50)
@@ -214,7 +215,7 @@ static int do_ep1_command(const struct sr_dev_inst *sdi,
 	}
 	if (xfer != cmd_len) {
 		sr_dbg("Failed to send EP1 command 0x%02x: incorrect length "
-		       "%d != %d.", xfer, cmd_len);
+		       "%d != %d.", command[0], xfer, cmd_len);
 		return SR_ERR;
 	}
 
@@ -230,7 +231,7 @@ static int do_ep1_command(const struct sr_dev_inst *sdi,
 	}
 	if (xfer != reply_len) {
 		sr_dbg("Failed to receive reply to EP1 command 0x%02x: "
-		       "incorrect length %d != %d.", xfer, reply_len);
+		       "incorrect length %d != %d.", command[0], xfer, reply_len);
 		return SR_ERR;
 	}
 
@@ -363,10 +364,13 @@ static int setup_register_mapping(const struct sr_dev_inst *sdi)
 		if ((ret = read_fpga_register(sdi, 7 /* No mapping */, &reg7)) != SR_OK)
 			return ret;
 
-		if (reg0 == 0 && reg7 > 0x10)
+		if (reg0 == 0 && reg7 > 0x10) {
+			sr_info("Original Saleae Logic16 using new bitstream.");
 			devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM;
-		else
+		} else {
+			sr_info("Original Saleae Logic16 using old bitstream.");
 			devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
+		}
 	}
 
 	if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) {
@@ -461,13 +465,17 @@ static int configure_led(const struct sr_dev_inst *sdi)
 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
 				 enum voltage_range vrange)
 {
+	uint64_t sum;
+	struct sr_resource bitstream;
 	struct dev_context *devc;
-	int offset, chunksize, ret;
-	const char *filename;
-	uint8_t len, buf[256 * 62], command[64];
-	FILE *fw;
+	struct drv_context *drvc;
+	const char *name;
+	ssize_t chunksize;
+	int ret;
+	uint8_t command[64];
 
 	devc = sdi->priv;
+	drvc = sdi->driver->context;
 
 	if (devc->cur_voltage_range == vrange)
 		return SR_OK;
@@ -475,51 +483,51 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
 	if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) {
 		switch (vrange) {
 		case VOLTAGE_RANGE_18_33_V:
-			filename = FPGA_FIRMWARE_18;
+			name = FPGA_FIRMWARE_18;
 			break;
 		case VOLTAGE_RANGE_5_V:
-			filename = FPGA_FIRMWARE_33;
+			name = FPGA_FIRMWARE_33;
 			break;
 		default:
 			sr_err("Unsupported voltage range.");
 			return SR_ERR;
 		}
 
-		sr_info("Uploading FPGA bitstream at %s.", filename);
-		if (!(fw = g_fopen(filename, "rb"))) {
-			sr_err("Unable to open bitstream file %s for reading: %s.",
-			       filename, strerror(errno));
-			return SR_ERR;
-		}
+		sr_info("Uploading FPGA bitstream '%s'.", name);
+		ret = sr_resource_open(drvc->sr_ctx, &bitstream,
+				SR_RESOURCE_FIRMWARE, name);
+		if (ret != SR_OK)
+			return ret;
 
-		buf[0] = COMMAND_FPGA_UPLOAD_INIT;
-		if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
-			fclose(fw);
+		command[0] = COMMAND_FPGA_UPLOAD_INIT;
+		if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) {
+			sr_resource_close(drvc->sr_ctx, &bitstream);
 			return ret;
 		}
 
+		sum = 0;
 		while (1) {
-			chunksize = fread(buf, 1, sizeof(buf), fw);
+			chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
+					&command[2], sizeof(command) - 2);
+			if (chunksize < 0) {
+				sr_resource_close(drvc->sr_ctx, &bitstream);
+				return SR_ERR;
+			}
 			if (chunksize == 0)
 				break;
-
-			for (offset = 0; offset < chunksize; offset += 62) {
-				len = (offset + 62 > chunksize ?
-					chunksize - offset : 62);
-				command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
-				command[1] = len;
-				memcpy(command + 2, buf + offset, len);
-				ret = do_ep1_command(sdi, command, len + 2, NULL, 0);
-				if (ret != SR_OK) {
-					fclose(fw);
-					return ret;
-				}
+			command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
+			command[1] = chunksize;
+
+			ret = do_ep1_command(sdi, command, chunksize + 2,
+					NULL, 0);
+			if (ret != SR_OK) {
+				sr_resource_close(drvc->sr_ctx, &bitstream);
+				return ret;
 			}
-
-			sr_info("Uploaded %d bytes.", chunksize);
+			sum += chunksize;
 		}
-		fclose(fw);
-		sr_info("FPGA bitstream upload done.");
+		sr_resource_close(drvc->sr_ctx, &bitstream);
+		sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", sum);
 	}
 
 	/* This needs to be called before accessing any FPGA registers. */