X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fsaleae-logic16%2Fprotocol.c;h=26db651581f7eb0ac8288526eeab9ee817349d9c;hb=879dd50fb6d5f810d3c5635c3264b2c08ad22a70;hp=785833432749f2f71f772a841699197e5d56da41;hpb=155b680da482cea2381becb73c51cfb838bff31e;p=libsigrok.git

diff --git a/src/hardware/saleae-logic16/protocol.c b/src/hardware/saleae-logic16/protocol.c
index 78583343..26db6515 100644
--- a/src/hardware/saleae-logic16/protocol.c
+++ b/src/hardware/saleae-logic16/protocol.c
@@ -464,6 +464,9 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
 	if ((ret = read_fpga_register(sdi, 1, &reg1)) != SR_OK)
 		return ret;
 
+	/* Ignore FIFO overflow on previous capture */
+	reg1 &= ~0x20;
+
 	if (reg1 != 0x08) {
 		sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08.", reg1);
 		return SR_ERR;
@@ -540,8 +543,8 @@ SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi)
 	if ((ret = read_fpga_register(sdi, 1, &reg1)) != SR_OK)
 		return ret;
 
-	if (reg1 != 0x08) {
-		sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08.", reg1);
+	if ((reg1 & ~0x20) != 0x08) {
+		sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08.", reg1 & ~0x20);
 		return SR_ERR;
 	}
 
@@ -551,6 +554,11 @@ SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi)
 	if ((ret = read_fpga_register(sdi, 9, &reg9)) != SR_OK)
 		return ret;
 
+	if (reg1 & 0x20) {
+		sr_warn("FIFO overflow, capture data may be truncated.");
+		return SR_ERR;
+	}
+
 	return SR_OK;
 }