X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Frigol-ds%2Fapi.c;h=c7a8937690e796917d3a65707dd4dff2af3cb5e9;hb=d53295e69edda62f966488bb6e4c05c1c842c6fe;hp=d21cff7d34c511383f69cacd4149434fa94cc13e;hpb=934cf6cf5078f01517da303f21ed2ffee9b878f3;p=libsigrok.git

diff --git a/src/hardware/rigol-ds/api.c b/src/hardware/rigol-ds/api.c
index d21cff7d..c7a89376 100644
--- a/src/hardware/rigol-ds/api.c
+++ b/src/hardware/rigol-ds/api.c
@@ -43,6 +43,7 @@ static const uint32_t devopts[] = {
 	SR_CONF_TIMEBASE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
 	SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
 	SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+	SR_CONF_TRIGGER_LEVEL | SR_CONF_GET | SR_CONF_SET,
 	SR_CONF_HORIZ_TRIGGERPOS | SR_CONF_SET,
 	SR_CONF_NUM_HDIV | SR_CONF_GET,
 	SR_CONF_SAMPLERATE | SR_CONF_GET,
@@ -257,6 +258,8 @@ static const struct rigol_ds_model supported_models[] = {
 	{SERIES(DS1000Z), "DS1104Z", {5, 1000000000}, 4, false},
 	{SERIES(DS1000Z), "DS1074Z-S", {5, 1000000000}, 4, false},
 	{SERIES(DS1000Z), "DS1104Z-S", {5, 1000000000}, 4, false},
+	{SERIES(DS1000Z), "DS1074Z Plus", {5, 1000000000}, 4, false},
+	{SERIES(DS1000Z), "DS1104Z Plus", {5, 1000000000}, 4, false},
 	{SERIES(DS1000Z), "MSO1074Z", {5, 1000000000}, 4, true},
 	{SERIES(DS1000Z), "MSO1104Z", {5, 1000000000}, 4, true},
 	{SERIES(DS1000Z), "MSO1074Z-S", {5, 1000000000}, 4, true},
@@ -588,6 +591,9 @@ static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *s
 		}
 		*data = g_variant_new_string(tmp_str);
 		break;
+	case SR_CONF_TRIGGER_LEVEL:
+		*data = g_variant_new_double(devc->trigger_level);
+		break;
 	case SR_CONF_TIMEBASE:
 		for (i = 0; i < devc->num_timebases; i++) {
 			float tb = (float)devc->timebases[i][0] / devc->timebases[i][1];
@@ -697,6 +703,13 @@ static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sd
 		g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
 		ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer);
 		break;
+	case SR_CONF_TRIGGER_LEVEL:
+		t_dbl = g_variant_get_double(data);
+		g_ascii_formatd(buffer, sizeof(buffer), "%.3f", t_dbl);
+		ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:LEV %s", buffer);
+		if (ret == SR_OK)
+			devc->trigger_level = t_dbl;
+		break;
 	case SR_CONF_TIMEBASE:
 		g_variant_get(data, "(tt)", &p, &q);
 		for (i = 0; i < devc->num_timebases; i++) {