X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Frigol-ds%2Fapi.c;h=c39e10c80229294afc1dc4d1165059ee9befcb40;hb=0f8bee7162f41095ca1975fec9a87975ce5a554a;hp=72f41b4c75cbf70b82a9d1884e5fa7fd2b60bd4c;hpb=53012da658ae94b245240c8a3e115723eede4c7d;p=libsigrok.git

diff --git a/src/hardware/rigol-ds/api.c b/src/hardware/rigol-ds/api.c
index 72f41b4c..c39e10c8 100644
--- a/src/hardware/rigol-ds/api.c
+++ b/src/hardware/rigol-ds/api.c
@@ -126,9 +126,6 @@ static const uint64_t vdivs[][2] = {
 	{ 100, 1 },
 };
 
-#define NUM_TIMEBASE  ARRAY_SIZE(timebases)
-#define NUM_VDIV      ARRAY_SIZE(vdivs)
-
 static const char *trigger_sources[] = {
 	"CH1",
 	"CH2",
@@ -206,8 +203,8 @@ static const struct rigol_ds_vendor supported_vendors[] = {
 };
 
 #define VENDOR(x) &supported_vendors[x]
-/* vendor, series, protocol, max timebase, min vdiv, number of horizontal divs,
- * live waveform samples, memory buffer samples */
+/* vendor, series/name, protocol, data format, max timebase, min vdiv,
+ * number of horizontal divs, live waveform samples, memory buffer samples */
 static const struct rigol_ds_series supported_series[] = {
 	[VS5000] = {VENDOR(RIGOL), "VS5000", PROTOCOL_V1, FORMAT_RAW,
 		{50, 1}, {2, 1000}, 14, 2048, 0},
@@ -397,18 +394,18 @@ static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
 				devc->digital_group);
 	}
 
-	for (i = 0; i < NUM_TIMEBASE; i++) {
+	for (i = 0; i < ARRAY_SIZE(timebases); i++) {
 		if (!memcmp(&devc->model->min_timebase, &timebases[i], sizeof(uint64_t[2])))
 			devc->timebases = &timebases[i];
 		if (!memcmp(&devc->model->series->max_timebase, &timebases[i], sizeof(uint64_t[2])))
 			devc->num_timebases = &timebases[i] - devc->timebases + 1;
 	}
 
-	for (i = 0; i < NUM_VDIV; i++) {
+	for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
 		if (!memcmp(&devc->model->series->min_vdiv,
 					&vdivs[i], sizeof(uint64_t[2]))) {
 			devc->vdivs = &vdivs[i];
-			devc->num_vdivs = NUM_VDIV - i;
+			devc->num_vdivs = ARRAY_SIZE(vdivs) - i;
 		}
 	}