X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Frigol-ds%2Fapi.c;h=af15587db2e36fef02c2a6c1963e01ad56e81542;hb=1cbb3b1cfbd0334001bde052413cc7aa869d5994;hp=bdbdbc0e7e75e840a97e314ebbd7b438cf5433f9;hpb=dd7a72ea697a172032f5473b0ddff5e8d47222f4;p=libsigrok.git diff --git a/src/hardware/rigol-ds/api.c b/src/hardware/rigol-ds/api.c index bdbdbc0e..af15587d 100644 --- a/src/hardware/rigol-ds/api.c +++ b/src/hardware/rigol-ds/api.c @@ -126,7 +126,14 @@ static const uint64_t vdivs[][2] = { { 100, 1 }, }; -static const char *trigger_sources[] = { +static const char *trigger_sources_2_chans[] = { + "CH1", "CH2", + "EXT", "AC Line", + "D0", "D1", "D2", "D3", "D4", "D5", "D6", "D7", + "D8", "D9", "D10", "D11", "D12", "D13", "D14", "D15", +}; + +static const char *trigger_sources_4_chans[] = { "CH1", "CH2", "CH3", "CH4", "EXT", "AC Line", "D0", "D1", "D2", "D3", "D4", "D5", "D6", "D7", @@ -152,6 +159,16 @@ static const char *data_sources[] = { "Segmented", }; +static const struct rigol_ds_command std_cmd[] = { + { CMD_GET_HORIZ_TRIGGERPOS, ":TIM:OFFS?" }, + { CMD_SET_HORIZ_TRIGGERPOS, ":TIM:OFFS %s" }, +}; + +static const struct rigol_ds_command mso7000a_cmd[] = { + { CMD_GET_HORIZ_TRIGGERPOS, ":TIM:POS?" }, + { CMD_SET_HORIZ_TRIGGERPOS, ":TIM:POS %s" }, +}; + enum vendor { RIGOL, AGILENT, @@ -163,7 +180,11 @@ enum series { DS2000, DS2000A, DSO1000, + DSO1000B, DS1000Z, + DS4000, + MSO5000, + MSO7000A, }; /* short name, full name */ @@ -186,58 +207,88 @@ static const struct rigol_ds_series supported_series[] = { {1000, 1}, {500, 1000000}, 14, 1400, 14000}, [DSO1000] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2, {50, 1}, {2, 1000}, 12, 600, 20480}, + [DSO1000B] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2, + {50, 1}, {2, 1000}, 12, 600, 20480}, [DS1000Z] = {VENDOR(RIGOL), "DS1000Z", PROTOCOL_V4, FORMAT_IEEE488_2, {50, 1}, {1, 1000}, 12, 1200, 12000000}, + [DS4000] = {VENDOR(RIGOL), "DS4000", PROTOCOL_V4, FORMAT_IEEE488_2, + {1000, 1}, {1, 1000}, 14, 1400, 0}, + [MSO5000] = {VENDOR(RIGOL), "MSO5000", PROTOCOL_V5, FORMAT_IEEE488_2, + {1000, 1}, {500, 1000000}, 10, 1000, 0}, + [MSO7000A] = {VENDOR(AGILENT), "MSO7000A", PROTOCOL_V4, FORMAT_IEEE488_2, + {50, 1}, {2, 1000}, 10, 1000, 8000000}, }; #define SERIES(x) &supported_series[x] +/* + * Use a macro to select the correct list of trigger sources and its length + * based on the number of analog channels and presence of digital channels. + */ +#define CH_INFO(num, digital) \ + num, digital, trigger_sources_##num##_chans, \ + digital ? ARRAY_SIZE(trigger_sources_##num##_chans) : (num + 2) /* series, model, min timebase, analog channels, digital */ static const struct rigol_ds_model supported_models[] = { - {SERIES(VS5000), "VS5022", {20, 1000000000}, 2, false}, - {SERIES(VS5000), "VS5042", {10, 1000000000}, 2, false}, - {SERIES(VS5000), "VS5062", {5, 1000000000}, 2, false}, - {SERIES(VS5000), "VS5102", {2, 1000000000}, 2, false}, - {SERIES(VS5000), "VS5202", {2, 1000000000}, 2, false}, - {SERIES(VS5000), "VS5022D", {20, 1000000000}, 2, true}, - {SERIES(VS5000), "VS5042D", {10, 1000000000}, 2, true}, - {SERIES(VS5000), "VS5062D", {5, 1000000000}, 2, true}, - {SERIES(VS5000), "VS5102D", {2, 1000000000}, 2, true}, - {SERIES(VS5000), "VS5202D", {2, 1000000000}, 2, true}, - {SERIES(DS1000), "DS1052E", {5, 1000000000}, 2, false}, - {SERIES(DS1000), "DS1102E", {2, 1000000000}, 2, false}, - {SERIES(DS1000), "DS1152E", {2, 1000000000}, 2, false}, - {SERIES(DS1000), "DS1052D", {5, 1000000000}, 2, true}, - {SERIES(DS1000), "DS1102D", {2, 1000000000}, 2, true}, - {SERIES(DS1000), "DS1152D", {2, 1000000000}, 2, true}, - {SERIES(DS2000), "DS2072", {5, 1000000000}, 2, false}, - {SERIES(DS2000), "DS2102", {5, 1000000000}, 2, false}, - {SERIES(DS2000), "DS2202", {2, 1000000000}, 2, false}, - {SERIES(DS2000), "DS2302", {1, 1000000000}, 2, false}, - {SERIES(DS2000A), "DS2072A", {5, 1000000000}, 2, false}, - {SERIES(DS2000A), "DS2102A", {5, 1000000000}, 2, false}, - {SERIES(DS2000A), "DS2202A", {2, 1000000000}, 2, false}, - {SERIES(DS2000A), "DS2302A", {1, 1000000000}, 2, false}, - {SERIES(DS2000A), "MSO2072A", {5, 1000000000}, 2, true}, - {SERIES(DS2000A), "MSO2102A", {5, 1000000000}, 2, true}, - {SERIES(DS2000A), "MSO2202A", {2, 1000000000}, 2, true}, - {SERIES(DS2000A), "MSO2302A", {1, 1000000000}, 2, true}, - {SERIES(DSO1000), "DSO1002A", {5, 1000000000}, 2, false}, - {SERIES(DSO1000), "DSO1004A", {5, 1000000000}, 4, false}, - {SERIES(DSO1000), "DSO1012A", {2, 1000000000}, 2, false}, - {SERIES(DSO1000), "DSO1014A", {2, 1000000000}, 4, false}, - {SERIES(DSO1000), "DSO1022A", {2, 1000000000}, 2, false}, - {SERIES(DSO1000), "DSO1024A", {2, 1000000000}, 4, false}, - {SERIES(DS1000Z), "DS1054Z", {5, 1000000000}, 4, false}, - {SERIES(DS1000Z), "DS1074Z", {5, 1000000000}, 4, false}, - {SERIES(DS1000Z), "DS1104Z", {5, 1000000000}, 4, false}, - {SERIES(DS1000Z), "DS1074Z-S", {5, 1000000000}, 4, false}, - {SERIES(DS1000Z), "DS1104Z-S", {5, 1000000000}, 4, false}, - {SERIES(DS1000Z), "DS1074Z Plus", {5, 1000000000}, 4, false}, - {SERIES(DS1000Z), "DS1104Z Plus", {5, 1000000000}, 4, false}, - {SERIES(DS1000Z), "MSO1074Z", {5, 1000000000}, 4, true}, - {SERIES(DS1000Z), "MSO1104Z", {5, 1000000000}, 4, true}, - {SERIES(DS1000Z), "MSO1074Z-S", {5, 1000000000}, 4, true}, - {SERIES(DS1000Z), "MSO1104Z-S", {5, 1000000000}, 4, true}, + {SERIES(VS5000), "VS5022", {20, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(VS5000), "VS5042", {10, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(VS5000), "VS5062", {5, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(VS5000), "VS5102", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(VS5000), "VS5202", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(VS5000), "VS5022D", {20, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(VS5000), "VS5042D", {10, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(VS5000), "VS5062D", {5, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(VS5000), "VS5102D", {2, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(VS5000), "VS5202D", {2, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(DS1000), "DS1052E", {5, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS1000), "DS1102E", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS1000), "DS1152E", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS1000), "DS1152E-EDU", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS1000), "DS1052D", {5, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(DS1000), "DS1102D", {2, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(DS1000), "DS1152D", {2, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(DS2000), "DS2072", {5, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS2000), "DS2102", {5, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS2000), "DS2202", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS2000), "DS2302", {1, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS2000A), "DS2072A", {5, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS2000A), "DS2102A", {5, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS2000A), "DS2202A", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS2000A), "DS2302A", {1, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS2000A), "MSO2072A", {5, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(DS2000A), "MSO2102A", {5, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(DS2000A), "MSO2202A", {2, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(DS2000A), "MSO2302A", {1, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(DSO1000), "DSO1002A", {5, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DSO1000), "DSO1004A", {5, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(DSO1000), "DSO1012A", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DSO1000), "DSO1014A", {2, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(DSO1000), "DSO1022A", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DSO1000), "DSO1024A", {2, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(DSO1000B), "DSO1052B", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DSO1000B), "DSO1072B", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DSO1000B), "DSO1102B", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DSO1000B), "DSO1152B", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS1000Z), "DS1054Z", {5, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(DS1000Z), "DS1074Z", {5, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(DS1000Z), "DS1104Z", {5, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(DS1000Z), "DS1074Z-S", {5, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(DS1000Z), "DS1104Z-S", {5, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(DS1000Z), "DS1074Z Plus", {5, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(DS1000Z), "DS1104Z Plus", {5, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(DS1000Z), "DS1202Z-E", {2, 1000000000}, CH_INFO(2, false), std_cmd}, + {SERIES(DS1000Z), "MSO1074Z", {5, 1000000000}, CH_INFO(4, true), std_cmd}, + {SERIES(DS1000Z), "MSO1104Z", {5, 1000000000}, CH_INFO(4, true), std_cmd}, + {SERIES(DS1000Z), "MSO1074Z-S", {5, 1000000000}, CH_INFO(4, true), std_cmd}, + {SERIES(DS1000Z), "MSO1104Z-S", {5, 1000000000}, CH_INFO(4, true), std_cmd}, + {SERIES(DS4000), "DS4024", {1, 1000000000}, CH_INFO(4, false), std_cmd}, + {SERIES(MSO5000), "MSO5072", {1, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(MSO5000), "MSO5074", {1, 1000000000}, CH_INFO(4, true), std_cmd}, + {SERIES(MSO5000), "MSO5102", {1, 1000000000}, CH_INFO(2, true), std_cmd}, + {SERIES(MSO5000), "MSO5104", {1, 1000000000}, CH_INFO(4, true), std_cmd}, + {SERIES(MSO5000), "MSO5204", {1, 1000000000}, CH_INFO(4, true), std_cmd}, + {SERIES(MSO5000), "MSO5354", {1, 1000000000}, CH_INFO(4, true), std_cmd}, + /* TODO: Digital channels are not yet supported on MSO7000A. */ + {SERIES(MSO7000A), "MSO7034A", {2, 1000000000}, CH_INFO(4, false), mso7000a_cmd}, }; static struct sr_dev_driver rigol_ds_driver_info; @@ -475,7 +526,6 @@ static int config_get(uint32_t key, GVariant **data, struct dev_context *devc; struct sr_channel *ch; const char *tmp_str; - uint64_t samplerate; int analog_channel = -1; float smallest_diff = INFINITY; int idx = -1; @@ -519,14 +569,7 @@ static int config_get(uint32_t key, GVariant **data, *data = g_variant_new_string("Segmented"); break; case SR_CONF_SAMPLERATE: - if (devc->data_source == DATA_SOURCE_LIVE) { - samplerate = analog_frame_size(sdi) / - (devc->timebase * devc->model->series->num_horizontal_divs); - *data = g_variant_new_uint64(samplerate); - } else { - sr_dbg("Unknown data source: %d.", devc->data_source); - return SR_ERR_NA; - } + *data = g_variant_new_uint64(devc->sample_rate); break; case SR_CONF_TRIGGER_SOURCE: if (!strcmp(devc->trigger_source, "ACL")) @@ -617,10 +660,9 @@ static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) { struct dev_context *devc; - uint64_t p, q; + uint64_t p; double t_dbl; - unsigned int i, j; - int ret; + int ret, idx, i; const char *tmp_str; char buffer[16]; @@ -632,24 +674,16 @@ static int config_set(uint32_t key, GVariant *data, return SR_ERR; } - ret = SR_OK; switch (key) { case SR_CONF_LIMIT_FRAMES: devc->limit_frames = g_variant_get_uint64(data); break; case SR_CONF_TRIGGER_SLOPE: - tmp_str = g_variant_get_string(data, NULL); - - if (!tmp_str || !(tmp_str[0] == 'f' || tmp_str[0] == 'r')) { - sr_err("Unknown trigger slope: '%s'.", - (tmp_str) ? tmp_str : "NULL"); + if ((idx = std_str_idx(data, ARRAY_AND_SIZE(trigger_slopes))) < 0) return SR_ERR_ARG; - } - g_free(devc->trigger_slope); - devc->trigger_slope = g_strdup((tmp_str[0] == 'r') ? "POS" : "NEG"); - ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope); - break; + devc->trigger_slope = g_strdup((trigger_slopes[idx][0] == 'r') ? "POS" : "NEG"); + return rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope); case SR_CONF_HORIZ_TRIGGERPOS: t_dbl = g_variant_get_double(data); if (t_dbl < 0.0 || t_dbl > 1.0) { @@ -661,121 +695,73 @@ static int config_set(uint32_t key, GVariant *data, * need to express this in seconds. */ t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases; g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl); - ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer); - break; + return rigol_ds_config_set(sdi, + devc->model->cmds[CMD_SET_HORIZ_TRIGGERPOS].str, buffer); case SR_CONF_TRIGGER_LEVEL: t_dbl = g_variant_get_double(data); g_ascii_formatd(buffer, sizeof(buffer), "%.3f", t_dbl); ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:LEV %s", buffer); if (ret == SR_OK) devc->trigger_level = t_dbl; - break; + return ret; case SR_CONF_TIMEBASE: - g_variant_get(data, "(tt)", &p, &q); - for (i = 0; i < devc->num_timebases; i++) { - if (devc->timebases[i][0] == p && devc->timebases[i][1] == q) { - devc->timebase = (float)p / q; - g_ascii_formatd(buffer, sizeof(buffer), "%.9f", - devc->timebase); - ret = rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer); - break; - } - } - if (i == devc->num_timebases) { - sr_err("Invalid timebase index: %d.", i); - ret = SR_ERR_ARG; - } - break; + if ((idx = std_u64_tuple_idx(data, devc->timebases, devc->num_timebases)) < 0) + return SR_ERR_ARG; + devc->timebase = (float)devc->timebases[idx][0] / devc->timebases[idx][1]; + g_ascii_formatd(buffer, sizeof(buffer), "%.9f", + devc->timebase); + return rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer); case SR_CONF_TRIGGER_SOURCE: - tmp_str = g_variant_get_string(data, NULL); - for (i = 0; i < ARRAY_SIZE(trigger_sources); i++) { - if (!strcmp(trigger_sources[i], tmp_str)) { - g_free(devc->trigger_source); - devc->trigger_source = g_strdup(trigger_sources[i]); - if (!strcmp(devc->trigger_source, "AC Line")) - tmp_str = "ACL"; - else if (!strcmp(devc->trigger_source, "CH1")) - tmp_str = "CHAN1"; - else if (!strcmp(devc->trigger_source, "CH2")) - tmp_str = "CHAN2"; - else if (!strcmp(devc->trigger_source, "CH3")) - tmp_str = "CHAN3"; - else if (!strcmp(devc->trigger_source, "CH4")) - tmp_str = "CHAN4"; - else - tmp_str = (char *)devc->trigger_source; - ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str); - break; - } - } - if (i == ARRAY_SIZE(trigger_sources)) { - sr_err("Invalid trigger source index: %d.", i); - ret = SR_ERR_ARG; - } - break; + if ((idx = std_str_idx(data, devc->model->trigger_sources, devc->model->num_trigger_sources)) < 0) + return SR_ERR_ARG; + g_free(devc->trigger_source); + devc->trigger_source = g_strdup(devc->model->trigger_sources[idx]); + if (!strcmp(devc->trigger_source, "AC Line")) + tmp_str = "ACL"; + else if (!strcmp(devc->trigger_source, "CH1")) + tmp_str = "CHAN1"; + else if (!strcmp(devc->trigger_source, "CH2")) + tmp_str = "CHAN2"; + else if (!strcmp(devc->trigger_source, "CH3")) + tmp_str = "CHAN3"; + else if (!strcmp(devc->trigger_source, "CH4")) + tmp_str = "CHAN4"; + else + tmp_str = (char *)devc->trigger_source; + return rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str); case SR_CONF_VDIV: if (!cg) return SR_ERR_CHANNEL_GROUP; - g_variant_get(data, "(tt)", &p, &q); - for (i = 0; i < devc->model->analog_channels; i++) { - if (cg == devc->analog_groups[i]) { - for (j = 0; j < ARRAY_SIZE(vdivs); j++) { - if (vdivs[j][0] != p || vdivs[j][1] != q) - continue; - devc->vdiv[i] = (float)p / q; - g_ascii_formatd(buffer, sizeof(buffer), "%.3f", - devc->vdiv[i]); - return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1, - buffer); - } - sr_err("Invalid vdiv index: %d.", j); - return SR_ERR_ARG; - } - } - sr_dbg("Didn't set vdiv, unknown channel(group)."); - return SR_ERR_NA; + if ((i = std_cg_idx(cg, devc->analog_groups, devc->model->analog_channels)) < 0) + return SR_ERR_ARG; + if ((idx = std_u64_tuple_idx(data, ARRAY_AND_SIZE(vdivs))) < 0) + return SR_ERR_ARG; + devc->vdiv[i] = (float)vdivs[idx][0] / vdivs[idx][1]; + g_ascii_formatd(buffer, sizeof(buffer), "%.3f", devc->vdiv[i]); + return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1, buffer); case SR_CONF_COUPLING: if (!cg) return SR_ERR_CHANNEL_GROUP; - tmp_str = g_variant_get_string(data, NULL); - for (i = 0; i < devc->model->analog_channels; i++) { - if (cg == devc->analog_groups[i]) { - for (j = 0; j < ARRAY_SIZE(coupling); j++) { - if (!strcmp(tmp_str, coupling[j])) { - g_free(devc->coupling[i]); - devc->coupling[i] = g_strdup(coupling[j]); - return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1, - devc->coupling[i]); - } - } - sr_err("Invalid coupling index: %d.", j); - return SR_ERR_ARG; - } - } - sr_dbg("Didn't set coupling, unknown channel(group)."); - return SR_ERR_NA; + if ((i = std_cg_idx(cg, devc->analog_groups, devc->model->analog_channels)) < 0) + return SR_ERR_ARG; + if ((idx = std_str_idx(data, ARRAY_AND_SIZE(coupling))) < 0) + return SR_ERR_ARG; + g_free(devc->coupling[i]); + devc->coupling[i] = g_strdup(coupling[idx]); + return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1, devc->coupling[i]); case SR_CONF_PROBE_FACTOR: if (!cg) return SR_ERR_CHANNEL_GROUP; + if ((i = std_cg_idx(cg, devc->analog_groups, devc->model->analog_channels)) < 0) + return SR_ERR_ARG; + if ((idx = std_u64_idx(data, ARRAY_AND_SIZE(probe_factor))) < 0) + return SR_ERR_ARG; p = g_variant_get_uint64(data); - for (i = 0; i < devc->model->analog_channels; i++) { - if (cg == devc->analog_groups[i]) { - for (j = 0; j < ARRAY_SIZE(probe_factor); j++) { - if (p == probe_factor[j]) { - devc->attenuation[i] = p; - ret = rigol_ds_config_set(sdi, ":CHAN%d:PROB %"PRIu64, - i + 1, p); - if (ret == SR_OK) - rigol_ds_get_dev_cfg_vertical(sdi); - return ret; - } - } - sr_err("Invalid probe factor: %"PRIu64".", p); - return SR_ERR_ARG; - } - } - sr_dbg("Didn't set probe factor, unknown channel(group)."); - return SR_ERR_NA; + devc->attenuation[i] = probe_factor[idx]; + ret = rigol_ds_config_set(sdi, ":CHAN%d:PROB %"PRIu64, i + 1, p); + if (ret == SR_OK) + rigol_ds_get_dev_cfg_vertical(sdi); + return ret; case SR_CONF_DATA_SOURCE: tmp_str = g_variant_get_string(data, NULL); if (!strcmp(tmp_str, "Live")) @@ -795,13 +781,12 @@ static int config_set(uint32_t key, GVariant *data, return SR_ERR_NA; } - return ret; + return SR_OK; } static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) { - unsigned int i; struct dev_context *devc; devc = (sdi) ? sdi->priv : NULL; @@ -811,17 +796,16 @@ static int config_list(uint32_t key, GVariant **data, case SR_CONF_DEVICE_OPTIONS: if (!cg) return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts); + if (!devc) + return SR_ERR_ARG; if (cg == devc->digital_group) { *data = std_gvar_array_u32(NULL, 0); return SR_OK; } else { - for (i = 0; i < devc->model->analog_channels; i++) { - if (cg == devc->analog_groups[i]) { - *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg_analog)); - return SR_OK; - } - } - return SR_ERR_NA; + if (std_cg_idx(cg, devc->analog_groups, devc->model->analog_channels) < 0) + return SR_ERR_ARG; + *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg_analog)); + return SR_OK; } break; case SR_CONF_COUPLING: @@ -854,8 +838,7 @@ static int config_list(uint32_t key, GVariant **data, if (!devc) /* Can't know this until we have the exact model. */ return SR_ERR_ARG; - *data = g_variant_new_strv(trigger_sources, - devc->model->has_digital ? ARRAY_SIZE(trigger_sources) : 4); + *data = g_variant_new_strv(devc->model->trigger_sources, devc->model->num_trigger_sources); break; case SR_CONF_TRIGGER_SLOPE: *data = g_variant_new_strv(ARRAY_AND_SIZE(trigger_slopes)); @@ -888,9 +871,9 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi) struct sr_scpi_dev_inst *scpi; struct dev_context *devc; struct sr_channel *ch; - struct sr_datafeed_packet packet; gboolean some_digital; GSList *l; + char *cmd; scpi = sdi->conn; devc = sdi->priv; @@ -933,9 +916,14 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi) } if (ch->enabled != devc->digital_channels[ch->index]) { /* Enabled channel is currently disabled, or vice versa. */ - if (rigol_ds_config_set(sdi, - devc->model->series->protocol >= PROTOCOL_V3 ? - ":LA:DIG%d:DISP %s" : ":DIG%d:TURN %s", ch->index, + if (devc->model->series->protocol >= PROTOCOL_V5) + cmd = ":LA:DISP D%d,%s"; + else if (devc->model->series->protocol >= PROTOCOL_V3) + cmd = ":LA:DIG%d:DISP %s"; + else + cmd = ":DIG%d:TURN %s"; + + if (rigol_ds_config_set(sdi, cmd, ch->index, ch->enabled ? "ON" : "OFF") != SR_OK) return SR_ERR; devc->digital_channels[ch->index] = ch->enabled; @@ -994,12 +982,25 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi) devc->channel_entry = devc->enabled_channels; + if (devc->data_source == DATA_SOURCE_LIVE) + devc->sample_rate = analog_frame_size(sdi) / + (devc->timebase * devc->model->series->num_horizontal_divs); + else { + float xinc; + if (devc->model->series->protocol >= PROTOCOL_V3 && + sr_scpi_get_float(sdi->conn, "WAV:XINC?", &xinc) != SR_OK) { + sr_err("Couldn't get sampling rate"); + return SR_ERR; + } + devc->sample_rate = 1. / xinc; + } + + if (rigol_ds_capture_start(sdi) != SR_OK) return SR_ERR; /* Start of first frame. */ - packet.type = SR_DF_FRAME_BEGIN; - sr_session_send(sdi, &packet); + std_session_send_df_frame_begin(sdi); return SR_OK; }