X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fopenbench-logic-sniffer%2Fapi.c;h=5e74a5236e745b56de2bfde26e3baa8ebebf212f;hb=6ad2fbaad2722f0aa18c3600cdbdddf812784b2d;hp=970d4a61dff3d6354f030c987e4b3a7da3c100d1;hpb=43376f3324cddd257a0260b06d9db8180c35fdf3;p=libsigrok.git

diff --git a/src/hardware/openbench-logic-sniffer/api.c b/src/hardware/openbench-logic-sniffer/api.c
index 970d4a61..5e74a523 100644
--- a/src/hardware/openbench-logic-sniffer/api.c
+++ b/src/hardware/openbench-logic-sniffer/api.c
@@ -126,14 +126,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 	if (serial_open(serial, SERIAL_RDWR) != SR_OK)
 		return NULL;
 
-	ret = SR_OK;
-	for (i = 0; i < 5; i++) {
-		if ((ret = send_shortcommand(serial, CMD_RESET)) != SR_OK) {
-			sr_err("Port %s is not writable.", conn);
-			break;
-		}
-	}
-	if (ret != SR_OK) {
+	if (ols_send_reset(serial) != SR_OK) {
 		serial_close(serial);
 		sr_err("Could not use port %s. Quitting.", conn);
 		return NULL;
@@ -480,6 +473,14 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 		return SR_ERR;
 	}
 	if (devc->num_stages > 0) {
+		/*
+		 * According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf
+		 * reset command must be send prior each arm command
+		 */
+		sr_dbg("Send reset command before trigger configure");
+		if (ols_send_reset(serial) != SR_OK)
+			return SR_ERR;
+
 		delaycount = readcount * (1 - devc->capture_ratio / 100.0);
 		devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
 		for (i = 0; i <= devc->num_stages; i++) {
@@ -543,7 +544,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 	devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
 	memset(devc->sample, 0, 4);
 
-	std_session_send_df_header(sdi, LOG_PREFIX);
+	std_session_send_df_header(sdi);
 
 	/* If the device stops sending for longer than it takes to send a byte,
 	 * that means it's finished. But wait at least 100 ms to be safe.