X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fkingst-la2016%2Fprotocol.h;h=995ae64bfd80f063626e01f0399f9c7c04ad7d62;hb=d32120c4c30650c30720d04eaf88dcf7b76a1e9f;hp=ffdd09a242be17d364df7bbfe092797f9f839a50;hpb=0fbb464bdf0951228d4430794263bb48bc668821;p=libsigrok.git

diff --git a/src/hardware/kingst-la2016/protocol.h b/src/hardware/kingst-la2016/protocol.h
index ffdd09a2..995ae64b 100644
--- a/src/hardware/kingst-la2016/protocol.h
+++ b/src/hardware/kingst-la2016/protocol.h
@@ -67,7 +67,7 @@
  * The device expects some zero padding to follow the content of the
  * file which contains the FPGA bitstream. Specify the chunk size here.
  */
-#define LA2016_EP2_PADDING	2048
+#define LA2016_EP2_PADDING	4096
 
 /*
  * Whether the logic input threshold voltage is a config item of the
@@ -107,12 +107,13 @@
 #define LA2016_CONVBUFFER_SIZE	(4 * 1024 * 1024)
 
 struct kingst_model {
-	uint8_t magic;		/* EEPROM magic byte value. */
+	uint8_t magic, magic2;	/* EEPROM magic byte values. */
 	const char *name;	/* User perceived model name. */
 	const char *fpga_stem;	/* Bitstream filename stem. */
 	uint64_t samplerate;	/* Max samplerate in Hz. */
 	size_t channel_count;	/* Max channel count (16, 32). */
 	uint64_t memory_bits;	/* RAM capacity in Gbit (1, 2, 4). */
+	uint64_t baseclock;	/* Base clock to derive samplerate from. */
 };
 
 struct dev_context {
@@ -120,8 +121,9 @@ struct dev_context {
 	char *mcu_firmware;
 	char *fpga_bitstream;
 	uint64_t fw_uploaded; /* Timestamp of most recent FW upload. */
-	uint8_t identify_magic;
+	uint8_t identify_magic, identify_magic2;
 	const struct kingst_model *model;
+	char **channel_names_logic;
 	struct sr_channel_group *cg_logic, *cg_pwm;
 
 	/* User specified parameters. */