X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fkingst-la2016%2Fprotocol.h;h=371a3ccd8e710255a866ef1907f0b1caad029155;hb=ca98f7ae40259e17c07302d27c3faf0056bfeade;hp=3fdf827932cc62e5744ff7c7551f97a65e57daa4;hpb=69320ad31c261df3e191aeb4c87daed299068661;p=libsigrok.git

diff --git a/src/hardware/kingst-la2016/protocol.h b/src/hardware/kingst-la2016/protocol.h
index 3fdf8279..371a3ccd 100644
--- a/src/hardware/kingst-la2016/protocol.h
+++ b/src/hardware/kingst-la2016/protocol.h
@@ -67,7 +67,7 @@
  * The device expects some zero padding to follow the content of the
  * file which contains the FPGA bitstream. Specify the chunk size here.
  */
-#define LA2016_EP2_PADDING	2048
+#define LA2016_EP2_PADDING	4096
 
 /*
  * Whether the logic input threshold voltage is a config item of the
@@ -81,8 +81,6 @@
 #define LA2016_THR_VOLTAGE_MIN	0.40
 #define LA2016_THR_VOLTAGE_MAX	4.00
 
-/* Properties related to the layout of capture data downloads. */
-#define TRANSFER_PACKET_LENGTH	16
 #define LA2016_NUM_SAMPLES_MAX	(UINT64_C(10 * 1000 * 1000 * 1000))
 
 /* Maximum device capabilities. May differ between models. */
@@ -113,6 +111,7 @@ struct kingst_model {
 	uint64_t samplerate;	/* Max samplerate in Hz. */
 	size_t channel_count;	/* Max channel count (16, 32). */
 	uint64_t memory_bits;	/* RAM capacity in Gbit (1, 2, 4). */
+	uint64_t baseclock;	/* Base clock to derive samplerate from. */
 };
 
 struct dev_context {
@@ -122,6 +121,7 @@ struct dev_context {
 	uint64_t fw_uploaded; /* Timestamp of most recent FW upload. */
 	uint8_t identify_magic, identify_magic2;
 	const struct kingst_model *model;
+	char **channel_names_logic;
 	struct sr_channel_group *cg_logic, *cg_pwm;
 
 	/* User specified parameters. */
@@ -141,6 +141,8 @@ struct dev_context {
 	gboolean frame_begin_sent;
 	gboolean completion_seen;
 	gboolean download_finished;
+	size_t transfer_size;
+	size_t sequence_size;
 	uint32_t packets_per_chunk;
 	struct capture_info {
 		uint32_t n_rep_packets;