X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fkingst-la2016%2Fprotocol.c;h=def77ba40128ce11030bf6cda2714e8dbaaaee85;hb=7047acc8e85b38713450e800037dbcddb1fa98ac;hp=c01bcc33a93d95d28f662db4bdf176dc36854770;hpb=3ab609080d3862dcf64148239e8151c8075fd1b8;p=libsigrok.git diff --git a/src/hardware/kingst-la2016/protocol.c b/src/hardware/kingst-la2016/protocol.c index c01bcc33..def77ba4 100644 --- a/src/hardware/kingst-la2016/protocol.c +++ b/src/hardware/kingst-la2016/protocol.c @@ -1,6 +1,7 @@ /* * This file is part of the libsigrok project. * + * Copyright (C) 2022 Gerhard Sittig * Copyright (C) 2020 Florian Schmidt * Copyright (C) 2013 Marcus Comstedt * Copyright (C) 2013 Bert Vermeulen @@ -86,6 +87,10 @@ static const struct kingst_model models[] = { #define REG_PWM1 0x70 /* Write config for user PWM1. */ #define REG_PWM2 0x78 /* Write config for user PWM2. */ +/* Bit patterns to write to REG_CAPT_MODE. */ +#define CAPTMODE_TO_RAM 0x00 +#define CAPTMODE_STREAM 0x01 + /* Bit patterns to write to REG_RUN, setup run mode. */ #define RUNMODE_HALT 0x00 #define RUNMODE_RUN 0x03 @@ -96,10 +101,6 @@ static const struct kingst_model models[] = { #define RUNSTATE_TRGD_BIT (1UL << 2) #define RUNSTATE_POST_BIT (1UL << 3) -/* Properties related to the layout of capture data downloads. */ -#define NUM_PACKETS_IN_CHUNK 5 -#define TRANSFER_PACKET_LENGTH 16 - static int ctrl_in(const struct sr_dev_inst *sdi, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, void *data, uint16_t wLength) @@ -119,7 +120,7 @@ static int ctrl_in(const struct sr_dev_inst *sdi, libusb_error_name(ret)); sr_err("Cannot read %d bytes from USB: %s.", wLength, libusb_error_name(ret)); - return SR_ERR; + return SR_ERR_IO; } return SR_OK; @@ -144,12 +145,62 @@ static int ctrl_out(const struct sr_dev_inst *sdi, libusb_error_name(ret)); sr_err("Cannot write %d bytes to USB: %s.", wLength, libusb_error_name(ret)); - return SR_ERR; + return SR_ERR_IO; } return SR_OK; } +/* HACK Experiment to spot FPGA registers of interest. */ +static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi, + const char *caption, size_t reg_lower, size_t reg_upper) +{ + static const size_t dump_chunk_len = 16; + + size_t rdlen; + uint8_t rdbuf[0x80 - 0x00]; /* Span all FPGA registers. */ + const uint8_t *rdptr; + int ret; + size_t dump_addr, indent, dump_len; + GString *txt; + + if (sr_log_loglevel_get() < SR_LOG_SPEW) + return; + + if (!reg_lower && !reg_upper) { + reg_lower = 0; + reg_upper = sizeof(rdbuf); + } + if (reg_upper - reg_lower > sizeof(rdbuf)) + reg_upper = sizeof(rdbuf) - reg_lower; + + rdlen = reg_upper - reg_lower; + ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen); + if (ret != SR_OK) { + sr_err("Cannot get registers space."); + return; + } + rdptr = rdbuf; + + sr_spew("FPGA registers dump: %s", caption ? : "for fun"); + dump_addr = reg_lower; + while (rdlen) { + dump_len = rdlen; + indent = dump_addr % dump_chunk_len; + if (dump_len > dump_chunk_len) + dump_len = dump_chunk_len; + if (dump_len + indent > dump_chunk_len) + dump_len = dump_chunk_len - indent; + txt = sr_hexdump_new(rdptr, dump_len); + sr_spew(" %04zx %*s%s", + dump_addr, (int)(3 * indent), "", txt->str); + sr_hexdump_free(txt); + dump_addr += dump_len; + rdptr += dump_len; + rdlen -= dump_len; + } +} + /* * Check the necessity for FPGA bitstream upload, because another upload * would take some 600ms which is undesirable after program startup. Try @@ -177,6 +228,7 @@ static int check_fpga_bitstream(const struct sr_dev_inst *sdi) const uint8_t *rdptr; sr_dbg("Checking operation of the FPGA bitstream."); + la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0); init_rsp = ~0; ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); @@ -270,7 +322,7 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, if (len < 0) { sr_err("Cannot read FPGA bitstream."); sr_resource_close(drvc->sr_ctx, &bitstream); - return SR_ERR; + return SR_ERR_IO; } } else { /* Zero-pad until 'zero_pad_to'. */ @@ -287,13 +339,13 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, if (ret != 0) { sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", pos, (int)len, libusb_error_name(ret)); - ret = SR_ERR; + ret = SR_ERR_IO; break; } if (act_len != len) { sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", pos, (int)len, act_len); - ret = SR_ERR; + ret = SR_ERR_IO; break; } pos += len; @@ -320,7 +372,7 @@ static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) if (resp != 0) { sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", resp); - return SR_ERR; + return SR_ERR_DATA; } g_usleep(30 * 1000); @@ -492,9 +544,9 @@ static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx) return SR_OK; } -static uint16_t get_channels_mask(const struct sr_dev_inst *sdi) +static uint32_t get_channels_mask(const struct sr_dev_inst *sdi) { - uint16_t channels; + uint32_t channels; GSList *l; struct sr_channel *ch; @@ -516,8 +568,8 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) struct dev_context *devc; struct sr_trigger *trigger; struct trigger_cfg { - uint32_t channels; - uint32_t enabled; + uint32_t channels; /* Actually: Enabled channels? */ + uint32_t enabled; /* Actually: Triggering channels? */ uint32_t level; uint32_t high_or_falling; } cfg; @@ -525,7 +577,7 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) GSList *channel; struct sr_trigger_stage *stage1; struct sr_trigger_match *match; - uint16_t ch_mask; + uint32_t ch_mask; int ret; uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */ uint8_t *wrptr; @@ -542,7 +594,7 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) stage1 = stages->data; if (stages->next) { sr_err("Only one trigger stage supported for now."); - return SR_ERR; + return SR_ERR_ARG; } channel = stage1->matches; while (channel) { @@ -561,7 +613,7 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) case SR_TRIGGER_RISING: if ((cfg.enabled & ~cfg.level)) { sr_err("Device only supports one edge trigger."); - return SR_ERR; + return SR_ERR_ARG; } cfg.level &= ~ch_mask; cfg.high_or_falling &= ~ch_mask; @@ -569,21 +621,21 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) case SR_TRIGGER_FALLING: if ((cfg.enabled & ~cfg.level)) { sr_err("Device only supports one edge trigger."); - return SR_ERR; + return SR_ERR_ARG; } cfg.level &= ~ch_mask; cfg.high_or_falling |= ch_mask; break; default: sr_err("Unknown trigger condition."); - return SR_ERR; + return SR_ERR_ARG; } cfg.enabled |= ch_mask; channel = channel->next; } } sr_dbg("Set trigger config: " - "channels 0x%04x, trigger-enabled 0x%04x, " + "enabled-channels 0x%04x, triggering-channels 0x%04x, " "level-triggered 0x%04x, high/falling 0x%04x.", cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); @@ -854,38 +906,39 @@ static int get_capture_info(const struct sr_dev_inst *sdi) devc->info.n_rep_packets_before_trigger, devc->info.write_pos, devc->info.write_pos); - if (devc->info.n_rep_packets % NUM_PACKETS_IN_CHUNK) { - sr_warn("Unexpected packets count %lu, not a multiple of %d.", + if (devc->info.n_rep_packets % devc->packets_per_chunk) { + sr_warn("Unexpected packets count %lu, not a multiple of %lu.", (unsigned long)devc->info.n_rep_packets, - NUM_PACKETS_IN_CHUNK); + (unsigned long)devc->packets_per_chunk); } return SR_OK; } SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi, - struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) + struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload) { struct dev_context *devc; - char *fw_file; + uint16_t pid; + char *fw; int ret; devc = sdi ? sdi->priv : NULL; + if (!devc || !devc->usb_pid) + return SR_ERR_ARG; + pid = devc->usb_pid; - fw_file = g_strdup_printf(MCU_FWFILE_FMT, product_id); - sr_info("USB PID %04hx, MCU firmware '%s'.", product_id, fw_file); + fw = g_strdup_printf(MCU_FWFILE_FMT, pid); + sr_info("USB PID %04hx, MCU firmware '%s'.", pid, fw); + devc->mcu_firmware = g_strdup(fw); - ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file); - if (ret != SR_OK) { - g_free(fw_file); + if (skip_upload) + ret = SR_OK; + else + ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw); + g_free(fw); + if (ret != SR_OK) return ret; - } - - if (devc) { - devc->mcu_firmware = fw_file; - fw_file = NULL; - } - g_free(fw_file); return SR_OK; } @@ -900,7 +953,7 @@ SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi, if (ret != SR_OK) return ret; - cmd = 0; + cmd = CAPTMODE_TO_RAM; ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd)); if (ret != SR_OK) { sr_err("Cannot send command to stop sampling."); @@ -974,8 +1027,10 @@ static int la2016_start_download(const struct sr_dev_inst *sdi, if (ret != SR_OK) return ret; - devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; - devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH; + devc->n_transfer_packets_to_read = devc->info.n_rep_packets; + devc->n_transfer_packets_to_read /= devc->packets_per_chunk; + devc->n_bytes_to_read = devc->n_transfer_packets_to_read; + devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH; devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; @@ -1011,8 +1066,9 @@ static int la2016_start_download(const struct sr_dev_inst *sdi, to_read = devc->n_bytes_to_read; if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */ to_read = LA2016_USB_BUFSZ; - else /* One transfer. */ - to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); + to_read += LA2016_EP6_PKTSZ - 1; + to_read /= LA2016_EP6_PKTSZ; + to_read *= LA2016_EP6_PKTSZ; buffer = g_try_malloc(to_read); if (!buffer) { sr_dbg("USB bulk transfer size %d bytes.", (int)to_read); @@ -1031,7 +1087,7 @@ static int la2016_start_download(const struct sr_dev_inst *sdi, libusb_free_transfer(devc->transfer); devc->transfer = NULL; g_free(buffer); - return SR_ERR; + return SR_ERR_IO; } return SR_OK; @@ -1048,7 +1104,7 @@ static void send_chunk(struct sr_dev_inst *sdi, struct dev_context *devc; size_t num_pkts; const uint8_t *rp; - uint16_t sample_value; + uint32_t sample_value; size_t repetitions; uint8_t sample_buff[sizeof(sample_value)]; @@ -1063,17 +1119,22 @@ static void send_chunk(struct sr_dev_inst *sdi, devc->trigger_marked = TRUE; } + sample_value = 0; rp = packets; while (num_xfers--) { - num_pkts = NUM_PACKETS_IN_CHUNK; + num_pkts = devc->packets_per_chunk; while (num_pkts--) { - sample_value = read_u16le_inc(&rp); + /* TODO Verify 32channel layout. */ + if (devc->model->channel_count == 32) + sample_value = read_u32le_inc(&rp); + else if (devc->model->channel_count == 16) + sample_value = read_u16le_inc(&rp); repetitions = read_u8_inc(&rp); devc->total_samples += repetitions; - write_u16le(sample_buff, sample_value); + write_u32le(sample_buff, sample_value); feed_queue_logic_submit(devc->feed_queue, sample_buff, repetitions); sr_sw_limits_update_samples_read(&devc->sw_limits, @@ -1137,8 +1198,9 @@ static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) */ if (to_read >= LA2016_USB_BUFSZ) to_read = LA2016_USB_BUFSZ; - else - to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); + to_read += LA2016_EP6_PKTSZ - 1; + to_read /= LA2016_EP6_PKTSZ; + to_read *= LA2016_EP6_PKTSZ; libusb_fill_bulk_transfer(transfer, usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, transfer->buffer, to_read, @@ -1192,8 +1254,11 @@ SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) devc->trigger_marked = FALSE; devc->total_samples = 0; + la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0); + /* Initiate the download of acquired sample data. */ std_session_send_df_frame_begin(sdi); + devc->frame_begin_sent = TRUE; ret = la2016_start_download(sdi, receive_transfer); if (ret != SR_OK) { sr_err("Cannot start acquisition data download."); @@ -1219,7 +1284,10 @@ SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) feed_queue_logic_flush(devc->feed_queue); feed_queue_logic_free(devc->feed_queue); devc->feed_queue = NULL; - std_session_send_df_frame_end(sdi); + if (devc->frame_begin_sent) { + std_session_send_df_frame_end(sdi); + devc->frame_begin_sent = FALSE; + } std_session_send_df_end(sdi); sr_dbg("Download finished, done post processing."); @@ -1360,7 +1428,7 @@ SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi, } if (!devc->model) { sr_err("Cannot identify as one of the supported models."); - return SR_ERR; + return SR_ERR_DATA; } return SR_OK; @@ -1391,8 +1459,8 @@ SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi) } state = run_state(sdi); - if (state != 0x85e9) { - sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state); + if ((state & 0xfff0) != 0x85e0) { + sr_warn("Unexpected run state, want 0x85eX, got 0x%04x.", state); } ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);