X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fkingst-la2016%2Fprotocol.c;h=def77ba40128ce11030bf6cda2714e8dbaaaee85;hb=7047acc8e85b38713450e800037dbcddb1fa98ac;hp=2cf67c707cda7ac201f2f81a33636439c2a0eb00;hpb=91aa0f043318df0269bc9247ddaaa1c7785e68d1;p=libsigrok.git

diff --git a/src/hardware/kingst-la2016/protocol.c b/src/hardware/kingst-la2016/protocol.c
index 2cf67c70..def77ba4 100644
--- a/src/hardware/kingst-la2016/protocol.c
+++ b/src/hardware/kingst-la2016/protocol.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the libsigrok project.
  *
+ * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net>
  * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
  * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
@@ -150,6 +151,56 @@ static int ctrl_out(const struct sr_dev_inst *sdi,
 	return SR_OK;
 }
 
+/* HACK Experiment to spot FPGA registers of interest. */
+static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi,
+	const char *caption, size_t reg_lower, size_t reg_upper)
+{
+	static const size_t dump_chunk_len = 16;
+
+	size_t rdlen;
+	uint8_t rdbuf[0x80 - 0x00];	/* Span all FPGA registers. */
+	const uint8_t *rdptr;
+	int ret;
+	size_t dump_addr, indent, dump_len;
+	GString *txt;
+
+	if (sr_log_loglevel_get() < SR_LOG_SPEW)
+		return;
+
+	if (!reg_lower && !reg_upper) {
+		reg_lower = 0;
+		reg_upper = sizeof(rdbuf);
+	}
+	if (reg_upper - reg_lower > sizeof(rdbuf))
+		reg_upper = sizeof(rdbuf) - reg_lower;
+
+	rdlen = reg_upper - reg_lower;
+	ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen);
+	if (ret != SR_OK) {
+		sr_err("Cannot get registers space.");
+		return;
+	}
+	rdptr = rdbuf;
+
+	sr_spew("FPGA registers dump: %s", caption ? : "for fun");
+	dump_addr = reg_lower;
+	while (rdlen) {
+		dump_len = rdlen;
+		indent = dump_addr % dump_chunk_len;
+		if (dump_len > dump_chunk_len)
+			dump_len = dump_chunk_len;
+		if (dump_len + indent > dump_chunk_len)
+			dump_len = dump_chunk_len - indent;
+		txt = sr_hexdump_new(rdptr, dump_len);
+		sr_spew("  %04zx  %*s%s",
+			dump_addr, (int)(3 * indent), "", txt->str);
+		sr_hexdump_free(txt);
+		dump_addr += dump_len;
+		rdptr += dump_len;
+		rdlen -= dump_len;
+	}
+}
+
 /*
  * Check the necessity for FPGA bitstream upload, because another upload
  * would take some 600ms which is undesirable after program startup. Try
@@ -177,6 +228,7 @@ static int check_fpga_bitstream(const struct sr_dev_inst *sdi)
 	const uint8_t *rdptr;
 
 	sr_dbg("Checking operation of the FPGA bitstream.");
+	la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0);
 
 	init_rsp = ~0;
 	ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp));
@@ -1202,6 +1254,8 @@ SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data)
 		devc->trigger_marked = FALSE;
 		devc->total_samples = 0;
 
+		la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0);
+
 		/* Initiate the download of acquired sample data. */
 		std_session_send_df_frame_begin(sdi);
 		devc->frame_begin_sent = TRUE;