X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fkingst-la2016%2Fprotocol.c;h=c3e51722c4156522cd5429373dbbbc889f587943;hb=a7740b06997b4d455428baaa995b777090c3b76e;hp=f3d9bb8f5c3d0f97cb0e5e4a48cee441d69c2aab;hpb=9de389b1979ad69e0a857a97d0e7a144d86d0f61;p=libsigrok.git diff --git a/src/hardware/kingst-la2016/protocol.c b/src/hardware/kingst-la2016/protocol.c index f3d9bb8f..c3e51722 100644 --- a/src/hardware/kingst-la2016/protocol.c +++ b/src/hardware/kingst-la2016/protocol.c @@ -21,35 +21,40 @@ */ #include -#include -#include + +#include #include #include -#include -#include -#include #include #include +#include +#include +#include +#include + #include "libsigrok-internal.h" #include "protocol.h" #define UC_FIRMWARE "kingst-la-%04x.fw" #define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream" #define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream" +#define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream" +#define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream" -#define MAX_SAMPLE_RATE SR_MHZ(200) +#define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200) +#define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100) #define MAX_SAMPLE_DEPTH 10e9 #define MAX_PWM_FREQ SR_MHZ(20) -#define PWM_CLOCK SR_MHZ(200) +#define PWM_CLOCK SR_MHZ(200) /* this is 200MHz for both the LA2016 and LA1016 */ /* usb vendor class control requests to the cypress FX2 microcontroller */ -#define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */ -#define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */ -#define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */ -#define CMD_FPGA_ENABLE 0x10 -#define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */ -#define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */ -#define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */ +#define CMD_FPGA_ENABLE 0x10 +#define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */ +#define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */ +#define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */ +#define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */ +#define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */ +#define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */ /* * fpga spi register addresses for control request CMD_FPGA_SPI: @@ -60,15 +65,15 @@ * as appropriate. In this driver code just use IN transactions * to read, OUT to write. */ -#define REG_RUN 0x00 /* read capture status, write capture start */ -#define REG_PWM_EN 0x02 /* user pwm channels on/off */ -#define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */ -#define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */ -#define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */ -#define REG_TRIGGER 0x20 /* write level and edge trigger config */ -#define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */ -#define REG_PWM1 0x70 /* write config for user pwm1 */ -#define REG_PWM2 0x78 /* write config for user pwm2 */ +#define REG_RUN 0x00 /* read capture status, write capture start */ +#define REG_PWM_EN 0x02 /* user pwm channels on/off */ +#define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */ +#define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */ +#define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */ +#define REG_TRIGGER 0x20 /* write level and edge trigger config */ +#define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */ +#define REG_PWM1 0x70 /* write config for user pwm1 */ +#define REG_PWM2 0x78 /* write config for user pwm2 */ static int ctrl_in(const struct sr_dev_inst *sdi, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, @@ -357,7 +362,7 @@ static int set_defaults(const struct sr_dev_inst *sdi) devc->capture_ratio = 5; /* percent */ devc->cur_channels = 0xffff; devc->limit_samples = 5000000; - devc->cur_samplerate = 200000000; + devc->cur_samplerate = SR_MHZ(100); ret = set_threshold_voltage(sdi, devc->threshold_voltage); if (ret) @@ -482,16 +487,16 @@ static int set_sample_config(const struct sr_dev_inst *sdi) devc = sdi->priv; total = 128 * 1024 * 1024; - if (devc->cur_samplerate > MAX_SAMPLE_RATE) { + if (devc->cur_samplerate > devc->max_samplerate) { sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate); return SR_ERR; } - clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate; + clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; if (clock_divisor > 0xffff) clock_divisor = 0xffff; divisor = (uint16_t)(clock_divisor + 0.5); - devc->cur_samplerate = MAX_SAMPLE_RATE / divisor; + devc->cur_samplerate = devc->max_samplerate / divisor; if (devc->limit_samples > MAX_SAMPLE_DEPTH) { sr_err("too high sample depth: %" PRIu64, devc->limit_samples); @@ -507,7 +512,7 @@ static int set_sample_config(const struct sr_dev_inst *sdi) write_u32le_inc(&wrptr, devc->limit_samples); write_u8_inc(&wrptr, 0); write_u32le_inc(&wrptr, devc->pre_trigger_size); - write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00 ); + write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00); write_u16le_inc(&wrptr, divisor); write_u8_inc(&wrptr, 0); @@ -520,24 +525,58 @@ static int set_sample_config(const struct sr_dev_inst *sdi) return SR_OK; } -/** - * lowest 2 bit are probably: - * 2: recording - * 1: finished - * next 2 bit indicate whether we are still waiting for triggering - * 0: waiting - * 3: triggered +/* The run state is read from FPGA registers 1[hi-byte] and 0[lo-byte] + * and the bits are interpreted as follows: + * + * register 0: + * bit0 1= idle + * bit1 1= writing to sdram + * bit2 0= waiting_for_trigger 1=been_triggered + * bit3 0= pretrigger_sampling 1=posttrigger_sampling + * ...unknown... + * register 1: + * meaning of bits unknown (but vendor software reads this, so just do the same) + * + * The run state values occur in this order: + * 0x85E2: pre-sampling (for samples before trigger position, capture ratio > 0%) + * 0x85EA: pre-sampling complete, now waiting for trigger (whilst sampling continuously) + * 0x85EE: running + * 0x85ED: idle */ static uint16_t run_state(const struct sr_dev_inst *sdi) { uint16_t state; + static uint16_t previous_state = 0; int ret; if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) { sr_err("failed to read run state!"); return ret; } - sr_dbg("run_state: 0x%04x", state); + + /* This function is called about every 50ms. + * To avoid filling the log file with redundant information during long captures, + * just print a log message if status has changed. + */ + + if (state != previous_state) { + previous_state = state; + if ((state & 0x0003) == 0x01) { + sr_dbg("run_state: 0x%04x (%s)", state, "idle"); + } + else if ((state & 0x000f) == 0x02) { + sr_dbg("run_state: 0x%04x (%s)", state, "pre-trigger sampling"); + } + else if ((state & 0x000f) == 0x0a) { + sr_dbg("run_state: 0x%04x (%s)", state, "sampling, waiting for trigger"); + } + else if ((state & 0x000f) == 0x0e) { + sr_dbg("run_state: 0x%04x (%s)", state, "post-trigger sampling"); + } + else { + sr_dbg("run_state: 0x%04x", state); + } + } return state; } @@ -622,20 +661,43 @@ SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) { - return set_run_mode(sdi, 3); + int ret; + + ret = set_run_mode(sdi, 3); + if (ret != SR_OK) + return ret; + + return SR_OK; } -SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi) +static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) { - return set_run_mode(sdi, 0); + int ret; + + ret = set_run_mode(sdi, 0); + if (ret != SR_OK) + return ret; + + return SR_OK; } SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) { - return la2016_stop_acquisition(sdi); + int ret; + struct dev_context *devc; + + ret = la2016_stop_acquisition(sdi); + if (ret != SR_OK) + return ret; + + devc = sdi ? sdi->priv : NULL; + if (devc && devc->transfer) + libusb_cancel_transfer(devc->transfer); + + return SR_OK; } -SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi) +static int la2016_has_triggered(const struct sr_dev_inst *sdi) { uint16_t state; @@ -644,7 +706,7 @@ SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi) return (state & 0x3) == 1; } -SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) +static int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) { struct dev_context *devc; struct sr_usb_dev_inst *usb; @@ -686,9 +748,11 @@ SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfe } to_read = devc->n_bytes_to_read; - if (to_read > LA2016_BULK_MAX) - to_read = LA2016_BULK_MAX; - + /* choose a buffer size for all of the usb transfers */ + if (to_read >= LA2016_USB_BUFSZ) + to_read = LA2016_USB_BUFSZ; /* multiple transfers */ + else /* one transfer, make buffer size some multiple of LA2016_EP6_PKTSZ */ + to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); buffer = g_try_malloc(to_read); if (!buffer) { sr_err("Failed to allocate %d bytes for bulk transfer", to_read); @@ -712,14 +776,196 @@ SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfe return SR_OK; } +static void send_chunk(struct sr_dev_inst *sdi, + const uint8_t *packets, unsigned int num_tfers) +{ + struct dev_context *devc; + struct sr_datafeed_logic logic; + struct sr_datafeed_packet sr_packet; + unsigned int max_samples, n_samples, total_samples, free_n_samples; + unsigned int i, j, k; + int do_signal_trigger; + uint16_t *wp; + const uint8_t *rp; + uint16_t state; + uint8_t repetitions; + + devc = sdi->priv; + + logic.unitsize = 2; + logic.data = devc->convbuffer; + + sr_packet.type = SR_DF_LOGIC; + sr_packet.payload = &logic; + + max_samples = devc->convbuffer_size / 2; + n_samples = 0; + wp = (uint16_t *)devc->convbuffer; + total_samples = 0; + do_signal_trigger = 0; + + if (devc->had_triggers_configured && devc->reading_behind_trigger == 0 && devc->info.n_rep_packets_before_trigger == 0) { + std_session_send_df_trigger(sdi); + devc->reading_behind_trigger = 1; + } + + rp = packets; + for (i = 0; i < num_tfers; i++) { + for (k = 0; k < NUM_PACKETS_IN_CHUNK; k++) { + free_n_samples = max_samples - n_samples; + if (free_n_samples < 256 || do_signal_trigger) { + logic.length = n_samples * 2; + sr_session_send(sdi, &sr_packet); + n_samples = 0; + wp = (uint16_t *)devc->convbuffer; + if (do_signal_trigger) { + std_session_send_df_trigger(sdi); + do_signal_trigger = 0; + } + } + + state = read_u16le_inc(&rp); + repetitions = read_u8_inc(&rp); + for (j = 0; j < repetitions; j++) + *wp++ = state; + + n_samples += repetitions; + total_samples += repetitions; + devc->total_samples += repetitions; + if (!devc->reading_behind_trigger) { + devc->n_reps_until_trigger--; + if (devc->n_reps_until_trigger == 0) { + devc->reading_behind_trigger = 1; + do_signal_trigger = 1; + sr_dbg(" here is trigger position after %" PRIu64 " samples, %.6fms", + devc->total_samples, + (double)devc->total_samples / devc->cur_samplerate * 1e3); + } + } + } + (void)read_u8_inc(&rp); /* Skip sequence number. */ + } + if (n_samples) { + logic.length = n_samples * 2; + sr_session_send(sdi, &sr_packet); + if (do_signal_trigger) { + std_session_send_df_trigger(sdi); + } + } + sr_dbg("send_chunk done after %d samples", total_samples); +} + +static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) +{ + struct sr_dev_inst *sdi; + struct dev_context *devc; + struct sr_usb_dev_inst *usb; + int ret; + + sdi = transfer->user_data; + devc = sdi->priv; + usb = sdi->conn; + + sr_dbg("receive_transfer(): status %s received %d bytes.", + libusb_error_name(transfer->status), transfer->actual_length); + + if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) { + sr_err("bulk transfer timeout!"); + devc->transfer_finished = 1; + } + send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH); + + devc->n_bytes_to_read -= transfer->actual_length; + if (devc->n_bytes_to_read) { + uint32_t to_read = devc->n_bytes_to_read; + /* determine read size for the next usb transfer */ + if (to_read >= LA2016_USB_BUFSZ) + to_read = LA2016_USB_BUFSZ; + else /* last transfer, make read size some multiple of LA2016_EP6_PKTSZ */ + to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); + libusb_fill_bulk_transfer( + transfer, usb->devhdl, + 0x86, transfer->buffer, to_read, + receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); + + if ((ret = libusb_submit_transfer(transfer)) == 0) + return; + sr_err("Failed to submit further transfer: %s.", libusb_error_name(ret)); + } + + g_free(transfer->buffer); + libusb_free_transfer(transfer); + devc->transfer_finished = 1; +} + +SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) +{ + const struct sr_dev_inst *sdi; + struct dev_context *devc; + struct drv_context *drvc; + struct timeval tv; + + (void)fd; + (void)revents; + + sdi = cb_data; + devc = sdi->priv; + drvc = sdi->driver->context; + + if (devc->have_trigger == 0) { + if (la2016_has_triggered(sdi) == 0) { + /* not yet ready for download */ + return TRUE; + } + devc->have_trigger = 1; + devc->transfer_finished = 0; + devc->reading_behind_trigger = 0; + devc->total_samples = 0; + /* we can start retrieving data! */ + if (la2016_start_retrieval(sdi, receive_transfer) != SR_OK) { + sr_err("failed to start retrieval!"); + return FALSE; + } + sr_dbg("retrieval is started..."); + std_session_send_df_frame_begin(sdi); + + return TRUE; + } + + tv.tv_sec = tv.tv_usec = 0; + libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); + + if (devc->transfer_finished) { + sr_dbg("transfer is finished!"); + std_session_send_df_frame_end(sdi); + + usb_source_remove(sdi->session, drvc->sr_ctx); + std_session_send_df_end(sdi); + + la2016_stop_acquisition(sdi); + + g_free(devc->convbuffer); + devc->convbuffer = NULL; + + devc->transfer = NULL; + + sr_dbg("transfer is now finished"); + } + + return TRUE; +} + SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) { + struct dev_context *devc; uint16_t state; uint8_t buf[8]; int16_t purchase_date_bcd[2]; uint8_t magic; int ret; + devc = sdi->priv; + /* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit * complemented checksum; e.g. 2004DFFB = 2020-April. * This helps to identify the age of devices if unknown magic numbers occur. @@ -729,7 +975,7 @@ SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) } else { sr_dbg("purchase date: 20%02hx-%02hx", (purchase_date_bcd[0]) & 0x00ff, (purchase_date_bcd[0] >> 8) & 0x00ff); - if( purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1]) ) { + if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) { sr_err("purchase date: checksum failure"); } } @@ -789,12 +1035,22 @@ SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) switch (magic) { case 2: ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016); + devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; + break; + case 3: + ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016); + devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; break; case 8: ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A); + devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; + break; + case 9: + ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016A); + devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; break; default: - sr_err("device_type: device not supported; magic number indicates this is not an LA2016"); + sr_err("device_type: device not supported; magic number indicates this is not a LA2016 or LA1016"); return SR_ERR; }