X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fkingst-la2016%2Fprotocol.c;h=a0de3be70c0982ea5bc7525a49069dfdc13bab39;hb=b0d0131eff8bacbf69aa0da818efaa4439f19a64;hp=f0d23e3130043b5a97dd82d57cd48121a6f87a7a;hpb=00849545026926298b68aa8eae76ae76310f8f9e;p=libsigrok.git diff --git a/src/hardware/kingst-la2016/protocol.c b/src/hardware/kingst-la2016/protocol.c index f0d23e31..a0de3be7 100644 --- a/src/hardware/kingst-la2016/protocol.c +++ b/src/hardware/kingst-la2016/protocol.c @@ -21,48 +21,64 @@ */ #include -#include -#include -#include -#include -#include -#include -#include -#include + #include +#include + #include "libsigrok-internal.h" #include "protocol.h" -#define FPGA_FIRMWARE "kingst-la2016a-fpga.bitstream" #define UC_FIRMWARE "kingst-la-%04x.fw" +#define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream" +#define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream" +#define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream" +#define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream" + +#define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200) +#define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100) +#define MAX_SAMPLE_DEPTH 10e9 +#define MAX_PWM_FREQ SR_MHZ(20) +#define PWM_CLOCK SR_MHZ(200) /* 200MHz for both LA2016 and LA1016 */ + +/* USB vendor class control requests, executed by the Cypress FX2 MCU. */ +#define CMD_FPGA_ENABLE 0x10 +#define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ +#define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ +#define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ +#define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ +#define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ +#define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ -#define MAX_SAMPLE_RATE SR_MHZ(200) -#define MAX_SAMPLE_DEPTH 10e9 -#define MAX_PWM_FREQ SR_MHZ(20) -#define PWM_CLOCK SR_MHZ(200) - -/* usb vendor class control requests to the cypress FX2 microcontroller */ -#define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */ -#define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */ -#define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */ -#define CMD_FPGA_ENABLE 0x10 -#define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */ -#define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */ -#define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */ - -/* registers for control request 32: */ -#define CTRL_RUN 0x00 -#define CTRL_PWM_EN 0x02 -#define CTRL_BULK 0x10 /* can be read to get 12 byte sampling_info (III) */ -#define CTRL_SAMPLING 0x20 -#define CTRL_TRIGGER 0x30 -#define CTRL_THRESHOLD 0x48 -#define CTRL_PWM1 0x70 -#define CTRL_PWM2 0x78 +/* + * FPGA register addresses (base addresses when registers span multiple + * bytes, in that case data is kept in little endian format). Passed to + * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail + * of SPI transfers encoding the read (1) or write (0) direction in the + * MSB of the address field. There are some 60 byte-wide FPGA registers. + * + * Unfortunately the FPGA registers change their meaning between the + * read and write directions of access, or exclusively provide one of + * these directions and not the other. This is an arbitrary vendor's + * choice, there is nothing which the sigrok driver could do about it. + * Values written to registers typically cannot get read back, neither + * verified after writing a configuration, nor queried upon startup for + * automatic detection of the current configuration. Neither appear to + * be there echo registers for presence and communication checks, nor + * version identifying registers, as far as we know. + */ +#define REG_RUN 0x00 /* Read capture status, write start capture. */ +#define REG_PWM_EN 0x02 /* User PWM channels on/off. */ +#define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ +#define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ +#define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ +#define REG_TRIGGER 0x20 /* write level and edge trigger config. */ +#define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ +#define REG_PWM1 0x70 /* Write config for user PWM1. */ +#define REG_PWM2 0x78 /* Write config for user PWM2. */ static int ctrl_in(const struct sr_dev_inst *sdi, - uint8_t bRequest, uint16_t wValue, uint16_t wIndex, - void *data, uint16_t wLength) + uint8_t bRequest, uint16_t wValue, uint16_t wIndex, + void *data, uint16_t wLength) { struct sr_usb_dev_inst *usb; int ret; @@ -73,9 +89,11 @@ static int ctrl_in(const struct sr_dev_inst *sdi, usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, bRequest, wValue, wIndex, (unsigned char *)data, wLength, DEFAULT_TIMEOUT_MS)) != wLength) { - sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.", - wLength, bRequest, wValue, wIndex, - libusb_error_name(ret)); + sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", + wLength, bRequest, wValue, wIndex, + libusb_error_name(ret)); + sr_err("Cannot read %d bytes from USB: %s.", + wLength, libusb_error_name(ret)); return SR_ERR; } @@ -83,8 +101,8 @@ static int ctrl_in(const struct sr_dev_inst *sdi, } static int ctrl_out(const struct sr_dev_inst *sdi, - uint8_t bRequest, uint16_t wValue, uint16_t wIndex, - void *data, uint16_t wLength) + uint8_t bRequest, uint16_t wValue, uint16_t wIndex, + void *data, uint16_t wLength) { struct sr_usb_dev_inst *usb; int ret; @@ -95,62 +113,138 @@ static int ctrl_out(const struct sr_dev_inst *sdi, usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, bRequest, wValue, wIndex, (unsigned char*)data, wLength, DEFAULT_TIMEOUT_MS)) != wLength) { - sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.", - wLength, bRequest, wValue, wIndex, - libusb_error_name(ret)); + sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", + wLength, bRequest, wValue, wIndex, + libusb_error_name(ret)); + sr_err("Cannot write %d bytes to USB: %s.", + wLength, libusb_error_name(ret)); return SR_ERR; } return SR_OK; } -static int upload_fpga_bitstream(const struct sr_dev_inst *sdi) +/* + * Check the necessity for FPGA bitstream upload, because another upload + * would take some 600ms which is undesirable after program startup. Try + * to access some FPGA registers and check the values' plausibility. The + * check should fail on the safe side, request another upload when in + * doubt. A positive response (the request to continue operation with the + * currently active bitstream) should be conservative. Accessing multiple + * registers is considered cheap compared to the cost of bitstream upload. + * + * It helps though that both the vendor software and the sigrok driver + * use the same bundle of MCU firmware and FPGA bitstream for any of the + * supported models. We don't expect to successfully communicate to the + * device yet disagree on its protocol. Ideally we would access version + * identifying registers for improved robustness, but are not aware of + * any. A bitstream reload can always be forced by a power cycle. + */ +static int check_fpga_bitstream(const struct sr_dev_inst *sdi) +{ + uint8_t init_rsp; + int ret; + uint16_t run_state; + uint8_t pwm_en; + size_t read_len; + uint8_t buff[sizeof(run_state)]; + const uint8_t *rdptr; + + sr_dbg("Checking operation of the FPGA bitstream."); + + init_rsp = 0xff; + ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); + if (ret != SR_OK || init_rsp != 0) { + sr_dbg("FPGA init query failed, or unexpected response."); + return SR_ERR_IO; + } + + read_len = sizeof(run_state); + ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); + if (ret != SR_OK) { + sr_dbg("FPGA register access failed (run state)."); + return SR_ERR_IO; + } + rdptr = buff; + run_state = read_u16le_inc(&rdptr); + sr_spew("FPGA register: run state 0x%04x.", run_state); + if (run_state && (run_state & 0x3) != 0x1) { + sr_dbg("Unexpected FPGA register content (run state)."); + return SR_ERR_DATA; + } + if (run_state && (run_state & ~0xf) != 0x85e0) { + sr_dbg("Unexpected FPGA register content (run state)."); + return SR_ERR_DATA; + } + + read_len = sizeof(pwm_en); + ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); + if (ret != SR_OK) { + sr_dbg("FPGA register access failed (PWM enable)."); + return SR_ERR_IO; + } + rdptr = buff; + pwm_en = read_u8_inc(&rdptr); + sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); + if ((pwm_en & 0x3) != 0x0) { + sr_dbg("Unexpected FPGA register content (PWM enable)."); + return SR_ERR_DATA; + } + + sr_info("Could re-use current FPGA bitstream. No upload required."); + return SR_OK; +} + +static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, + const char *bitstream_fname) { - struct dev_context *devc; struct drv_context *drvc; struct sr_usb_dev_inst *usb; struct sr_resource bitstream; + uint32_t bitstream_size; uint8_t buffer[sizeof(uint32_t)]; uint8_t *wrptr; - uint8_t cmd_resp; uint8_t block[4096]; int len, act_len; unsigned int pos; int ret; - unsigned int zero_pad_to = 0x2c000; + unsigned int zero_pad_to; - devc = sdi->priv; drvc = sdi->driver->context; usb = sdi->conn; - sr_info("Uploading FPGA bitstream '%s'.", FPGA_FIRMWARE); + sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); - ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, FPGA_FIRMWARE); + ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname); if (ret != SR_OK) { - sr_err("could not find la2016 firmware %s!", FPGA_FIRMWARE); + sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); return ret; } - devc->bitstream_size = (uint32_t)bitstream.size; + bitstream_size = (uint32_t)bitstream.size; wrptr = buffer; - write_u32le_inc(&wrptr, devc->bitstream_size); + write_u32le_inc(&wrptr, bitstream_size); if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) { - sr_err("failed to give upload init command"); + sr_err("Cannot initiate FPGA bitstream upload."); sr_resource_close(drvc->sr_ctx, &bitstream); return ret; } + zero_pad_to = bitstream_size; + zero_pad_to += LA2016_EP2_PADDING - 1; + zero_pad_to /= LA2016_EP2_PADDING; + zero_pad_to *= LA2016_EP2_PADDING; pos = 0; while (1) { if (pos < bitstream.size) { len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block)); if (len < 0) { - sr_err("failed to read from fpga bitstream!"); + sr_err("Cannot read FPGA bitstream."); sr_resource_close(drvc->sr_ctx, &bitstream); return SR_ERR; } } else { - // fill with zero's until zero_pad_to + /* Zero-pad until 'zero_pad_to'. */ len = zero_pad_to - pos; if ((unsigned)len > sizeof(block)) len = sizeof(block); @@ -159,14 +253,17 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi) if (len == 0) break; - ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS); + ret = libusb_bulk_transfer(usb->devhdl, 2, + &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); if (ret != 0) { - sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret)); + sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", + pos, (int)len, libusb_error_name(ret)); ret = SR_ERR; break; } if (act_len != len) { - sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len); + sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", + pos, (int)len, act_len); ret = SR_ERR; break; } @@ -175,51 +272,94 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi) sr_resource_close(drvc->sr_ctx, &bitstream); if (ret != 0) return ret; - sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size); + sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", + bitstream.size); + + return SR_OK; +} + +static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) +{ + int ret; + uint8_t cmd_resp; if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) { - sr_err("failed to read response after FPGA bitstream upload"); + sr_err("Cannot read response after FPGA bitstream upload."); return ret; } if (cmd_resp != 0) { - sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp); + sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", + cmd_resp); return SR_ERR; } - g_usleep(30000); if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) { - sr_err("failed enable fpga"); + sr_err("Cannot enable FPGA after bitstream upload."); return ret; } - g_usleep(40000); + return SR_OK; } static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) { struct dev_context *devc; - float o1, o2, v1, v2, f; - uint32_t cfgval; - uint8_t buffer[sizeof(uint32_t)]; - uint8_t *wrptr; int ret; devc = sdi->priv; - o1 = 15859969; v1 = 0.45; - o2 = 15860333; v2 = 1.65; - f = (o2 - o1) / (v2 - v1); - cfgval = (uint32_t)(o1 + (voltage - v1) * f); - sr_dbg("set threshold voltage %.2fV, raw value 0x%lx", - voltage, (unsigned long)cfgval); - wrptr = buffer; - write_u32le_inc(&wrptr, cfgval); - ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_THRESHOLD, 0, buffer, wrptr - buffer); + uint16_t duty_R79, duty_R56; + uint8_t buf[2 * sizeof(uint16_t)]; + uint8_t *wrptr; + + /* Clamp threshold setting to valid range for LA2016. */ + if (voltage > 4.0) { + voltage = 4.0; + } else if (voltage < -4.0) { + voltage = -4.0; + } + + /* + * Two PWM output channels feed one DAC which generates a bias + * voltage, which offsets the input probe's voltage level, and + * in combination with the FPGA pins' fixed threshold result in + * a programmable input threshold from the user's perspective. + * The PWM outputs can be seen on R79 and R56 respectively, the + * frequency is 100kHz and the duty cycle varies. The R79 PWM + * uses three discrete settings. The R56 PWM varies with desired + * thresholds and depends on the R79 PWM configuration. See the + * schematics comments which discuss the formulae. + */ + if (voltage >= 2.9) { + duty_R79 = 0; /* PWM off (0V). */ + duty_R56 = (uint16_t)(302 * voltage - 363); + } else if (voltage <= -0.4) { + duty_R79 = 0x02d7; /* 72% duty cycle. */ + duty_R56 = (uint16_t)(302 * voltage + 1090); + } else { + duty_R79 = 0x00f2; /* 25% duty cycle. */ + duty_R56 = (uint16_t)(302 * voltage + 121); + } + + /* Clamp duty register values to sensible limits. */ + if (duty_R56 < 10) { + duty_R56 = 10; + } else if (duty_R56 > 1100) { + duty_R56 = 1100; + } + + sr_dbg("Set threshold voltage %.2fV.", voltage); + sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); + + wrptr = buf; + write_u16le_inc(&wrptr, duty_R56); + write_u16le_inc(&wrptr, duty_R79); + + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); if (ret != SR_OK) { - sr_err("Error setting %.2fV threshold voltage (%d)", - voltage, ret); + sr_err("Cannot set threshold voltage %.2fV.", voltage); return ret; } devc->threshold_voltage = voltage; @@ -239,10 +379,10 @@ static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) if (p1) cfg |= 1 << 0; if (p2) cfg |= 1 << 1; - sr_dbg("set pwm enable %d %d", p1, p2); - ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM_EN, 0, &cfg, sizeof(cfg)); + sr_dbg("Set PWM enable %d %d. Config 0x%02x.", p1, p2, cfg); + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); if (ret != SR_OK) { - sr_err("error setting new pwm enable 0x%02x", cfg); + sr_err("Cannot setup PWM enabled state."); return ret; } devc->pwm_setting[0].enabled = (p1) ? 1 : 0; @@ -251,9 +391,10 @@ static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) return SR_OK; } -static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty) +static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, + float freq, float duty) { - int CTRL_PWM[] = { CTRL_PWM1, CTRL_PWM2 }; + int CTRL_PWM[] = { REG_PWM1, REG_PWM2 }; struct dev_context *devc; pwm_setting_dev_t cfg; pwm_setting_t *setting; @@ -264,28 +405,29 @@ static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, flo devc = sdi->priv; if (which < 1 || which > 2) { - sr_err("invalid pwm channel: %d", which); + sr_err("Invalid PWM channel: %d.", which); return SR_ERR; } if (freq > MAX_PWM_FREQ) { - sr_err("pwm frequency too high: %.1f", freq); + sr_err("Too high a PWM frequency: %.1f.", freq); return SR_ERR; } if (duty > 100 || duty < 0) { - sr_err("invalid pwm percentage: %f", duty); + sr_err("Invalid PWM duty cycle: %f.", duty); return SR_ERR; } cfg.period = (uint32_t)(PWM_CLOCK / freq); cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); - sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty); + sr_dbg("Set PWM%d period %d, duty %d.", which, cfg.period, cfg.duty); wrptr = buf; write_u32le_inc(&wrptr, cfg.period); write_u32le_inc(&wrptr, cfg.duty); ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf); if (ret != SR_OK) { - sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty); + sr_err("Cannot setup PWM%d configuration %d %d.", + which, cfg.period, cfg.duty); return ret; } setting = &devc->pwm_setting[which - 1]; @@ -305,7 +447,7 @@ static int set_defaults(const struct sr_dev_inst *sdi) devc->capture_ratio = 5; /* percent */ devc->cur_channels = 0xffff; devc->limit_samples = 5000000; - devc->cur_samplerate = 200000000; + devc->cur_samplerate = SR_MHZ(100); ret = set_threshold_voltage(sdi, devc->threshold_voltage); if (ret) @@ -374,7 +516,7 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) break; case SR_TRIGGER_RISING: if ((cfg.enabled & ~cfg.level)) { - sr_err("Only one trigger signal with falling-/rising-edge allowed."); + sr_err("Device only supports one edge trigger."); return SR_ERR; } cfg.level &= ~ch_mask; @@ -382,24 +524,24 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) break; case SR_TRIGGER_FALLING: if ((cfg.enabled & ~cfg.level)) { - sr_err("Only one trigger signal with falling-/rising-edge allowed."); + sr_err("Device only supports one edge trigger."); return SR_ERR; } cfg.level &= ~ch_mask; cfg.high_or_falling |= ch_mask; break; default: - sr_err("Unknown trigger value."); + sr_err("Unknown trigger condition."); return SR_ERR; } cfg.enabled |= ch_mask; channel = channel->next; } } - sr_dbg("set trigger configuration channels: 0x%04x, " - "trigger-enabled 0x%04x, level-triggered 0x%04x, " - "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level, - cfg.high_or_falling); + sr_dbg("Set trigger config: " + "channels 0x%04x, trigger-enabled 0x%04x, " + "level-triggered 0x%04x, high/falling 0x%04x.", + cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); devc->had_triggers_configured = cfg.enabled != 0; @@ -408,9 +550,9 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) write_u32le_inc(&wrptr, cfg.enabled); write_u32le_inc(&wrptr, cfg.level); write_u32le_inc(&wrptr, cfg.high_or_falling); - ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_TRIGGER, 16, buf, wrptr - buf); + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); if (ret != SR_OK) { - sr_err("error setting trigger config!"); + sr_err("Cannot setup trigger configuration."); return ret; } @@ -421,7 +563,6 @@ static int set_sample_config(const struct sr_dev_inst *sdi) { struct dev_context *devc; double clock_divisor; - uint64_t psa; uint64_t total; int ret; uint16_t divisor; @@ -431,61 +572,97 @@ static int set_sample_config(const struct sr_dev_inst *sdi) devc = sdi->priv; total = 128 * 1024 * 1024; - if (devc->cur_samplerate > MAX_SAMPLE_RATE) { - sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate); + if (devc->cur_samplerate > devc->max_samplerate) { + sr_err("Too high a sample rate: %" PRIu64 ".", + devc->cur_samplerate); return SR_ERR; } - clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate; + clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; if (clock_divisor > 0xffff) clock_divisor = 0xffff; divisor = (uint16_t)(clock_divisor + 0.5); - devc->cur_samplerate = MAX_SAMPLE_RATE / divisor; + devc->cur_samplerate = devc->max_samplerate / divisor; if (devc->limit_samples > MAX_SAMPLE_DEPTH) { - sr_err("too high sample depth: %" PRIu64, devc->limit_samples); + sr_err("Too high a sample depth: %" PRIu64 ".", + devc->limit_samples); return SR_ERR; } devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100; - sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%", - devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio); + sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples, trigger-pos %" PRIu64 "%%.", + devc->cur_samplerate / 1000, + devc->limit_samples, + devc->capture_ratio); - psa = devc->pre_trigger_size * 256; wrptr = buf; write_u32le_inc(&wrptr, devc->limit_samples); - write_u48le_inc(&wrptr, psa); - write_u32le_inc(&wrptr, (total * devc->capture_ratio) / 100); - write_u16le_inc(&wrptr, clock_divisor); + write_u8_inc(&wrptr, 0); + write_u32le_inc(&wrptr, devc->pre_trigger_size); + write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xffffff00); + write_u16le_inc(&wrptr, divisor); + write_u8_inc(&wrptr, 0); - ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_SAMPLING, 0, buf, wrptr - buf); + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); if (ret != SR_OK) { - sr_err("error setting sample config!"); + sr_err("Cannot setup acquisition configuration."); return ret; } return SR_OK; } -/** - * lowest 2 bit are probably: - * 2: recording - * 1: finished - * next 2 bit indicate whether we are still waiting for triggering - * 0: waiting - * 3: triggered +/* + * FPGA register REG_RUN holds the run state (u16le format). Bit fields + * of interest: + * bit 0: value 1 = idle + * bit 1: value 1 = writing to SDRAM + * bit 2: value 0 = waiting for trigger, 1 = trigger seen + * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling + * The meaning of other bit fields is unknown. + * + * Typical values in order of appearance during execution: + * 0x85e2: pre-sampling, samples before the trigger position, + * when capture ratio > 0% + * 0x85ea: pre-sampling complete, now waiting for the trigger + * (whilst sampling continuously) + * 0x85ee: trigger seen, capturing post-trigger samples, running + * 0x85ed: idle */ static uint16_t run_state(const struct sr_dev_inst *sdi) { uint16_t state; + static uint16_t previous_state = 0; int ret; - if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, CTRL_RUN, 0, &state, sizeof(state))) != SR_OK) { - sr_err("failed to read run state!"); + if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) { + sr_err("Cannot read run state."); return ret; } - sr_dbg("run_state: 0x%04x", state); + + /* + * Avoid flooding the log, only dump values as they change. + * The routine is called about every 50ms. + */ + if (state != previous_state) { + previous_state = state; + if ((state & 0x0003) == 0x01) { + sr_dbg("Run state: 0x%04x (%s).", state, "idle"); + } else if ((state & 0x000f) == 0x02) { + sr_dbg("Run state: 0x%04x (%s).", state, + "pre-trigger sampling"); + } else if ((state & 0x000f) == 0x0a) { + sr_dbg("Run state: 0x%04x (%s).", state, + "sampling, waiting for trigger"); + } else if ((state & 0x000f) == 0x0e) { + sr_dbg("Run state: 0x%04x (%s).", state, + "post-trigger sampling"); + } else { + sr_dbg("Run state: 0x%04x.", state); + } + } return state; } @@ -494,8 +671,8 @@ static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking) { int ret; - if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) { - sr_err("failed to send set-run-mode command %d", fast_blinking); + if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) { + sr_err("Cannot configure run mode %d.", fast_blinking); return ret; } @@ -511,8 +688,8 @@ static int get_capture_info(const struct sr_dev_inst *sdi) devc = sdi->priv; - if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, CTRL_BULK, 0, buf, sizeof(buf))) != SR_OK) { - sr_err("failed to read capture info!"); + if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) { + sr_err("Cannot read capture info."); return ret; } @@ -521,18 +698,22 @@ static int get_capture_info(const struct sr_dev_inst *sdi) devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); devc->info.write_pos = read_u32le_inc(&rdptr); - sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d", - devc->info.n_rep_packets, devc->info.n_rep_packets, - devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger, - devc->info.write_pos, devc->info.write_pos); + sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d.", + devc->info.n_rep_packets, devc->info.n_rep_packets, + devc->info.n_rep_packets_before_trigger, + devc->info.n_rep_packets_before_trigger, + devc->info.write_pos, devc->info.write_pos); - if (devc->info.n_rep_packets % 5) - sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets); + if (devc->info.n_rep_packets % 5) { + sr_warn("Unexpected packets count %lu, not a multiple of 5.", + (unsigned long)devc->info.n_rep_packets); + } return SR_OK; } -SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) +SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, + libusb_device *dev, uint16_t product_id) { char fw_file[1024]; snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id); @@ -552,8 +733,8 @@ SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) return ret; cmd = 0; - if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, 0x03, 0, &cmd, sizeof(cmd))) != SR_OK) { - sr_err("failed to send stop sampling command"); + if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) { + sr_err("Cannot send command to stop sampling."); return ret; } @@ -570,20 +751,43 @@ SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) { - return set_run_mode(sdi, 3); + int ret; + + ret = set_run_mode(sdi, 3); + if (ret != SR_OK) + return ret; + + return SR_OK; } -SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi) +static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) { - return set_run_mode(sdi, 0); + int ret; + + ret = set_run_mode(sdi, 0); + if (ret != SR_OK) + return ret; + + return SR_OK; } SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) { - return la2016_stop_acquisition(sdi); + int ret; + struct dev_context *devc; + + ret = la2016_stop_acquisition(sdi); + if (ret != SR_OK) + return ret; + + devc = sdi ? sdi->priv : NULL; + if (devc && devc->transfer) + libusb_cancel_transfer(devc->transfer); + + return SR_OK; } -SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi) +static int la2016_has_triggered(const struct sr_dev_inst *sdi) { uint16_t state; @@ -592,7 +796,8 @@ SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi) return (state & 0x3) == 1; } -SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) +static int la2016_start_retrieval(const struct sr_dev_inst *sdi, + libusb_transfer_cb_fn cb) { struct dev_context *devc; struct sr_usb_dev_inst *usb; @@ -613,33 +818,41 @@ SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfe devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; - sr_dbg("want to read %d tfer-packets starting from pos %d", - devc->n_transfer_packets_to_read, devc->read_pos); + sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", + devc->n_transfer_packets_to_read, devc->read_pos); if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { - sr_err("failed to reset bulk state"); + sr_err("Cannot reset USB bulk state."); return ret; } - sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read); + sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", + (unsigned long)devc->read_pos, devc->n_bytes_to_read); wrptr = wrbuf; write_u32le_inc(&wrptr, devc->read_pos); write_u32le_inc(&wrptr, devc->n_bytes_to_read); - if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) { - sr_err("failed to send bulk config"); + if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) { + sr_err("Cannot send USB bulk config."); return ret; } if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) { - sr_err("failed to unblock bulk transfers"); + sr_err("Cannot unblock USB bulk transfers."); return ret; } + /* + * Pick a buffer size for all USB transfers. The buffer size + * must be a multiple of the endpoint packet size. And cannot + * exceed a maximum value. + */ to_read = devc->n_bytes_to_read; - if (to_read > LA2016_BULK_MAX) - to_read = LA2016_BULK_MAX; - + if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */ + to_read = LA2016_USB_BUFSZ; + else /* One transfer. */ + to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); buffer = g_try_malloc(to_read); if (!buffer) { - sr_err("Failed to allocate %d bytes for bulk transfer", to_read); + sr_dbg("USB bulk transfer size %d bytes.", (int)to_read); + sr_err("Cannot allocate buffer for USB bulk transfer."); return SR_ERR_MALLOC; } @@ -650,7 +863,7 @@ SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfe cb, (void *)sdi, DEFAULT_TIMEOUT_MS); if ((ret = libusb_submit_transfer(devc->transfer)) != 0) { - sr_err("Failed to submit transfer: %s.", libusb_error_name(ret)); + sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret)); libusb_free_transfer(devc->transfer); devc->transfer = NULL; g_free(buffer); @@ -660,95 +873,325 @@ SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfe return SR_OK; } -SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) +static void send_chunk(struct sr_dev_inst *sdi, + const uint8_t *packets, unsigned int num_tfers) { struct dev_context *devc; - int ret; - uint32_t i1; - uint32_t i2[2]; + struct sr_datafeed_logic logic; + struct sr_datafeed_packet sr_packet; + unsigned int max_samples, n_samples, total_samples, free_n_samples; + unsigned int i, j, k; + int do_signal_trigger; + uint16_t *wp; + const uint8_t *rp; uint16_t state; + uint8_t repetitions; - /* this unknown_cmd1 seems to depend on the FPGA bitstream */ - uint8_t unknown_cmd1_340[] = { 0xa3, 0x09, 0xc9, 0x8d, 0xe7, 0xad, 0x7a, 0x62, 0xb6, 0xd1, 0xbf }; - uint8_t unknown_cmd1_342[] = { 0xa3, 0x09, 0xc9, 0xf4, 0x32, 0x4c, 0x4d, 0xee, 0xab, 0xa0, 0xdd }; - uint8_t expected_unknown_resp1_340[] = { 0xa3, 0x10, 0xda, 0x66, 0x6b, 0x93, 0x5c, 0x55, 0x38, 0x50, 0x39, 0x51, 0x98, 0x86, 0x5d, 0x06, 0x7c, 0xea }; - uint8_t expected_unknown_resp1_342[] = { 0xa3, 0x10, 0xb3, 0x92, 0x7b, 0xd8, 0x6b, 0xca, 0xa5, 0xab, 0x42, 0x6e, 0xda, 0xcd, 0x9d, 0xf1, 0x31, 0x2f }; - uint8_t unknown_resp1[sizeof(expected_unknown_resp1_340)]; - uint8_t *expected_unknown_resp1; - uint8_t *unknown_cmd1; + devc = sdi->priv; - uint8_t unknown_cmd2[] = { 0xa3, 0x01, 0xca }; - uint8_t expected_unknown_resp2[] = { 0xa3, 0x08, 0x06, 0x83, 0x96, 0x29, 0x15, 0xe1, 0x92, 0x74, 0x00, 0x00 }; - uint8_t unknown_resp2[sizeof(expected_unknown_resp2)]; + logic.unitsize = 2; + logic.data = devc->convbuffer; - devc = sdi->priv; + sr_packet.type = SR_DF_LOGIC; + sr_packet.payload = &logic; - if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, &i1, sizeof(i1))) != SR_OK) { - sr_err("failed to read i1"); - return ret; + max_samples = devc->convbuffer_size / 2; + n_samples = 0; + wp = (uint16_t *)devc->convbuffer; + total_samples = 0; + do_signal_trigger = 0; + + if (devc->had_triggers_configured && devc->reading_behind_trigger == 0 && devc->info.n_rep_packets_before_trigger == 0) { + std_session_send_df_trigger(sdi); + devc->reading_behind_trigger = 1; } - sr_dbg("i1: 0x%08x", i1); - if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &i2, sizeof(i2))) != SR_OK) { - sr_err("failed to read i2"); - return ret; + rp = packets; + for (i = 0; i < num_tfers; i++) { + for (k = 0; k < NUM_PACKETS_IN_CHUNK; k++) { + free_n_samples = max_samples - n_samples; + if (free_n_samples < 256 || do_signal_trigger) { + logic.length = n_samples * 2; + sr_session_send(sdi, &sr_packet); + n_samples = 0; + wp = (uint16_t *)devc->convbuffer; + if (do_signal_trigger) { + std_session_send_df_trigger(sdi); + do_signal_trigger = 0; + } + } + + state = read_u16le_inc(&rp); + repetitions = read_u8_inc(&rp); + for (j = 0; j < repetitions; j++) + *wp++ = state; + + n_samples += repetitions; + total_samples += repetitions; + devc->total_samples += repetitions; + if (!devc->reading_behind_trigger) { + devc->n_reps_until_trigger--; + if (devc->n_reps_until_trigger == 0) { + devc->reading_behind_trigger = 1; + do_signal_trigger = 1; + sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", + devc->total_samples, + (double)devc->total_samples / devc->cur_samplerate * 1e3); + } + } + } + (void)read_u8_inc(&rp); /* Skip sequence number. */ + } + if (n_samples) { + logic.length = n_samples * 2; + sr_session_send(sdi, &sr_packet); + if (do_signal_trigger) { + std_session_send_df_trigger(sdi); + } } - sr_dbg("i2: 0x%08x, 0x%08x", i2[0], i2[1]); + sr_dbg("Send_chunk done after %u samples.", total_samples); +} - if ((ret = upload_fpga_bitstream(sdi)) != SR_OK) { - sr_err("failed to upload fpga bitstream"); - return ret; +static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) +{ + struct sr_dev_inst *sdi; + struct dev_context *devc; + struct sr_usb_dev_inst *usb; + int ret; + + sdi = transfer->user_data; + devc = sdi->priv; + usb = sdi->conn; + + sr_dbg("receive_transfer(): status %s received %d bytes.", + libusb_error_name(transfer->status), transfer->actual_length); + + if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) { + sr_err("USB bulk transfer timeout."); + devc->transfer_finished = 1; + } + send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH); + + devc->n_bytes_to_read -= transfer->actual_length; + if (devc->n_bytes_to_read) { + uint32_t to_read = devc->n_bytes_to_read; + /* + * Determine read size for the next USB transfer. Make + * the buffer size a multiple of the endpoint packet + * size. Don't exceed a maximum value. + */ + if (to_read >= LA2016_USB_BUFSZ) + to_read = LA2016_USB_BUFSZ; + else + to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); + libusb_fill_bulk_transfer( + transfer, usb->devhdl, + 0x86, transfer->buffer, to_read, + receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); + + if ((ret = libusb_submit_transfer(transfer)) == 0) + return; + sr_err("Cannot submit another USB transfer: %s.", + libusb_error_name(ret)); } - if (run_state(sdi) == 0xffff) { - sr_err("run_state after fpga bitstream upload is 0xffff!"); - return SR_ERR; + g_free(transfer->buffer); + libusb_free_transfer(transfer); + devc->transfer_finished = 1; +} + +SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) +{ + const struct sr_dev_inst *sdi; + struct dev_context *devc; + struct drv_context *drvc; + struct timeval tv; + + (void)fd; + (void)revents; + + sdi = cb_data; + devc = sdi->priv; + drvc = sdi->driver->context; + + if (devc->have_trigger == 0) { + if (la2016_has_triggered(sdi) == 0) { + /* Not yet ready for sample data download. */ + return TRUE; + } + devc->have_trigger = 1; + devc->transfer_finished = 0; + devc->reading_behind_trigger = 0; + devc->total_samples = 0; + /* We can start downloading sample data. */ + if (la2016_start_retrieval(sdi, receive_transfer) != SR_OK) { + sr_err("Cannot start acquisition data download."); + return FALSE; + } + sr_dbg("Acquisition data download started."); + std_session_send_df_frame_begin(sdi); + + return TRUE; + } + + tv.tv_sec = tv.tv_usec = 0; + libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); + + if (devc->transfer_finished) { + sr_dbg("Download finished, post processing."); + std_session_send_df_frame_end(sdi); + + usb_source_remove(sdi->session, drvc->sr_ctx); + std_session_send_df_end(sdi); + + la2016_stop_acquisition(sdi); + + g_free(devc->convbuffer); + devc->convbuffer = NULL; + + devc->transfer = NULL; + + sr_dbg("Download finished, done post processing."); } - if (devc->bitstream_size == 0x2b602) { - // v3.4.0 - unknown_cmd1 = unknown_cmd1_340; - expected_unknown_resp1 = expected_unknown_resp1_340; + return TRUE; +} + +SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) +{ + struct dev_context *devc; + uint16_t state; + uint8_t buf[8]; + int16_t purchase_date_bcd[2]; + uint8_t magic; + const char *bitstream_fn; + int ret; + + devc = sdi->priv; + + /* + * Four EEPROM bytes at offset 0x20 are purchase year and month + * in BCD format, with 16bit complemented checksum. For example + * 20 04 df fb translates to 2020-04. This can help identify the + * age of devices when unknown magic numbers are seen. + */ + if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) { + sr_err("Cannot read purchase date in EEPROM."); } else { - // v3.4.2 - if (devc->bitstream_size != 0x2b839) - sr_warn("the FPGA bitstream size %d is unknown. tested bistreams from vendor's version 3.4.0 and 3.4.2\n", devc->bitstream_size); - unknown_cmd1 = unknown_cmd1_342; - expected_unknown_resp1 = expected_unknown_resp1_342; + sr_dbg("Purchase date: 20%02hx-%02hx.", + (purchase_date_bcd[0]) & 0xff, + (purchase_date_bcd[0] >> 8) & 0xff); + if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) { + sr_err("Purchase date fails checksum test."); + } } - if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1_340))) != SR_OK) { - sr_err("failed to send unknown_cmd1"); + + /* + * Several Kingst logic analyzer devices share the same USB VID + * and PID. The product ID determines which MCU firmware to load. + * The MCU firmware provides access to EEPROM content which then + * allows to identify the device model. Which in turn determines + * which FPGA bitstream to load. Eight bytes at offset 0x08 are + * to get inspected. + * + * EEPROM content for model identification is kept redundantly + * in memory. The values are stored in verbatim and in inverted + * form, multiple copies are kept at different offsets. Example + * data: + * + * magic 0x08 + * | ~magic 0xf7 + * | | + * 08f7000008f710ef + * | | + * | ~magic backup + * magic backup + * + * Exclusively inspecting the magic byte appears to be sufficient, + * other fields seem to be 'don't care'. + * + * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" + * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" + * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" + * (latest v1.3.0 PCB, perhaps others) + * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" + * (latest v1.3.0 PCB, perhaps others) + * + * When EEPROM content does not match the hardware configuration + * (the board layout), the software may load but yield incorrect + * results (like swapped channels). The FPGA bitstream itself + * will authenticate with IC U10 and fail when its capabilities + * do not match the hardware model. An LA1016 won't become a + * LA2016 by faking its EEPROM content. + */ + if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) { + sr_err("Cannot read EEPROM device identifier bytes."); return ret; } - g_usleep(80 * 1000); - if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) { - sr_err("failed to read unknown_resp1"); - return ret; + + magic = 0; + if (buf[0] == (0xff & ~buf[1])) { + /* Primary copy of magic passes complement check. */ + magic = buf[0]; + } else if (buf[4] == (0xff & ~buf[5])) { + /* Backup copy of magic passes complement check. */ + sr_dbg("Using backup copy of device type magic number."); + magic = buf[4]; } - if (memcmp(unknown_resp1, expected_unknown_resp1, sizeof(unknown_resp1))) - sr_dbg("unknown_cmd1 response is not as expected, this is to be expected..."); - state = run_state(sdi); - if (state != 0x85e9) - sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state); + sr_dbg("Device type: magic number is %hhu.", magic); + + /* Select the FPGA bitstream depending on the model. */ + switch (magic) { + case 2: + bitstream_fn = FPGA_FW_LA2016; + devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; + break; + case 3: + bitstream_fn = FPGA_FW_LA1016; + devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; + break; + case 8: + bitstream_fn = FPGA_FW_LA2016A; + devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; + break; + case 9: + bitstream_fn = FPGA_FW_LA1016A; + devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; + break; + default: + bitstream_fn = NULL; + break; + } + if (!bitstream_fn || !*bitstream_fn) { + sr_err("Cannot identify as one of the supported models."); + return SR_ERR; + } - if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) { - sr_err("failed to send unknown_cmd2"); - return ret; + if (check_fpga_bitstream(sdi) != SR_OK) { + ret = upload_fpga_bitstream(sdi, bitstream_fn); + if (ret != SR_OK) { + sr_err("Cannot upload FPGA bitstream."); + return ret; + } } - g_usleep(80 * 1000); - if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) { - sr_err("failed to read unknown_resp2"); + ret = enable_fpga_bitstream(sdi); + if (ret != SR_OK) { + sr_err("Cannot enable FPGA bitstream after upload."); return ret; } - if (memcmp(unknown_resp2, expected_unknown_resp2, sizeof(unknown_resp2))) - sr_dbg("unknown_cmd2 response is not as expected!"); + + state = run_state(sdi); + if (state != 0x85e9) { + sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state); + } if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { - sr_err("failed to send unknown_cmd3"); + sr_err("Cannot reset USB bulk transfer."); return ret; } - sr_dbg("device should be initialized"); + + sr_dbg("Device should be initialized."); return set_defaults(sdi); } @@ -758,7 +1201,7 @@ SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) int ret; if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) { - sr_err("failed to send deinit command"); + sr_err("Cannot deinitialize device's FPGA."); return ret; }