X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fkingst-la2016%2Fprotocol.c;h=8602147badc8655c8f01c5b5cce15219d479c976;hb=b1a17c1a20261612864bc262ab846dfa0e8d0b41;hp=69ec4042f15626c78052989b55c64f144a81b860;hpb=91f738728dd0cff2f2a37626e103773663b9c88c;p=libsigrok.git diff --git a/src/hardware/kingst-la2016/protocol.c b/src/hardware/kingst-la2016/protocol.c index 69ec4042..8602147b 100644 --- a/src/hardware/kingst-la2016/protocol.c +++ b/src/hardware/kingst-la2016/protocol.c @@ -34,51 +34,82 @@ #define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream" #define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream" +/* Maximum device capabilities. May differ between models. */ #define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200) #define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100) #define MAX_SAMPLE_DEPTH 10e9 #define MAX_PWM_FREQ SR_MHZ(20) #define PWM_CLOCK SR_MHZ(200) /* 200MHz for both LA2016 and LA1016 */ -/* usb vendor class control requests to the cypress FX2 microcontroller */ +/* + * Default device configuration. Must be applicable to any of the + * supported devices (no model specific default values yet). Specific + * firmware implementation details unfortunately won't let us detect + * and keep using previously configured values. + */ +#define LA2016_DFLT_SAMPLERATE SR_MHZ(100) +#define LA2016_DFLT_SAMPLEDEPTH (5 * 1000 * 1000) +#define LA2016_DFLT_CAPT_RATIO 5 /* Capture ratio, in percent. */ + +/* TODO + * What is the origin and motivation of that 128Mi literal? What is its + * unit? How does it relate to a device's hardware capabilities? How to + * map the 1GiB of RAM of an LA2016 (at 16 channels) to the 128Mi value? + * It cannot be sample count. Is it memory size in bytes perhaps? + */ +#define LA2016_PRE_MEM_LIMIT_BASE (128 * 1024 * 1024) + +/* USB vendor class control requests, executed by the Cypress FX2 MCU. */ #define CMD_FPGA_ENABLE 0x10 -#define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */ -#define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */ -#define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */ -#define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */ -#define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */ -#define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */ +#define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ +#define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ +#define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ +#define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ +#define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ +#define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ /* - * fpga spi register addresses for control request CMD_FPGA_SPI: - * There are around 60 byte-wide registers within the fpga and - * these are the base addresses used for accessing them. - * On the spi bus, the msb of the address byte is set for read - * and cleared for write, but that is handled by the fx2 mcu - * as appropriate. In this driver code just use IN transactions - * to read, OUT to write. + * FPGA register addresses (base addresses when registers span multiple + * bytes, in that case data is kept in little endian format). Passed to + * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail + * of SPI transfers encoding the read (1) or write (0) direction in the + * MSB of the address field. There are some 60 byte-wide FPGA registers. + * + * Unfortunately the FPGA registers change their meaning between the + * read and write directions of access, or exclusively provide one of + * these directions and not the other. This is an arbitrary vendor's + * choice, there is nothing which the sigrok driver could do about it. + * Values written to registers typically cannot get read back, neither + * verified after writing a configuration, nor queried upon startup for + * automatic detection of the current configuration. Neither appear to + * be there echo registers for presence and communication checks, nor + * version identifying registers, as far as we know. */ -#define REG_RUN 0x00 /* read capture status, write capture start */ -#define REG_PWM_EN 0x02 /* user pwm channels on/off */ -#define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */ -#define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */ -#define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */ -#define REG_TRIGGER 0x20 /* write level and edge trigger config */ -#define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */ -#define REG_PWM1 0x70 /* write config for user pwm1 */ -#define REG_PWM2 0x78 /* write config for user pwm2 */ +#define REG_RUN 0x00 /* Read capture status, write start capture. */ +#define REG_PWM_EN 0x02 /* User PWM channels on/off. */ +#define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ +#define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ +#define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ +#define REG_TRIGGER 0x20 /* write level and edge trigger config. */ +#define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ +#define REG_PWM1 0x70 /* Write config for user PWM1. */ +#define REG_PWM2 0x78 /* Write config for user PWM2. */ + +/* Bit patterns to write to REG_RUN, setup run mode. */ +#define RUNMODE_HALT 0x00 +#define RUNMODE_RUN 0x03 static int ctrl_in(const struct sr_dev_inst *sdi, - uint8_t bRequest, uint16_t wValue, uint16_t wIndex, - void *data, uint16_t wLength) + uint8_t bRequest, uint16_t wValue, uint16_t wIndex, + void *data, uint16_t wLength) { struct sr_usb_dev_inst *usb; int ret; usb = sdi->conn; - if ((ret = libusb_control_transfer( - usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, + if ((ret = libusb_control_transfer(usb->devhdl, + LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, bRequest, wValue, wIndex, (unsigned char *)data, wLength, DEFAULT_TIMEOUT_MS)) != wLength) { sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", @@ -93,16 +124,16 @@ static int ctrl_in(const struct sr_dev_inst *sdi, } static int ctrl_out(const struct sr_dev_inst *sdi, - uint8_t bRequest, uint16_t wValue, uint16_t wIndex, - void *data, uint16_t wLength) + uint8_t bRequest, uint16_t wValue, uint16_t wIndex, + void *data, uint16_t wLength) { struct sr_usb_dev_inst *usb; int ret; usb = sdi->conn; - if ((ret = libusb_control_transfer( - usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, + if ((ret = libusb_control_transfer(usb->devhdl, + LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, bRequest, wValue, wIndex, (unsigned char*)data, wLength, DEFAULT_TIMEOUT_MS)) != wLength) { sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", @@ -116,22 +147,92 @@ static int ctrl_out(const struct sr_dev_inst *sdi, return SR_OK; } -static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bitstream_fname) +/* + * Check the necessity for FPGA bitstream upload, because another upload + * would take some 600ms which is undesirable after program startup. Try + * to access some FPGA registers and check the values' plausibility. The + * check should fail on the safe side, request another upload when in + * doubt. A positive response (the request to continue operation with the + * currently active bitstream) should be conservative. Accessing multiple + * registers is considered cheap compared to the cost of bitstream upload. + * + * It helps though that both the vendor software and the sigrok driver + * use the same bundle of MCU firmware and FPGA bitstream for any of the + * supported models. We don't expect to successfully communicate to the + * device yet disagree on its protocol. Ideally we would access version + * identifying registers for improved robustness, but are not aware of + * any. A bitstream reload can always be forced by a power cycle. + */ +static int check_fpga_bitstream(const struct sr_dev_inst *sdi) +{ + uint8_t init_rsp; + int ret; + uint16_t run_state; + uint8_t pwm_en; + size_t read_len; + uint8_t buff[sizeof(run_state)]; + const uint8_t *rdptr; + + sr_dbg("Checking operation of the FPGA bitstream."); + + init_rsp = ~0; + ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); + if (ret != SR_OK || init_rsp != 0) { + sr_dbg("FPGA init query failed, or unexpected response."); + return SR_ERR_IO; + } + + read_len = sizeof(run_state); + ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); + if (ret != SR_OK) { + sr_dbg("FPGA register access failed (run state)."); + return SR_ERR_IO; + } + rdptr = buff; + run_state = read_u16le_inc(&rdptr); + sr_spew("FPGA register: run state 0x%04x.", run_state); + if (run_state && (run_state & 0x3) != 0x1) { + sr_dbg("Unexpected FPGA register content (run state)."); + return SR_ERR_DATA; + } + if (run_state && (run_state & ~0xf) != 0x85e0) { + sr_dbg("Unexpected FPGA register content (run state)."); + return SR_ERR_DATA; + } + + read_len = sizeof(pwm_en); + ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); + if (ret != SR_OK) { + sr_dbg("FPGA register access failed (PWM enable)."); + return SR_ERR_IO; + } + rdptr = buff; + pwm_en = read_u8_inc(&rdptr); + sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); + if ((pwm_en & 0x3) != 0x0) { + sr_dbg("Unexpected FPGA register content (PWM enable)."); + return SR_ERR_DATA; + } + + sr_info("Could re-use current FPGA bitstream. No upload required."); + return SR_OK; +} + +static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, + const char *bitstream_fname) { - struct dev_context *devc; struct drv_context *drvc; struct sr_usb_dev_inst *usb; struct sr_resource bitstream; + uint32_t bitstream_size; uint8_t buffer[sizeof(uint32_t)]; uint8_t *wrptr; - uint8_t cmd_resp; uint8_t block[4096]; int len, act_len; unsigned int pos; int ret; - unsigned int zero_pad_to = 0x2c000; + unsigned int zero_pad_to; - devc = sdi->priv; drvc = sdi->driver->context; usb = sdi->conn; @@ -143,14 +244,18 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bits return ret; } - devc->bitstream_size = (uint32_t)bitstream.size; + bitstream_size = (uint32_t)bitstream.size; wrptr = buffer; - write_u32le_inc(&wrptr, devc->bitstream_size); + write_u32le_inc(&wrptr, bitstream_size); if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) { sr_err("Cannot initiate FPGA bitstream upload."); sr_resource_close(drvc->sr_ctx, &bitstream); return ret; } + zero_pad_to = bitstream_size; + zero_pad_to += LA2016_EP2_PADDING - 1; + zero_pad_to /= LA2016_EP2_PADDING; + zero_pad_to *= LA2016_EP2_PADDING; pos = 0; while (1) { @@ -162,7 +267,7 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bits return SR_ERR; } } else { - // fill with zero's until zero_pad_to + /* Zero-pad until 'zero_pad_to'. */ len = zero_pad_to - pos; if ((unsigned)len > sizeof(block)) len = sizeof(block); @@ -171,7 +276,8 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bits if (len == 0) break; - ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS); + ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM, + &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); if (ret != 0) { sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", pos, (int)len, libusb_error_name(ret)); @@ -192,6 +298,14 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bits sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size); + return SR_OK; +} + +static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) +{ + int ret; + uint8_t cmd_resp; + if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) { sr_err("Cannot read response after FPGA bitstream upload."); return ret; @@ -201,15 +315,14 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bits cmd_resp); return SR_ERR; } - - g_usleep(30000); + g_usleep(30 * 1000); if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) { sr_err("Cannot enable FPGA after bitstream upload."); return ret; } + g_usleep(40 * 1000); - g_usleep(40000); return SR_OK; } @@ -220,51 +333,43 @@ static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) devc = sdi->priv; - uint16_t duty_R79,duty_R56; + uint16_t duty_R79, duty_R56; uint8_t buf[2 * sizeof(uint16_t)]; uint8_t *wrptr; - /* clamp threshold setting within valid range for LA2016 */ + /* Clamp threshold setting to valid range for LA2016. */ if (voltage > 4.0) { voltage = 4.0; - } - else if (voltage < -4.0) { + } else if (voltage < -4.0) { voltage = -4.0; } /* - * The fpga has two programmable pwm outputs which feed a dac that - * is used to adjust input offset. The dac changes the input - * swing around the fixed fpga input threshold. - * The two pwm outputs can be seen on R79 and R56 respectvely. - * Frequency is fixed at 100kHz and duty is varied. - * The R79 pwm uses just three settings. - * The R56 pwm varies with required threshold and its behaviour - * also changes depending on the setting of R79 PWM. - */ - - /* - * calculate required pwm duty register values from requested threshold voltage - * see last page of schematic (on wiki) for an explanation of these numbers + * Two PWM output channels feed one DAC which generates a bias + * voltage, which offsets the input probe's voltage level, and + * in combination with the FPGA pins' fixed threshold result in + * a programmable input threshold from the user's perspective. + * The PWM outputs can be seen on R79 and R56 respectively, the + * frequency is 100kHz and the duty cycle varies. The R79 PWM + * uses three discrete settings. The R56 PWM varies with desired + * thresholds and depends on the R79 PWM configuration. See the + * schematics comments which discuss the formulae. */ if (voltage >= 2.9) { - duty_R79 = 0; /* this pwm is off (0V)*/ + duty_R79 = 0; /* PWM off (0V). */ duty_R56 = (uint16_t)(302 * voltage - 363); - } - else if (voltage <= -0.4) { - duty_R79 = 0x02D7; /* 72% duty */ - duty_R56 = (uint16_t)(302 * voltage + 1090); - } - else { - duty_R79 = 0x00f2; /* 25% duty */ + } else if (voltage > -0.4) { + duty_R79 = 0x00f2; /* 25% duty cycle. */ duty_R56 = (uint16_t)(302 * voltage + 121); + } else { + duty_R79 = 0x02d7; /* 72% duty cycle. */ + duty_R56 = (uint16_t)(302 * voltage + 1090); } - /* clamp duty register values at sensible limits */ + /* Clamp duty register values to sensible limits. */ if (duty_R56 < 10) { duty_R56 = 10; - } - else if (duty_R56 > 1100) { + } else if (duty_R56 > 1100) { duty_R56 = 1100; } @@ -309,7 +414,8 @@ static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) return SR_OK; } -static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty) +static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, + float freq, float duty) { int CTRL_PWM[] = { REG_PWM1, REG_PWM2 }; struct dev_context *devc; @@ -321,7 +427,7 @@ static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, flo devc = sdi->priv; - if (which < 1 || which > 2) { + if (which < 1 || which > ARRAY_SIZE(CTRL_PWM)) { sr_err("Invalid PWM channel: %d.", which); return SR_ERR; } @@ -361,10 +467,10 @@ static int set_defaults(const struct sr_dev_inst *sdi) devc = sdi->priv; - devc->capture_ratio = 5; /* percent */ + devc->capture_ratio = LA2016_DFLT_CAPT_RATIO; devc->cur_channels = 0xffff; - devc->limit_samples = 5000000; - devc->cur_samplerate = SR_MHZ(100); + devc->limit_samples = LA2016_DFLT_SAMPLEDEPTH; + devc->cur_samplerate = LA2016_DFLT_SAMPLERATE; ret = set_threshold_voltage(sdi, devc->threshold_voltage); if (ret) @@ -374,11 +480,11 @@ static int set_defaults(const struct sr_dev_inst *sdi) if (ret) return ret; - ret = set_pwm(sdi, 1, 1e3, 50); + ret = set_pwm(sdi, 1, SR_KHZ(1), 50); if (ret) return ret; - ret = set_pwm(sdi, 2, 100e3, 50); + ret = set_pwm(sdi, 2, SR_KHZ(100), 50); if (ret) return ret; @@ -467,6 +573,12 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) write_u32le_inc(&wrptr, cfg.enabled); write_u32le_inc(&wrptr, cfg.level); write_u32le_inc(&wrptr, cfg.high_or_falling); + /* TODO + * Comment on this literal 16. Origin, meaning? Cannot be the + * register offset, nor the transfer length. Is it a channels + * count that is relevant for 16 and 32 channel models? Is it + * an obsolete experiment? + */ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); if (ret != SR_OK) { sr_err("Cannot setup trigger configuration."); @@ -480,14 +592,14 @@ static int set_sample_config(const struct sr_dev_inst *sdi) { struct dev_context *devc; double clock_divisor; - uint64_t total; - int ret; - uint16_t divisor; - uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)]; + uint16_t divider_u16; + uint64_t pre_trigger_samples; + uint64_t pre_trigger_memory; + uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ uint8_t *wrptr; + int ret; devc = sdi->priv; - total = 128 * 1024 * 1024; if (devc->cur_samplerate > devc->max_samplerate) { sr_err("Too high a sample rate: %" PRIu64 ".", @@ -496,10 +608,10 @@ static int set_sample_config(const struct sr_dev_inst *sdi) } clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; - if (clock_divisor > 0xffff) - clock_divisor = 0xffff; - divisor = (uint16_t)(clock_divisor + 0.5); - devc->cur_samplerate = devc->max_samplerate / divisor; + if (clock_divisor > 65535) + return SR_ERR_ARG; + divider_u16 = (uint16_t)(clock_divisor + 0.5); + devc->cur_samplerate = devc->max_samplerate / divider_u16; if (devc->limit_samples > MAX_SAMPLE_DEPTH) { sr_err("Too high a sample depth: %" PRIu64 ".", @@ -507,21 +619,47 @@ static int set_sample_config(const struct sr_dev_inst *sdi) return SR_ERR; } - devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100; + /* + * The acquisition configuration communicates "pre-trigger" + * specs in several formats. sigrok users provide a percentage + * (0-100%), which translates to a pre-trigger samples count + * (assuming that a total samples count limit was specified). + * The device supports hardware compression, which depends on + * slowly changing input data to be effective. Fast changing + * input data may occupy more space in sample memory than its + * uncompressed form would. This is why a third parameter can + * limit the amount of sample memory to use for pre-trigger + * data. Only the upper 24 bits of that memory size spec get + * communicated to the device (written to its FPGA register). + */ + pre_trigger_samples = devc->limit_samples * devc->capture_ratio / 100; + pre_trigger_memory = LA2016_PRE_MEM_LIMIT_BASE; + pre_trigger_memory *= devc->capture_ratio; + pre_trigger_memory /= 100; - sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples, trigger-pos %" PRIu64 "%%.", - devc->cur_samplerate / 1000, - devc->limit_samples, - devc->capture_ratio); + sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples.", + devc->cur_samplerate / 1000, devc->limit_samples); + sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".", + devc->capture_ratio, pre_trigger_samples, pre_trigger_memory); + /* + * The acquisition configuration occupies a total of 16 bytes: + * - A 34bit total samples count limit (up to 10 billions) that + * is kept in a 40bit register. + * - A 34bit pre-trigger samples count limit (up to 10 billions) + * in another 40bit register. + * - A 32bit pre-trigger memory space limit (in bytes) of which + * the upper 24bits are kept in an FPGA register. + * - A 16bit clock divider which gets applied to the maximum + * samplerate of the device. + * - An 8bit register of unknown meaning. Currently always 0. + */ wrptr = buf; - write_u32le_inc(&wrptr, devc->limit_samples); - write_u8_inc(&wrptr, 0); - write_u32le_inc(&wrptr, devc->pre_trigger_size); - write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00); - write_u16le_inc(&wrptr, divisor); + write_u40le_inc(&wrptr, devc->limit_samples); + write_u40le_inc(&wrptr, pre_trigger_samples); + write_u24le_inc(&wrptr, pre_trigger_memory >> 8); + write_u16le_inc(&wrptr, divider_u16); write_u8_inc(&wrptr, 0); - ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); if (ret != SR_OK) { sr_err("Cannot setup acquisition configuration."); @@ -531,58 +669,60 @@ static int set_sample_config(const struct sr_dev_inst *sdi) return SR_OK; } -/* The run state is read from FPGA registers 1[hi-byte] and 0[lo-byte] - * and the bits are interpreted as follows: - * - * register 0: - * bit0 1= idle - * bit1 1= writing to sdram - * bit2 0= waiting_for_trigger 1=been_triggered - * bit3 0= pretrigger_sampling 1=posttrigger_sampling - * ...unknown... - * register 1: - * meaning of bits unknown (but vendor software reads this, so just do the same) +/* + * FPGA register REG_RUN holds the run state (u16le format). Bit fields + * of interest: + * bit 0: value 1 = idle + * bit 1: value 1 = writing to SDRAM + * bit 2: value 0 = waiting for trigger, 1 = trigger seen + * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling + * The meaning of other bit fields is unknown. * - * The run state values occur in this order: - * 0x85E2: pre-sampling (for samples before trigger position, capture ratio > 0%) - * 0x85EA: pre-sampling complete, now waiting for trigger (whilst sampling continuously) - * 0x85EE: running - * 0x85ED: idle + * Typical values in order of appearance during execution: + * 0x85e2: pre-sampling, samples before the trigger position, + * when capture ratio > 0% + * 0x85ea: pre-sampling complete, now waiting for the trigger + * (whilst sampling continuously) + * 0x85ee: trigger seen, capturing post-trigger samples, running + * 0x85ed: idle */ static uint16_t run_state(const struct sr_dev_inst *sdi) { - uint16_t state; - static uint16_t previous_state = 0; + static uint16_t previous_state; + int ret; + uint16_t state; + uint8_t buff[sizeof(state)]; + const uint8_t *rdptr; + const char *label; - if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) { + if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state))) != SR_OK) { sr_err("Cannot read run state."); return ret; } + rdptr = buff; + state = read_u16le_inc(&rdptr); - /* This function is called about every 50ms. - * To avoid filling the log file with redundant information during long captures, - * just print a log message if status has changed. + /* + * Avoid flooding the log, only dump values as they change. + * The routine is called about every 50ms. */ - if (state != previous_state) { previous_state = state; - if ((state & 0x0003) == 0x01) { - sr_dbg("Run state: 0x%04x (%s).", state, "idle"); - } - else if ((state & 0x000f) == 0x02) { - sr_dbg("Run state: 0x%04x (%s).", state, - "pre-trigger sampling"); - } - else if ((state & 0x000f) == 0x0a) { - sr_dbg("Run state: 0x%04x (%s).", state, - "sampling, waiting for trigger"); - } - else if ((state & 0x000f) == 0x0e) { - sr_dbg("Run state: 0x%04x (%s).", state, - "post-trigger sampling"); + if ((state & 0x3) == 0x1) { + label = "idle"; + } else if ((state & 0xf) == 0x2) { + label = "pre-trigger sampling"; + } else if ((state & 0xf) == 0xa) { + label = "sampling, waiting for trigger"; + } else if ((state & 0xf) == 0xe) { + label = "post-trigger sampling"; + } else { + label = NULL; } - else { + if (label && *label) { + sr_dbg("Run state: 0x%04x (%s).", state, label); + } else { sr_dbg("Run state: 0x%04x.", state); } } @@ -590,12 +730,23 @@ static uint16_t run_state(const struct sr_dev_inst *sdi) return state; } -static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking) +static int la2016_has_triggered(const struct sr_dev_inst *sdi) +{ + uint16_t state; + + state = run_state(sdi); + if ((state & 0x3) == 0x1) + return 1; + + return 0; +} + +static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode) { int ret; - if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) { - sr_err("Cannot configure run mode %d.", fast_blinking); + if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode))) != SR_OK) { + sr_err("Cannot configure run mode %d.", mode); return ret; } @@ -622,20 +773,22 @@ static int get_capture_info(const struct sr_dev_inst *sdi) devc->info.write_pos = read_u32le_inc(&rdptr); sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d.", - devc->info.n_rep_packets, devc->info.n_rep_packets, - devc->info.n_rep_packets_before_trigger, - devc->info.n_rep_packets_before_trigger, - devc->info.write_pos, devc->info.write_pos); - - if (devc->info.n_rep_packets % 5) { - sr_warn("Unexpected packets count %lu, not a multiple of 5.", - (unsigned long)devc->info.n_rep_packets); + devc->info.n_rep_packets, devc->info.n_rep_packets, + devc->info.n_rep_packets_before_trigger, + devc->info.n_rep_packets_before_trigger, + devc->info.write_pos, devc->info.write_pos); + + if (devc->info.n_rep_packets % NUM_PACKETS_IN_CHUNK) { + sr_warn("Unexpected packets count %lu, not a multiple of %d.", + (unsigned long)devc->info.n_rep_packets, + NUM_PACKETS_IN_CHUNK); } return SR_OK; } -SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) +SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, + libusb_device *dev, uint16_t product_id) { char fw_file[1024]; snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id); @@ -675,7 +828,7 @@ SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) { int ret; - ret = set_run_mode(sdi, 3); + ret = set_run_mode(sdi, RUNMODE_RUN); if (ret != SR_OK) return ret; @@ -686,7 +839,7 @@ static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) { int ret; - ret = set_run_mode(sdi, 0); + ret = set_run_mode(sdi, RUNMODE_HALT); if (ret != SR_OK) return ret; @@ -709,16 +862,8 @@ SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) return SR_OK; } -static int la2016_has_triggered(const struct sr_dev_inst *sdi) -{ - uint16_t state; - - state = run_state(sdi); - - return (state & 0x3) == 1; -} - -static int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) +static int la2016_start_retrieval(const struct sr_dev_inst *sdi, + libusb_transfer_cb_fn cb) { struct dev_context *devc; struct sr_usb_dev_inst *usb; @@ -740,7 +885,7 @@ static int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", - devc->n_transfer_packets_to_read, devc->read_pos); + devc->n_transfer_packets_to_read, devc->read_pos); if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { sr_err("Cannot reset USB bulk state."); @@ -760,11 +905,15 @@ static int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer return ret; } + /* + * Pick a buffer size for all USB transfers. The buffer size + * must be a multiple of the endpoint packet size. And cannot + * exceed a maximum value. + */ to_read = devc->n_bytes_to_read; - /* choose a buffer size for all of the usb transfers */ - if (to_read >= LA2016_USB_BUFSZ) - to_read = LA2016_USB_BUFSZ; /* multiple transfers */ - else /* one transfer, make buffer size some multiple of LA2016_EP6_PKTSZ */ + if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */ + to_read = LA2016_USB_BUFSZ; + else /* One transfer. */ to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); buffer = g_try_malloc(to_read); if (!buffer) { @@ -774,9 +923,9 @@ static int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer } devc->transfer = libusb_alloc_transfer(0); - libusb_fill_bulk_transfer( - devc->transfer, usb->devhdl, - 0x86, buffer, to_read, + libusb_fill_bulk_transfer(devc->transfer, + usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, + buffer, to_read, cb, (void *)sdi, DEFAULT_TIMEOUT_MS); if ((ret = libusb_submit_transfer(devc->transfer)) != 0) { @@ -799,22 +948,23 @@ static void send_chunk(struct sr_dev_inst *sdi, unsigned int max_samples, n_samples, total_samples, free_n_samples; unsigned int i, j, k; int do_signal_trigger; - uint16_t *wp; + uint8_t *wp; const uint8_t *rp; uint16_t state; uint8_t repetitions; + uint8_t sample_buff[sizeof(state)]; devc = sdi->priv; - logic.unitsize = 2; + logic.unitsize = sizeof(sample_buff); logic.data = devc->convbuffer; sr_packet.type = SR_DF_LOGIC; sr_packet.payload = &logic; - max_samples = devc->convbuffer_size / 2; + max_samples = devc->convbuffer_size / sizeof(sample_buff); n_samples = 0; - wp = (uint16_t *)devc->convbuffer; + wp = devc->convbuffer; total_samples = 0; do_signal_trigger = 0; @@ -831,7 +981,7 @@ static void send_chunk(struct sr_dev_inst *sdi, logic.length = n_samples * 2; sr_session_send(sdi, &sr_packet); n_samples = 0; - wp = (uint16_t *)devc->convbuffer; + wp = devc->convbuffer; if (do_signal_trigger) { std_session_send_df_trigger(sdi); do_signal_trigger = 0; @@ -840,8 +990,11 @@ static void send_chunk(struct sr_dev_inst *sdi, state = read_u16le_inc(&rp); repetitions = read_u8_inc(&rp); - for (j = 0; j < repetitions; j++) - *wp++ = state; + write_u16le((void *)&sample_buff, state); + for (j = 0; j < repetitions; j++) { + memcpy(wp, sample_buff, logic.unitsize); + wp += logic.unitsize; + } n_samples += repetitions; total_samples += repetitions; @@ -852,15 +1005,15 @@ static void send_chunk(struct sr_dev_inst *sdi, devc->reading_behind_trigger = 1; do_signal_trigger = 1; sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", - devc->total_samples, - (double)devc->total_samples / devc->cur_samplerate * 1e3); + devc->total_samples, + (double)devc->total_samples / devc->cur_samplerate * 1e3); } } } (void)read_u8_inc(&rp); /* Skip sequence number. */ } if (n_samples) { - logic.length = n_samples * 2; + logic.length = n_samples * logic.unitsize; sr_session_send(sdi, &sr_packet); if (do_signal_trigger) { std_session_send_df_trigger(sdi); @@ -881,7 +1034,7 @@ static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) usb = sdi->conn; sr_dbg("receive_transfer(): status %s received %d bytes.", - libusb_error_name(transfer->status), transfer->actual_length); + libusb_error_name(transfer->status), transfer->actual_length); if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) { sr_err("USB bulk transfer timeout."); @@ -892,14 +1045,18 @@ static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) devc->n_bytes_to_read -= transfer->actual_length; if (devc->n_bytes_to_read) { uint32_t to_read = devc->n_bytes_to_read; - /* determine read size for the next usb transfer */ + /* + * Determine read size for the next USB transfer. Make + * the buffer size a multiple of the endpoint packet + * size. Don't exceed a maximum value. + */ if (to_read >= LA2016_USB_BUFSZ) to_read = LA2016_USB_BUFSZ; - else /* last transfer, make read size some multiple of LA2016_EP6_PKTSZ */ + else to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); - libusb_fill_bulk_transfer( - transfer, usb->devhdl, - 0x86, transfer->buffer, to_read, + libusb_fill_bulk_transfer(transfer, + usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, + transfer->buffer, to_read, receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); if ((ret = libusb_submit_transfer(transfer)) == 0) @@ -929,14 +1086,14 @@ SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) if (devc->have_trigger == 0) { if (la2016_has_triggered(sdi) == 0) { - /* not yet ready for download */ + /* Not yet ready for sample data download. */ return TRUE; } devc->have_trigger = 1; devc->transfer_finished = 0; devc->reading_behind_trigger = 0; devc->total_samples = 0; - /* we can start retrieving data! */ + /* We can start downloading sample data. */ if (la2016_start_retrieval(sdi, receive_transfer) != SR_OK) { sr_err("Cannot start acquisition data download."); return FALSE; @@ -975,104 +1132,129 @@ SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) struct dev_context *devc; uint16_t state; uint8_t buf[8]; - int16_t purchase_date_bcd[2]; + const uint8_t *rdptr; + uint8_t date_yy, date_mm; + uint8_t dinv_yy, dinv_mm; uint8_t magic; + const char *bitstream_fn; int ret; devc = sdi->priv; - /* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit - * complemented checksum; e.g. 2004DFFB = 2020-April. - * This helps to identify the age of devices if unknown magic numbers occur. + /* + * Four EEPROM bytes at offset 0x20 are the manufacturing date, + * year and month in BCD format, followed by inverted values for + * consistency checks. For example bytes 20 04 df fb translate + * to 2020-04. This information can help identify the vintage of + * devices when unknown magic numbers are seen. */ - if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) { - sr_err("Cannot read purchase date in EEPROM."); - } - else { - sr_dbg("Purchase date: 20%02hx-%02hx.", - (purchase_date_bcd[0]) & 0xff, - (purchase_date_bcd[0] >> 8) & 0xff); - if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) { - sr_err("Purchase date fails checksum test."); - } + ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, buf, 4 * sizeof(uint8_t)); + if (ret != SR_OK) { + sr_err("Cannot read manufacture date in EEPROM."); + } else { + rdptr = &buf[0]; + date_yy = read_u8_inc(&rdptr); + date_mm = read_u8_inc(&rdptr); + dinv_yy = read_u8_inc(&rdptr); + dinv_mm = read_u8_inc(&rdptr); + sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm); + if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff) + sr_warn("Manufacture date fails checksum test."); } /* - * There are four known kingst logic analyser devices which use this same usb vid and pid: - * LA2016, LA1016 and the older revision of each of these. They all use the same hardware - * and the same FX2 mcu firmware but each requires a different fpga bitstream. They are - * differentiated by a 'magic' byte within the 8 bytes of EEPROM from address 0x08. - * For example; + * Several Kingst logic analyzer devices share the same USB VID + * and PID. The product ID determines which MCU firmware to load. + * The MCU firmware provides access to EEPROM content which then + * allows to identify the device model. Which in turn determines + * which FPGA bitstream to load. Eight bytes at offset 0x08 are + * to get inspected. * - * magic=0x08 - * | ~magic=0xf7 - * | | - * 08F7000008F710EF - * | | - * | ~magic-backup - * magic-backup + * EEPROM content for model identification is kept redundantly + * in memory. The values are stored in verbatim and in inverted + * form, multiple copies are kept at different offsets. Example + * data: * - * It seems that only these magic bytes are used, other bytes shown above are 'don't care'. - * Changing the magic byte on newer device to older magic causes OEM software to load - * the older fpga bitstream. The device then functions but has channels out of order. - * It's likely the bitstreams were changed to move input channel pins due to PCB changes. + * magic 0x08 + * | ~magic 0xf7 + * | | + * 08f7000008f710ef + * | | + * | ~magic backup + * magic backup * - * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) - * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) - * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" - * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" + * Exclusively inspecting the magic byte appears to be sufficient, + * other fields seem to be 'don't care'. * - * This was all determined by altering the eeprom contents of an LA2016 and LA1016 and observing - * the vendor software actions, either raising errors or loading specific bitstreams. + * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" + * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" + * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" + * (latest v1.3.0 PCB, perhaps others) + * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" + * (latest v1.3.0 PCB, perhaps others) * - * Note: - * An LA1016 cannot be converted to an LA2016 by changing the magic number - the bitstream - * will not authenticate with ic U10, which has different security coding for each device type. + * When EEPROM content does not match the hardware configuration + * (the board layout), the software may load but yield incorrect + * results (like swapped channels). The FPGA bitstream itself + * will authenticate with IC U10 and fail when its capabilities + * do not match the hardware model. An LA1016 won't become a + * LA2016 by faking its EEPROM content. */ - if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) { sr_err("Cannot read EEPROM device identifier bytes."); return ret; } - - magic = 0; - if (buf[0] == (0x0ff & ~buf[1])) { - /* primary copy of magic passes complement check */ + if ((buf[0] ^ buf[1]) == 0xff) { + /* Primary copy of magic passes complement check. */ + sr_dbg("Using primary copy of device type magic number."); magic = buf[0]; - } - else if (buf[4] == (0x0ff & ~buf[5])) { - /* backup copy of magic passes complement check */ + } else if ((buf[4] ^ buf[5]) == 0xff) { + /* Backup copy of magic passes complement check. */ sr_dbg("Using backup copy of device type magic number."); magic = buf[4]; + } else { + sr_err("Cannot find consistent device type identification."); + magic = 0; } - sr_dbg("Device type: magic number is %hhu.", magic); - /* select the correct fpga bitstream for this device */ + /* Select the FPGA bitstream depending on the model. */ switch (magic) { case 2: - ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016); + bitstream_fn = FPGA_FW_LA2016; devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; break; case 3: - ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016); + bitstream_fn = FPGA_FW_LA1016; devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; break; case 8: - ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A); + bitstream_fn = FPGA_FW_LA2016A; devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; break; case 9: - ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016A); + bitstream_fn = FPGA_FW_LA1016A; devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; break; default: + bitstream_fn = NULL; + break; + } + if (!bitstream_fn || !*bitstream_fn) { sr_err("Cannot identify as one of the supported models."); return SR_ERR; } + if (check_fpga_bitstream(sdi) != SR_OK) { + ret = upload_fpga_bitstream(sdi, bitstream_fn); + if (ret != SR_OK) { + sr_err("Cannot upload FPGA bitstream."); + return ret; + } + } + ret = enable_fpga_bitstream(sdi); if (ret != SR_OK) { - sr_err("Cannot upload FPGA bitstream."); + sr_err("Cannot enable FPGA bitstream after upload."); return ret; } @@ -1088,7 +1270,11 @@ SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) sr_dbg("Device should be initialized."); - return set_defaults(sdi); + ret = set_defaults(sdi); + if (ret != SR_OK) + return ret; + + return SR_OK; } SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi)